Beruflich Dokumente
Kultur Dokumente
CD4023BMS
CMOS NAND Gates
November 1994
Features
Pinouts
CD4011BMS
TOP VIEW
14 VDD
B 2
13 H
J = AB 3
12 G
K = CD 4
11 M = GH
C 5
10 L = EF
D 6
9 E
VSS 7
8 F
CD4012BMS
TOP VIEW
J = ABCD 1
Description
CD4011BMS - Quad 2 Input
14 VDD
A 2
13 K = EFGH
B 3
12 H
C 4
11 G
D 5
10 F
NC 6
9 E
VSS 7
8 NC
NC = NO CONNECTION
CD4023BMS
TOP VIEW
A 1
14 VDD
B 2
13 G
CD4011B
CD4012B
CD4023B
D 3
12 H
H4Q
H4H
H4Q
E 4
11 I
H1B
H1B
H1B
F 5
10 L = GHI
Ceramic Flatpack
H3W
H3W
H3W
K = DEF 6
VSS 7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
7-53
9 J = ABC
8 C
File Number
3079
J = AB
VDD
13
12
11
K = CD
14
L = EF
C
10
VSS
M = GH
CD4011BMS
J = ABCD
14
VDD
13
12
11
10
NC
NC
VSS
K = EFGH
NC = NO CONNECTION
CD4012BMS
14
VDD
13
12
11
10
L = GHI
F
VSS
K = DEF
J = ABC
CD4023BMS
7-54
Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . .
ja
jc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
IIL
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VDD = 20
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
MAX
+25
0.5
+125oC
50
-55oC
0.5
+25o
-100
nA
+125oC
-1000
nA
-55oC
-100
nA
+25oC
100
nA
+125oC
1000
nA
100
nA
50
mV
-55oC
Output Voltage
VOL15
1, 2, 3
Output Voltage
VOH15
1, 2, 3
VDD = 18V
IOL5
UNITS
oC
+25oC
0.53
mA
IOL10
+25oC
1.4
mA
IOL15
+25oC
3.5
mA
+25oC
-0.53
mA
+25oC
-1.8
mA
IOH5A
IOH5B
IOH10
+25oC
-1.4
mA
IOH15
+25oC
-3.5
mA
+25oC
-2.8
-0.7
+25oC
0.7
2.8
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
+25oC
+25oC
8A
+125oC
8B
-55oC
VIL
1, 2, 3
1.5
VIH
1, 2, 3
3.5
VIL
1, 2, 3
VIH
1, 2, 3
11
7-55
PARAMETER
Propagation Delay
Transition Time
SYMBOL
TPHL
TPLH
CONDITIONS (NOTE 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
9
10, 11
TTHL
TTLH
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
250
ns
338
ns
200
ns
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
1, 2
-55oC, +25oC
0.25
7.5
-55 C, +25 C
0.5
+125oC
15
0.5
+125 C
VDD = 10V, VIN = VDD or GND
1, 2
1, 2
-55oC,
+25oC
30
Output Voltage
VOL
1, 2
+25oC, +125oC,
-55oC
50
mV
Output Voltage
VOL
1, 2
+25oC, +125oC,
-55oC
50
mV
Output Voltage
VOH
1, 2
+25oC, +125oC,
-55oC
4.95
Output Voltage
VOH
1, 2
+25oC, +125oC,
-55oC
9.95
IOL5
1, 2
+125oC
0.36
mA
-55oC
0.64
mA
+125oC
0.9
mA
-55oC
1.6
mA
oC
+125
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
+125oC
2.4
mA
-55oC
4.2
mA
+125oC
-0.36
mA
-55oC
-0.64
mA
+125oC
-1.15
mA
-55oC
-2.0
mA
+125oC
-0.9
mA
-55oC
-1.6
mA
+125oC
-2.4
mA
-55oC
-4.2
mA
VIL
1, 2
+25oC, +125oC,
-55oC
VIH
1, 2
+25oC, +125oC,
-55oC
Propagation Delay
TPHL
TPLH
1, 2, 3
+25oC
120
ns
1, 2, 3
+25oC
90
ns
VDD = 10V
VDD = 15V
7-56
SYMBOL
Transition Time
TTHL
TTLH
Input Capacitance
CONDITIONS
VDD = 10V
VDD = 15V
CIN
Any Input
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
100
ns
1, 2, 3
+25 C
80
ns
1, 2
+25oC
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
N Threshold Voltage
VNTH
N Threshold Voltage
Delta
VNTH
P Threshold Voltage
VPTH
P Threshold Voltage
Delta
VPTH
Functional
CONDITIONS
NOTES
TEMPERATURE
UNITS
+25 C
2.5
1, 4
+25oC
-2.8
-0.2
1, 4
+25oC
1, 4
+25oC
0.2
2.8
1, 4
+25oC
+25oC
VOH >
VDD/2
VOL <
VDD/2
1, 2, 3, 4
+25oC
1.35 x
+25oC
Limit
ns
TPHL
TPLH
MAX
1, 4
MIN
VDD = 5V
SYMBOL
DELTA LIMIT
IDD
0.1A
IOL5
IOH5A
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
100% 5004
1, 7, 9, Deltas
100% 5004
Sample 5005
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
PDA (Note 1)
Final Test
Group A
7-57
GROUP A SUBGROUPS
Subgroup B-5
Sample 5005
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
CONFORMANCE GROUP
Group B
Group D
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TEST
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
OPEN
GROUND
VDD
9V -0.5V
50kHz
3, 4, 10, 11
1, 2, 5, 6, 8, 9, 12,
13
1, 13
2 - 5, 9 - 12
6, 9, 10
1 - 5, 8, 11 - 13
25kHz
3, 4, 10, 11
1, 2, 5 - 9, 12, 13
14
Static Burn-In
2 Note 1
3, 4, 10, 11
1, 2, 5, 6, 8, 9,
12 - 14
14
3, 4, 10, 11
1, 2, 5, 6, 8, 9,
12 - 14
Irradiation
Note 2
1, 6, 8, 13
2 - 5, 7, 9 - 12
14
Static Burn-In
2 Note 1
1, 6, 8, 13
2 - 5, 9 - 12, 14
6, 8
14
1, 6, 8, 13
2 - 5, 9 - 12, 14
Irradiation
Note 2
6, 9, 10
1 - 5, 7, 8, 11 - 13
14
Static Burn-In
2 Note 1
6, 9, 10
1 - 5, 8, 11 - 14
14
6, 9, 10
1 - 5, 8, 11 - 14
Irradiation
Note 2
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V 0.5V
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7-58
p
1*
(9, 5, 12)
p
p
2*
14
3*(1, 11)
n
(8, 6, 13)
VDD
p
VDD
4*(2, 12)
n
p
3 (10, 4, 11)
n
5*(8, 13)
VDD
n 6(9, 10)
VDD
7
VSS
VSS
VSS
VSS
1 OF 4 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
7
1 OF 3 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
3(1, 11)
1(8, 6,13)
3
2(9, 5, 12)
4(2, 12)
(10, 4, 11)
(9, 10)
LOGIC DIAGRAM
LOGIC DIAGRAM
5(8, 13)
CD4011BMS
CD4023BMS
14
2(12)
VDD
2*(12)
3(11)
p
n
1
(13)
4(10)
3*(11)
5(9)
LOGIC DIAGRAM
p
VDD
4*(10)
p
n
p
5*(9)
VSS
n
1
1 OF 2 GATES (NUMBERS
IN PARENTHESES ARE
TERMINAL NUMBERS FOR
OTHER GATES)
n
n
VSS
CD4012BMS
7-59
(13)
10V
10
5V
5
o
8 AMBIENT TEMPERATURE (TA) = +25 C
6
4
104 8
10V
6
4
10V
5V
103
8
6
4
2
102
8
6
4
CL = 50pF
CL = 15pF
10
2
10
15
INPUT VOLTAGE (VI) (V)
20
25
30
25
20
15
10V
10
5
5V
0
4 6 8
4 6 8
4 6 8
103
10
102
INPUT FREQUENCY (fI) (kHz)
104
4 68
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-10V
-15V
-10
-15
7-60
175
150
200
(Continued)
125
100
10V
75
50
15V
25
0
10
20
30
40
50
60
70
80
90
200
100
10V
15V
50
0
0
100
150
20
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
CD4011BMSH
CD4012BMSH
METALLIZATION:
PASSIVATION:
AL.
CD4023BMSH
7-61