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5

Fonseca 14.1" DIS Schematics Document

rPGA988A Mobile Arrandale


Intel Ibex Peak-M
C

2010-03-22
REV : -1
B

DY : Nopop Component
B_TPM:Use Lom TPM
C_TPM:Use China TPM
A

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Monday, March 22, 2010

Cover Page

Rev

-1

Fonseca 14.1" DIS


Sheet
1

of

89

Fonseca 14" DIS Block Diagram


D

Clock Generator
SLG8SP585VTR

Thermal & Fan


EMC4022

DDR III DIMM1


1333Mhz
18

DDR III DIMM2


1333Mhz
19

39

ATI M92LP-S2

PEG

Intel Mobile CPU

Channel A

gDDR3
800MHz

INPUTS

80,81,82,83

OUTPUTS

eDP

rPGA988A 8~14

+PWR_SRC

46

TPS51125

MAX4885EETG+

14.1" eDP-LCD

+VCC_CORE

SYSTEM DC/DC

CRT
VSW

INPUTS

CRT CONN

75

OUTPUTS
+3.3V_ALW

55

+PWR_SRC

DMIx4

+5V_ALW

BL Converter

BTO(1)

54

Smart CARD
Socket

O2
OZ77CR6

67

BTO(2)

SYSTEM DC/DC

Display Port (C)

USB2.0
34

47

ISL62883

VRAM
64Mx16bx4 (512MB)
84,85
4

Arrandale
Channel B

Project name: DF3-14D


Project code: 91.4GQ01.001
PCB P/N
: 48.4GQ01.011
Revision
: 09281 - 1
CPU DC/DC

X1

Intel PCH

50

TPS51116

Display Port (B)

INPUTS

OUTPUTS

USB2.0

PC CARD
Socket

Ibex Peak-M
72

Ricoh
1394 Connector

PCIE
12 USB 2.0/1.1 ports

BTO(3)
Power SW(NewCard)

New Card
Connector

72

INT2

HDD CONN

LPC I/F

75

+1.8V_RUN

OP AMP

2CH
SPEAKER
(1W/1W)

SPI

Bluetooth (Option)

SYSTEM LDO

Module

RT9035

73

51

INPUTS

OUTPUTS

+3.3V_SUS

Camera (Option)

+1.8V_DELAY

60
Module

SPI FLASH
32Mb + 16Mb

USB2.0
63

MDC (Option)
Module
IO Board

62

76

73

LPC

FLASH
8Mb

36

76
IO Board

76

RJ45

76
IO Board

ESW

LPC

IO Board

BCM5761E

86

TPS51511

USB Port x 2
X2

LOM
35

SYSTEM DC/DC

RJ11

X2

TCM (Option)
ZTE, Jetway

INPUTS

OUTPUTS

+PWR_SRC

+VCC_GFX_CORE

1/2 Mini-Card

BATTERY CHARGER

WLAN Module

35

(AC, Battery Existence)

64

INPUTS

Int KB

BC

TouchPad
KSI/KSO
ECE1077

EC

PS2

MEC 5045
37

IO Board

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

38

Finger Printer
Title
AES2880 (Option)
78

Size
Document Number
Custom
Date:

+PBATT

<Core Design>

76

ECE 5028

FP Board

OUTPUTS

+DC_IN_SS

WWAN Module

SIO Expander
BC

68

45

TI BQ24745

64

Mini-Card
A

59

USB Port x 2

WLAN Switch

+3.3V_SUS

74

59

LPC

OUTPUTS

HP Jack

30

ODD CONN

INPUTS

INT1
20~28

51

RT9035
MIC Jack

IDT
92HD81

SMBus

SATA

+1.05V_VTT

SYSTEM LDO

HD AUDIO

PCI/PCI BRIDGE

SATA

OUTPUTS

TLV320AIC3004

Azalia
CODEC

ACPI 1.1

72

Free Fall Sensor


40
DE351DL

52

INPUTS
+PWR_SRC

4 SATA ports

PCIE

SATA

E/Family

73

Module

6 PCIE ports

USB2.0

TPS2231MRGPR

SYSTEM DC/DC

Docking

High Definition Audio


32

X2

Digital MIC

10/100/1000Mb ETHERNET

SD/SDHC/MMC
Socket
71

+0.75V_DDR_VTT

TPS51218

R5U242

71

+1.5V_SUS

+PWR_SRC

USB2.0
SATA
PCIE

Block Diagram

Thursday, March 18, 2010

Rev

Fonseca 14.1" DIS


Sheet
1

-1
of

89

Regulator
ADAPTER

LDO

ISL62883
47

+VCC_CORE47

Switch
BATTERY

+PWR_SRC

+3V_ALW_246

TPS51218

TPS51116

TPS51511 86

52

50

TPS51125

CHARGER
BQ24745

+5V_ALW_246

46

+1.05V_VTT

+GPU_CORE +1.1V_GFX_PCIE

52

86

+1.5V_SUS

86

+0.75V_DDR_VTT

50

50

SIR460DP
42

+5V_ALW

+3.3V_ALW

46

+1.5V_RUN
42

46

SI4800BDY
42

SI4800BDY
42

SI4800BDY
42

+15V_ALW

SI3456DDV
35

SI2301CDS
42

SI3456DDV
42

SI4800BDY
42

46

+3.3V_SUS

42

+3.3V_DELAY
42
+5V_MOD

42

+5V_RUN

+3.3V_RUN

42

42

+3.3V_LAN

35

RT9035
51

+1.5V_RUN_CPU
42

RT9035
51
SI3456DDV
42

+CAMERA_VDD73

+1.8V_RUN
51

NJT4030PT1G
35

+1.8V_DEALY
51

<Core Design>

Wistron Corporation

+1.2V_LOM 35

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

+3.3V_ALW_PCH 42

Title

Power Diagram

Size
Document Number
Custom
Date:
5

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

of

89

2.2K

2.2K
PCH_SMB_CLK
PCH_SMB_DATA

+3.3V_RUN
2.2K

2N7002
2N7002

202
200
202
200

PCH
ibex Peak-M
2.2K
C6
G8
G12

2.2K
+3.3V_ALW_PCH

H14
C8

PCH_SML0CLK
PCH_SML0DATA

+3.3V_ALW_PCH

DIMM A(DM1) SMB

Addr=[A0]

DIMM B(DM2) SMB

Addr=[A4]
D

53
51

XDP1

53
51

XDP2

Dummy

2.2K

E10

Dummy

2.2K
KBC_SCL1
KBC_SDA1

A5

+3.3V_ALW_PCH
14
13

2.2K

FFSensor
DE351DL

SMB Addr=[3A]

2.2K

B6

+3.3V_LAN
A50
B53

LAN_SMBCLK
LAN_SMBDAT

2.2K

2N7002
2N7002

LOM

A3
A4

BCM5761E

SMB Addr=[XX]

EC

Dummy
Dummy

MEC5045

2.2K

2.2K
+3.3V_ALW

A7
B7

2.2K

+3.3V_RUN
2.2K

2N7002
2N7002

CKG_SMBCLK
CKG_SMBDAT
2.2K

B4
A3

SMB Addr=[D2]

+3.3V_ALW

2.2K
DOCK_SMB_ALERT#

133

DOCK_SMB_CLK
DOCK_SMB_DAT

127
129
2.2K

Docking

SMB Addr=[C4/72/70/48]

2.2K
+3.3V_ALW

B5
A4

SLG8SP585VTR

10K
+3.3V_ALW

A2

CLK Gen

32
31

2.2K

+LCDVDD
2.2K

2N7002
2N7002

LCD_SMBCLK
LCD_SMBDAT

13
12

LCD Panel
(eDP Type)

SMB Addr=[XX]

2.2K
+3.3V_ALW
A56
B59

100 ohm

2.2K
PBAT_SMBCLK
PBAT_SMBDAT

3
4

100 ohm

2.2K

Battery
connector

SMB Addr=[XX]

+3.3V_ALW
B50
A47

2.2K
CHARGER_SMBCLK
CHARGER_SMBDAT

10
9
2.2K
2.2K

+3.3V_RUN
2N7002
2N7002

AUD_DOCK_SMBCLK
AUD_DOCK_SMBDAT

SMB Addr=[12]

2.2K
+3.3V_ALW

B49
B48

Charger
BQ24745RHDR

2.2K
8
9

ADC/DAC
TLV320AIC3004

SMB Addr=[30]
A

2.2K
+3.3V_ALW
A49
B52

2.2K
CARD_SMBCLK
CARD_SMBDAT

20
19

ExpressCard

<Core Design>

connector

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:

SMBus Diagram

Document Number

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

of

89

Audio Block Diagram


Thermal Block Diagram
D

AUD_EXT_MIC_L
HP0_PORT_A_L
AUD_EXT_MIC_R

MIC

HP0_PORT_A_R
AUD_VREFOUT_B

60

VREFOUT_A_OR_F

HP1_PORT_B_L
HP1_PORT_B_R

Earphone

AUD_HP_OUT_L
AUD_HP_OUT_R

60

DP1
MMBT3904-3-GP
SC470P50V3JN-2GP
DN1

CPU
PORT_C_L

PORT_C_R
DP2
VREFOUT_C

MMBT3904-3-GP
SC470P50V3JN-2GP

Thermal
EMC4022

DN2

Skin
Anti-Parallel Diodes

Codec
92HD81

DP3
MMBT3904-3-GP
SC470P50V3JN-2GP
DN3

VGA

SPKR_PORT_D_L+

AUD_SPK_L+

AUD_SPK_L+_R

SPKR_PORT_D_L-

AUD_SPK_L-

AUD_SPK_L-_R

SPKR_PORT_D_R-

AUD_SPK_R+

AUD_SPK_R+_R

SPKR_PORT_D_R+

AUD_SPK_R-

SPEAKER

DP4
MMBT3904-3-GP
SC470P50V3JN-2GP
DN4

60

AUD_SPK_R-_R

DIMM
Anti-Parallel Diodes

0R3-0-U-V-GP

DP5
PORT_E_L

AUD_DOCK_HP_OUT_L_C

PORT_E_R

AUD_DOCK_HP_OUT_R_C

PORT_F_L

AUD_DOCK_MIC_IN_L

PORT_F_R

AUD_DOCK_MIC_IN_R

75

DN5
SCD47U25V3KX-1GP

THERMTRIP1#

CPU_ThermalTrip

THERMTRIP2#

DOCKING
TLV320AIC3004

DAI_BCLK#

DOCK
HP

DAI_LRCK#
DAI_DO#
DAI_DI

DOCK
MIC

DMIC_CLK/GPIO1
DMIC0/GPIO2

0R2J-2-GP
AUD_DMIC_CLK

Digital
50
MIC

AUD_DMIC_CLK_G_C

AUD_DMIC_IN0

AUD_DMIC_IN0_C
33R2J-2-GP

74

SC1U16V3KX-2GP

PCH_ThermalTrip
THERMTRIP3#

+3.3V_SUS
<Core Design>
SC1U10V3KX-3GP

39

30

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

AUDIO/THERMAL Diagram

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

of

89

PCH Strapping
SPKR

Calpella Schematic Checklist Rev: 1.6

Reboot option at power-up


Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k ~ 10-k weak
pull-up resistor.

Processor Strapping
Calpella Schematic Checklist Rev: 1.6
Schematics Notes

Name

INIT3_3V#

Internal pull-up. Leave as "No Connect"

GNT3#/
GPIO55

Default Mode: Internal pull-up.


Low (0) = Top Block Swap Mode
Note: Connect to ground with 4.7-k weak pull-down resistor.
CRB uses a 1 k ; do not stuff resistor

INTVRMEN

High (1) = Integrated VRM is enabled


Low (0) = Integrated VRM is disabled
Note: CRB uses a 330-k resistor.

GNT0#,
GNT1#

Default (SPI): Leave both GNT0# and GNT1# floating. No pull up required

Pin Name

Strap Description

Configuration (Default value for each bit is


1 unless specified otherwise)

Default
Value

CFG[4]

Embedded
DisplayPort
Presence

1: Disabled - No Physical Display Port attached to


Embedded DisplayPort.
0: Enabled - An external Display Port device is
connected to the Embedded Display Port.
1: Normal Operation.
0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...

CFG[3]

PCI-Express Static
Lane Reversal

CFG[0]

PCI-Express
1: Single PCI-Express Graphics
Configuration Select 0: Bifurcation enabled

1
1

Boot from PCI: Connect GNT1# to ground with 1-k pull-down resistor.
Leave GNT0# Floating.
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k pull-down
resistor.
Default - Internal pull-up.
Low (0)= Configures DMI for ESI compatible operation (for servers only.
Not for mobile/desktops).

GNT2#/
GPIO53
C

SPI_MOSI

Enable Intel Anti-Theft Technology: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Intel Anti-Theft Technology:Left floating, no pull-down required.

NV_ALE

Enable Intel Anti-Theft Technology: Connect to +NVRAM_VCCQ with 8.2-k weak


pull-up resistor [CRB has it pulled up with 1-k no-stuff resistor]
Disable Intel Anti-Theft Technology: Leave floating (internal pull-down).

NV_CLE

DMI termination voltage. Weak internal pull-up. Do not pull low.

HDA_DOCK_EN#
/GPIO[33]

Low (0):

Flash Descriptor Security will be overridden.


Also, when this signals is sampled on the rising edge of PWROK then
it will also disable Intel ME and its features.

High (1): Security measure defined in the Flash Descriptor will be enabled.
Platform design should provide appropriate pull-up or pull-down
depending on the desired settings.
If a jumper option is used to tie this signal to GND as required by
the functional strap, the signal should be pulled low through a weak pull-down
in order to avoid asserting HDA_DOCK_EN# inadvertently.
Note:
CRB recommends 1-k pull-down for FD Override.
There is an internal pull-up of 20 k for HDA_DOCK_EN# which is only
enabled at boot/reset for strapping functions.

HDA_SDO

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

HDA_SYNC

Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.

PCIE Routing
LANE1
LANE2
LANE3
LANE4

- Intel ME Crypto Transport Layer Security TLS) cipher suite with no


confidentiality.
High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with
confidentiality.
Note:
This is an unmuxed signal.
This signal has a weak internal pull-down of 20K which is enabled when PWROK is
low.
Sampled at rising edge of RSMRST#.
CRB has a 1K pull-up on this signal to +3.3VA rail.

USB Routing
USB

WWAN

Pair

WLAN
PCMCIA
Express Card

Low (1)

GPIO15

GPIO8

Weak internal pull-up. Do not pull low. Sampled at rising edge of RSMRST#.

GPIO27

Default = Do not connect (floating). Internal pull-up.


High(1) = Enables the internal VccVRM to have a clean supply for analog rails.
No need to use on-board filter circuit.
Low (0) = Disables the VccVRM.
Need to use on-board filter circuits for analog rails.

LANE5

None

LANE6

10M/100M/1G LAN

LANE7

Not available for HM55

LANE8

Not available for HM55

Device

USB0 @ MB

USB1 @ MB

USB2 @ IO Board

USB3 @ IO Board

WLAN

Bluetooth

Not available for HM55

Not available for HM55

DOCKING PORT1

DOCKING PORT2

10

Finger Printer

11

Camera

12

PCCard/ SmartCard/ ExpCard

13

WWAN

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Table of Content

Document Number

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

of

89

SSID = CLOCK

+3.3V_RUN

+3.3V_RUN

2
1

37 CKG_SMBDAT
+3.3V_RUN

+3.3V_RUN_CLKGEN

C709
37 CKG_SMBCLK

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3
4

C708

C707

C706

C705

SCD1U16V2ZY-2GP

C704

DY
2

DY

SC1U10V2KX-1GP

DY

C703
SC10U10V5ZY-1GP

C702

RN702
SRN2K2J-1-GP

Q701

1 L702
2
0R0805-PAD-2-GP

DMN66D0LDW -7-GP

CLK_SDATA

R709
R710

+3.3V_RUN_CLKGEN

DY

DY

CLK_SCLK_HDDFALL

0R2J-2-GP

40

CLK_SDATA_HDDFALL

0R2J-2-GP

40

C712

+1.05V_RUN_CLKGEN_IO

C713

SRC_2#
SRC_2

11
10

SRC_1/SATA#
SRC_1/SATA

18

2
1

15

VDD_CPU_IO

29

17

VDD_SRC_IO

VDD_27

CLK_GPU27M_SS 81

CLK_GPU27M_NSS
CLK_GPU_27M_SS

CPU_STOP#
CKPWRGD/PD#
REF_0/CPU_SEL

16
25
30

CPU_STOP#
CK_PW RGD
FSC
CLK_XTAL_IN
CLK_XTAL_OUT

EC702
SC10P50V2JN-4GP

CLK_SDATA
CLK_SCLK

2
R704

1
10KR2J-3-GP

R705

CLK_PCH_14M 23

33R2J-2-GP

SDA
SCL

31
32

C714
SC4D7P50V2CN-1GP

For EMI

VSS_27
8

26

33

DY

VSS_SATA

CPU_1#
CPU_1
VSS_DOT

XTAL_IN
XTAL_OUT

19
20

VSS_SRC

CPU_0#
CPU_0

28
27

GND

22
23

12

CLK_CPU_BCLK#
CLK_CPU_BCLK

23 CLK_CPU_BCLK#
23 CLK_CPU_BCLK

EC703
SC10P50V2JN-4GP

+3.3V_RUN

VSS_CPU

CLK_PCIE_SATA#
CLK_PCIE_SATA

23 CLK_PCIE_SATA#
23 CLK_PCIE_SATA

27MHZ
SLG8SP585VTR-GP 27MHZ_SS

6
7

2
33R2J-2-GP

14
13

CLK_GPU27M_NSS 81

DOT_96#
DOT_96

CLKIN_DMI#
CLKIN_DMI

1
R703

4
3

21

23 CLKIN_DMI#
23 CLKIN_DMI

DREFCLK#
DREFCLK

VSS_REF

23 DREFCLK#
23 DREFCLK

VDD_DOT

-1.10/0310

VDD_REF

24
VDD_CPU

U701

VDD_SRC

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

Damping need to check


series resistance

-1.10/0310

DY
SC10U10V5ZY-1GP

C711

C710
SC1U10V2KX-1GP

1 L701
2
0R0805-PAD-2-GP

+1.05V_RUN_CLKGEN_IO

+1.05V_VTT

DY

CLK_SCLK

+3.3V_RUN_CLKGEN

Main Source: 71.08585.003 (SLG8SP585VTR)


2nd Source: 71.93197.003 (ICS9LRS3197AKLFT)
3rd Source: 71.00875.D03 (RTM875N-632-VB-GRT)

R706
10KR2J-3-GP

CK_PW RGD

Q702
2N7002A-7-GP

+1.05V_VTT

VR_CLKEN# 47

R701

DY 4K7R2J-2-GP

FSC

X701
CLK_XTAL_IN

R707
10KR2J-3-GP

FSC
SPEED

133MHz
(Default)

<Core Design>

CLK_XTAL_OUT

X-14D31818M-37GP
C715
SC15P50V2JN-2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

C701
SC15P50V2JN-2-GP
Title

100MHz
Size
A3
Date:

Clock Generator - SLG8SP585


Document Number

Sheet
1

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

of

89

SSID = CPU

22
22
22
22

DMI_PTX_CRXP0
DMI_PTX_CRXP1
DMI_PTX_CRXP2
DMI_PTX_CRXP3

B24
D23
B23
A22

DMI_RX0
DMI_RX1
DMI_RX2
DMI_RX3

22
22
22
22

DMI_CTX_PRXN0
DMI_CTX_PRXN1
DMI_CTX_PRXN2
DMI_CTX_PRXN3

D24
G24
F23
H23

DMI_TX0#
DMI_TX1#
DMI_TX2#
DMI_TX3#

22
22
22
22

DMI_CTX_PRXP0
DMI_CTX_PRXP1
DMI_CTX_PRXP2
DMI_CTX_PRXP3

D25
F24
E23
G23

DMI_TX0
DMI_TX1
DMI_TX2
DMI_TX3

4
3
RN801
SRN1KJ-7-GP

1
2

FDI_TX0#
FDI_TX1#
FDI_TX2#
FDI_TX3#
FDI_TX4#
FDI_TX5#
FDI_TX6#
FDI_TX7#

D22
C21
D20
C18
G22
E20
F20
G19

FDI_TX0
FDI_TX1
FDI_TX2
FDI_TX3
FDI_TX4
FDI_TX5
FDI_TX6
FDI_TX7

F17
E17

FDI_FSYNC0
FDI_FSYNC1

C17

FDI_INT

F18
D17

FDI_LSYNC0
FDI_LSYNC1

R801
PEG_IRCOMP_R

EXP_RBIAS

2 49D9R2F-GP

B26
A26
B27
A25

PEG_RX0#
PEG_RX1#
PEG_RX2#
PEG_RX3#
PEG_RX4#
PEG_RX5#
PEG_RX6#
PEG_RX7#
PEG_RX8#
PEG_RX9#
PEG_RX10#
PEG_RX11#
PEG_RX12#
PEG_RX13#
PEG_RX14#
PEG_RX15#

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PEG_CRX_GTX_N15
PEG_CRX_GTX_N14
PEG_CRX_GTX_N13
PEG_CRX_GTX_N12
PEG_CRX_GTX_N11
PEG_CRX_GTX_N10
PEG_CRX_GTX_N9
PEG_CRX_GTX_N8
PEG_CRX_GTX_N7
PEG_CRX_GTX_N6
PEG_CRX_GTX_N5
PEG_CRX_GTX_N4
PEG_CRX_GTX_N3
PEG_CRX_GTX_N2
PEG_CRX_GTX_N1
PEG_CRX_GTX_N0

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8
PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PEG_CRX_GTX_P15
PEG_CRX_GTX_P14
PEG_CRX_GTX_P13
PEG_CRX_GTX_P12
PEG_CRX_GTX_P11
PEG_CRX_GTX_P10
PEG_CRX_GTX_P9
PEG_CRX_GTX_P8
PEG_CRX_GTX_P7
PEG_CRX_GTX_P6
PEG_CRX_GTX_P5
PEG_CRX_GTX_P4
PEG_CRX_GTX_P3
PEG_CRX_GTX_P2
PEG_CRX_GTX_P1
PEG_CRX_GTX_P0

PEG_TX0#
PEG_TX1#
PEG_TX2#
PEG_TX3#
PEG_TX4#
PEG_TX5#
PEG_TX6#
PEG_TX7#
PEG_TX8#
PEG_TX9#
PEG_TX10#
PEG_TX11#
PEG_TX12#
PEG_TX13#
PEG_TX14#
PEG_TX15#

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PEG_CTX_GRX_C_N15
PEG_CTX_GRX_C_N14
PEG_CTX_GRX_C_N13
PEG_CTX_GRX_C_N12
PEG_CTX_GRX_C_N11
PEG_CTX_GRX_C_N10
PEG_CTX_GRX_C_N9
PEG_CTX_GRX_C_N8
PEG_CTX_GRX_C_N7
PEG_CTX_GRX_C_N6
PEG_CTX_GRX_C_N5
PEG_CTX_GRX_C_N4
PEG_CTX_GRX_C_N3
PEG_CTX_GRX_C_N2
PEG_CTX_GRX_C_N1
PEG_CTX_GRX_C_N0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

C817
C816
C815
C814
C813
C812
C811
C810
C809
C808
C807
C806
C805
C804
C803
C802

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

PEG_CTX_GRX_N15
PEG_CTX_GRX_N14
PEG_CTX_GRX_N13
PEG_CTX_GRX_N12
PEG_CTX_GRX_N11
PEG_CTX_GRX_N10
PEG_CTX_GRX_N9
PEG_CTX_GRX_N8
PEG_CTX_GRX_N7
PEG_CTX_GRX_N6
PEG_CTX_GRX_N5
PEG_CTX_GRX_N4
PEG_CTX_GRX_N3
PEG_CTX_GRX_N2
PEG_CTX_GRX_N1
PEG_CTX_GRX_N0

PEG_TX0
PEG_TX1
PEG_TX2
PEG_TX3
PEG_TX4
PEG_TX5
PEG_TX6
PEG_TX7
PEG_TX8
PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_CTX_GRX_C_P15
PEG_CTX_GRX_C_P14
PEG_CTX_GRX_C_P13
PEG_CTX_GRX_C_P12
PEG_CTX_GRX_C_P11
PEG_CTX_GRX_C_P10
PEG_CTX_GRX_C_P9
PEG_CTX_GRX_C_P8
PEG_CTX_GRX_C_P7
PEG_CTX_GRX_C_P6
PEG_CTX_GRX_C_P5
PEG_CTX_GRX_C_P4
PEG_CTX_GRX_C_P3
PEG_CTX_GRX_C_P2
PEG_CTX_GRX_C_P1
PEG_CTX_GRX_C_P0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

C828
C823
C871
C832
C827
C822
C831
C826
C821
C830
C825
C820
C829
C824
C819
C818

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

PEG_CTX_GRX_P15
PEG_CTX_GRX_P14
PEG_CTX_GRX_P13
PEG_CTX_GRX_P12
PEG_CTX_GRX_P11
PEG_CTX_GRX_P10
PEG_CTX_GRX_P9
PEG_CTX_GRX_P8
PEG_CTX_GRX_P7
PEG_CTX_GRX_P6
PEG_CTX_GRX_P5
PEG_CTX_GRX_P4
PEG_CTX_GRX_P3
PEG_CTX_GRX_P2
PEG_CTX_GRX_P1
PEG_CTX_GRX_P0

<Core Design>

Intel(R) FDI

FDI_INT

E22
D21
D19
D18
G21
E19
F21
G18

PCI EXPRESS -- GRAPHICS

DMI_RX0#
DMI_RX1#
DMI_RX2#
DMI_RX3#

AUBURNDALE

A24
C23
B22
A21

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

DMI

DMI_PTX_CRXN0
DMI_PTX_CRXN1
DMI_PTX_CRXN2
DMI_PTX_CRXN3

1 OF 9

CPU1A

22
22
22
22

R802

2 750R2F-GP

PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]

PEG_CTX_GRX_P[0..15] 80
PEG_CTX_GRX_N[0..15] 80

PEG_CRX_GTX_N[0..15]

PEG_CRX_GTX_N[0..15] 80

PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_P[0..15] 80

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU - PCIE/DMI/FDI (1/7)

Size
A3

Document Number

Date:

Friday, March 19, 2010

Sheet

Rev

-1

Fonseca 14.1" DIS


of

89

SSID = CPU

Processor Compensation Signals

COMP1

H_COMP0

AT26

COMP0

49D9R2F-GP
49D9R2F-GP

H_CPURST#
68R2-GP

H_SKTOCC#

37 H_SKTOCC#

AH24

H_CATERR#

PECI

25 H_PECI
R912
8K2R2J-3-GP

1 2

DY

R913
2K2R2J-2-GP

H_PROCHOT#

47 H_PROCHOT#

Q901

AN26

H_THERMTRIP#

25,39 H_THERMTRIP#

AK15

PROCHOT#

THERMTRIP#

3 DY 2 H_CATERR#
MMBT3904-7-F-GP

PEG_CLK
PEG_CLK#

E16
D16

PEG_CLK_R
PEG_CLK#_R

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A18
A17

38 CPU_CATERR#

BCLK_ITP_P_R
BCLK_ITP_N_R

H_CPURST#

58 H_CPURST#

AP26
AL15

22 H_PM_SYNC

-1.10/0318

PM_SYNC

VCCPW RGOOD

AN14

VCCPWRGOOD_1

VCCPW RGOOD_0

AN27

VCCPWRGOOD_0

22 DRAM_PW ROK

DRAM_PW ROK

AK13

SM_DRAMPWROK

52 H_VTTPW RGD

H_VTTPW RGD

AM15

VTTPWRGOOD

H_PW RGD_XDP

AM26

TAPPWRGOOD

PLT_RST#_R

AL14

RSTIN#

25,58 H_PW RGD

1 R917
2
0R0402-PAD-2-GP

RESET_OBS#

1 R919
2
0R0402-PAD-2-GP

58 H_PW RGD_XDP

RN903

4
3

DY

BCLK_ITP_P 58
BCLK_ITP_N 58

SRN0J-6-GP

PEG_CLK_R 23
PEG_CLK#_R 23

DDR_HVREF_RST_GATE

Q902

F6

SM_DRAMRST#

AL1
AM1
AN1

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

PM_EXT_TS0#
PM_EXT_TS1#

AN15
AP15

PM_EXTTS#_R

PRDY#
PREQ#

AT28
AP27

XDP_PRDY#
XDP_PREQ#

TCK
TMS
TRST#

AN28
AP28
AT27

XDP_TCLK
XDP_TMS
XDP_TRST#

TDI
TDO
TDI_M
TDO_M

AT29
AR27
AR29
AP29

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

DBR#

AN25

H_DBR#_R

BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPM6#
BPM7#

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

SM_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2

+1.05V_VTT

R914

R918

1
R934
D
2N7002A-7-GP

+1.5V_SUS

2
1KR2J-1-GP
DDR3_DRAMRST#

18,19

R915

DY

1
10KR2J-3-GP

37

C903
SCD047U10V2KX-2GP

1 DY
R936
0R2J-2-GP

C902
SC470P50V2JN-GP

XDP_PRDY# 58
XDP_PREQ# 58
XDP_TCLK 58
XDP_TMS 58
XDP_TRST# 58

DDR3 Compensation Signals


SM_RCOMP_0
1
R909
SM_RCOMP_1
1
R910
SM_RCOMP_2
1
R911

XDP_DBRESET#
0R0402-PAD-2-GP

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

2
2
2

100R2F-L1-GP-U
24D9R2F-L-GP

130R2F-1-GP

XDP_DBRESET# 22,38,58

58
58
58
58
58
58
58
58

+1.05V_VTT
XDP_TMS
R922

1
R921
1K5R2F-2-GP

21,58,80 PLTRST1#

JTAG & BPM

C901
SCD1U10V2KX-4GP

PWR MANAGEMENT

Place near U3801

DY

BCLK_CPU_P_R 25
BCLK_CPU_N_R 25

1
2

CATERR#

+1.05V_VTT

AT15

BCLK_ITP
BCLK_ITP#

AR30
AT30

THERMAL

+3.3V_RUN

AK14

SKTOCC#

BCLK_CPU_P_R
BCLK_CPU_N_R

R907

G16

A16
B16

DY

R905
H_PROCHOT#

49D9R2F-GP

H_COMP1

COMP2

49D9R2F-GP

AT24

BCLK
BCLK#

R908

H_COMP2
20R2F-GP

OF 9

COMP3

100KR2J-1-GP
2
1

DY

H_CATERR#

AT23

CLOCKS

R906

H_COMP3
20R2F-GP

DDR3
MISC

R903

MISC

R904

AUBURNDALE

R902

Processor Pullups

CPU1B
+1.05V_VTT

XDP_TDI_R
R924
750R2F-GP

R923
XDP_PREQ#

R925
XDP_TCLK
R926

DY

DY

DY

DY

51R2J-2-GP
51R2J-2-GP
51R2J-2-GP
51R2J-2-GP

JTAG MAPPING

XDP_TDI_R
R929

XDP_TDO_M

1
R930

DY

XDP_TDI

XDP_TDI

0R0402-PAD-2-GP
XDP_TDO
0R2J-2-GP

58

XDP_TDO 58

+3.3V_ALW _PCH

R941
DY 0R2J-2-GP

U901

SIO_SLP_S3#_C
0R0402-PAD-2-GP
RUNPW ROK_C
0R0402-PAD-2-GP

GND

VCC
Y

R932

0R2J-2-GP
0R0402-PAD-2-GP

XDP_TRST#

5
4

DRAM_PW ROK_R

74LVC1G08GW -1-GP

1
2
R937
1K5R2F-2-GP

DRAM_PW ROK

R939
750R2F-GP

Scan Chain
(Default)
CPU Only
GMCH Only

DY

Stuff --> R901, R929, R932


No Stuff --> R930, R931

R933
51R2J-2-GP

Stuff --> R929, R930


No Stuff --> R901, R931, R932
Stuff --> R931, R932
No Stuff --> R929, R930, R901

1
R927
1
R920

37,38,58 RUNPW ROK

1
R931

XDP_TDO_R

22,35,38,50 SIO_SLP_S3#

XDP_TDI_M

+3.3V_ALW _PCH

R901
0R0402-PAD-2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU Thermal/Clock/PM (2/7)

Size
A3

Document Number

Date:

Friday, March 19, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet

of

89

SSID = CPU

18 M_A_BS0
18 M_A_BS1
18 M_A_BS2

AC3
AB2
U7

18 M_A_CAS#
18 M_A_RAS#
18 M_A_W E#

AE1
AB3
AE9

SA_BS0
SA_BS1
SA_BS2

SA_CAS#
SA_RAS#
SA_WE#

SA_CK0
SA_CK0#
SA_CKE0

19 M_B_DQ[63..0]

AA6
AA7
P7

M_CLK_DDR0 18
M_CLK_DDR#0 18
M_CKE0 18

SA_CK1
SA_CK1#
SA_CKE1

Y6
Y5
P6

M_CLK_DDR1 18
M_CLK_DDR#1 18
M_CKE1 18

SA_CS0#
SA_CS1#

AE2
AE8

M_CS#0 18
M_CS#1 18

SA_ODT0
SA_ODT1

AD8
AF9

M_ODT0 18
M_ODT1 18

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

B9
D7
H7
M7
AG6
AM7
AN10
AN13

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DM[7..0] 18
M_A_DQS#[7..0] 18
M_A_DQS[7..0] 18

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

C9
F8
J9
N9
AH7
AK9
AP11
AT13

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

C8
F9
H9
M9
AH8
AK10
AN11
AR13

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A[15..0] 18

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

AUBURNDALE

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

OF 9

OF 9

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

19 M_B_BS0
19 M_B_BS1
19 M_B_BS2

AB1
W5
R7

SB_BS0
SB_BS1
SB_BS2

19 M_B_CAS#
19 M_B_RAS#
19 M_B_W E#

AC5
Y7
AC6

SB_CAS#
SB_RAS#
SB_WE#

SB_CK0
SB_CK0#
SB_CKE0

W8
W9
M3

M_CLK_DDR2 19
M_CLK_DDR#2 19
M_CKE2 19

SB_CK1
SB_CK1#
SB_CKE1

V7
V6
M2

M_CLK_DDR3 19
M_CLK_DDR#3 19
M_CKE3 19

SB_CS0#
SB_CS1#

AB8
AD6

M_CS#2 19
M_CS#3 19

SB_ODT0
SB_ODT1

AC7
AD1

M_ODT2 19
M_ODT3 19

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

D4
E1
H3
K1
AH1
AL2
AR4
AT8

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

D5
F4
J4
L4
AH2
AL4
AR5
AR8

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

C5
E3
H4
M5
AG2
AL5
AP5
AR7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DM[7..0] 19
M_B_DQS#[7..0] 19
M_B_DQS[7..0] 19

DDR SYSTEM MEMORY - B

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

AUBURNDALE

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

DDR SYSTEM MEMORY A

18 M_A_DQ[63..0]

CPU1D
3

CPU1C

M_B_A[15..0] 19

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU - DDR (3/7)

Size
A3

Document Number

Date:

Friday, March 19, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet
1

10

of

89

SSID = CPU

CPU1E

TP1116
TP1117

1
1

SA_DIMM_VREF#
SB_DIMM_VREF#

CFG0

PCI-Express Configuration Select

TP1101
TP1102

1
1

TP1103
TP1104

1
1

TP1105
TP1106
TP1107
TP1108
TP1109
TP1110
TP1111
TP1112
TP1113
TP1114

1
1
1
1
1
1
1
1
1
1

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

RSVD#AP25
RSVD#AL25
RSVD#AL24
RSVD#AL22
RSVD#AJ33
RSVD#AG9
RSVD#M27
RSVD#L28
SA_DIMM_VREF#
SB_DIMM_VREF#
RSVD#G25
RSVD#G17
RSVD#E31
RSVD#E30

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
RSVD_TP#H16

AUBURNDALE

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

RSVD#AL26
RSVD_NCTF#AR2
RSVD#AJ26
RSVD#AJ27

RSVD#AL28
RSVD#AL29
RSVD#AP30
RSVD#AP32
RSVD#AL27
RSVD#AT31
RSVD#AT32
RSVD#AP33
RSVD#AR33

RSVD#AR32
RSVD_TP#E15
RSVD_TP#F15
KEY
RSVD#D15
RSVD#C15
RSVD#AJ15
RSVD#AH15

R1102

CFG0

DY 3K01R2F-3-GP

1:Single PEG
0:Bifurcation enabled

B19
A19

For Clarksfield

A20
B20
CFG3

CFG3 - PCI-Express Static Lane Reversal


R1105
3K3R2J-3-GP

U9
T9

CFG3

AC9
AB9

1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

J29
J28

R1109

CFG4

DY 3K01R2F-3-GP

AJ13
AJ12

H_RSVD32
H_RSVD33

1
1

TP1118
TP1119

AH25
AK26

H_RSVD35

TP1120

H_RSVD36

TP1121

AL26
AR2
AJ26
AJ27

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33

AR32
E15
F15
A2
D15
C15
AJ15
AH15

RSVD#B19
RSVD#A19
RSVD#A20
RSVD#B20
RSVD_TP#AA5
RSVD_TP#AA4
RSVD_TP#R8
RSVD_TP#AD3
RSVD_TP#AD2
RSVD_TP#AA2
RSVD_TP#AA1
RSVD_TP#R9
RSVD_TP#AG7
RSVD_TP#AE3

RSVD#U9
RSVD#T9
RSVD#AC9
RSVD#AB9

RSVD_TP#V4
RSVD_TP#V5
RSVD_TP#N2
RSVD_TP#AD5
RSVD_TP#AD7
RSVD_TP#W3
RSVD_TP#W2
RSVD_TP#N3
RSVD_TP#AE5
RSVD_TP#AD9

CFG4

CFG4 - Display Port Presence

OF 9

RSVD#AH25
RSVD#AK26

RESERVED

SO-DIMM VREFDQ (M3) Circuit


for Clarksfield Processor

RSVD#AJ13
RSVD#AJ12

CPU Piin AJ13 and AJ12:


Core voltage sense line.
Via from PGA pad to the back of the MB
and provide test point.
Do not route any additional trace.

RSVD#J29
RSVD#J28

1:Disabled; No Physical Display Port


attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port

VSS

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34

VSS (AP34) can be left NC is


CRB implementation; EDS/DG
recommendation to GND.

RSVD_VSS

R1117
0R0402-PAD-2-GP

CFG7

R1103
DY 3K01R2F-3-GP
A

CFG7(Reserved) - Temporarily used for early


Clarksfield samples.
CFG7

Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor.

Note: Only temporary for early CFD sample


(rPGA/BGA) [For details please refer to the
WW33 MoW and sighting report].
For a common M/B design (for AUB and CFD),
the pull-down resistor shouble be used. Does
not impact AUB functionality.

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU - Reserve (4/7)

Size
Document Number
Custom
Date:
5

Rev

-1

Fonseca 14.1" DIS

Friday, March 19, 2010

Sheet
1

11

of

89

CPU1F

AUBURNDALE

1
2

1
2

1
2

1
2

The decoupling capacitors, filter


recommendations and sense resistors on the
CPU/PCH Rails are specific to the CRB
Implementation. Customers need to follow the
recommendations in the Calpella Platform
Design Guide.

C1218

C1219

C1217

1.1V RAIL POWER

DY

C1235
SC22U6D3V5MX-2GP

C1234
SC10U10V5KX-2GP

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

Please note that


The VTT Rail values are
Arrandale for VTT=1.05V
Clarksfield for VTT=1.1V

CPU VIDS

PSI#

POWER

VID0
VID1
VID2
VID3
VID4
VID5
VID6
PROC_DPRSLPVR

VTT_SELECT

AN33
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

PSI# 47
H_VID[6..0]

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

47

PM_DPRSLPVR

47
B

G15

H_VTTVID1

TP1201

Arrandale drives this pin High for 1.05V


Clarksfield drives this pin Low for 1.1V
+VCC_CORE

R1203
0R0402-PAD-2-GP
1
2
1
2
R1201
0R0402-PAD-2-GP

1
2

B15
A15

VTT_SENSE_R
TP_VSS_SENSE_VTT 1

R1202
100R2F-L1-GP-U

R1206
0R2J-2-GP
1
DY
TP1202

VCC_SENSE_R
VSS_SENSE_R

39,47

VTT_SENSE 52

DY

DY

VCC_SENSE 47
VSS_SENSE 47

R1204
100R2F-L1-GP-U

AJ34
AJ35

CPU_IMON

VTT_SENSE
VSS_SENSE_VTT

CPU_IMON_R

R1208
27D4R2F-L1-GP
2

VCC_SENSE
VSS_SENSE

AN35

ISENSE

R1205
0R0402-PAD-2-GP
1
2

R1207
27D4R2F-L1-GP
2

1
2
1
2

1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2
1
2
1
2
1
2

1
2

C1209
SC10U10V5KX-2GP

C1208
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C1207

+1.05V_VTT

SC10U10V5KX-2GP

C1216
SC10U10V5KX-2GP

C1206

SC10U10V5KX-2GP

C1205

SC10U10V5KX-2GP

C1204

SC22U6D3V5MX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC22U6D3V5MX-2GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5MX-3GP

C1203

SC10U10V5KX-2GP

C1242

C1202

+1.05V_VTT

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

CPU CORE SUPPLY

C1241

C1233
SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP
C1240

C1232

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

SC10U10V5KX-2GP

C1231

+1.05V_VTT

VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0
VTT0

SC10U10V5KX-2GP

C1225
SC10U10V5KX-2GP

C1239

C1215
SC22U6D3V5MX-2GP

C1230
SC10U10V5KX-2GP

SC10U10V5KX-2GP
C1238

C1224
SC10U6D3V5KX-1GP

C1229

C1214
SC22U6D3V5MX-2GP

C1223
SC10U6D3V5KX-1GP

C1237

C1213
SC22U6D3V5MX-2GP

C1228
SC10U10V5KX-2GP

DY

C1222
SC22U6D3V5MX-2GP

C1236
SC10U6D3V5MX-3GP

SC22U6D3V5MX-2GP

DY

C1227
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP
C1201

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP
C1226

C1221

C1212
SC22U6D3V5MX-2GP

C1220

C1211
SC10U10V5KX-2GP

SC10U10V5KX-2GP

C1210

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

OF 9

SC10U10V5KX-2GP

48A

+VCC_CORE
D

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

SENSE LINES

+VCC_CORE

PROCESSOR CORE POWER

SSID = CPU

VSS_SENSE_R

47

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU - VCC_CORE (5/7)

Size
Document Number
Custom
Date:
5

Friday, March 19, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet
1

12

of

89

SSID = CPU

C1315

DY

TC1304
SE330U2VDM-L-GP

C1314

C1313

C1312

C1311

C1310

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

J22
J20
J18
H21
H20
H19

VTT1
VTT1
VTT1
VTT1

P10
N10
L10
K10

C1309

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

+1.5V_RUN_CPU

3A
2

1
2

+1.05V_VTT

- 1.5V RAILS

SENSE
LINES

GRAPHICS VIDs

R1301
GFX_IMON_R

1KR2J-1-GP

DDR3

AR25
AT25
AM24

SC22U6D3V5MX-2GP

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

SC10U6D3V5KX-1GP

AM22
AP22
AN22
AP23
AM23
AP24
AN24

SC1U10V2KX-1GP

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6

SC1U10V2KX-1GP

VTT1
VTT1
VTT1

AR22
AT22

SC1U6D3V2KX-GP

J24
J23
H25

VAXG_SENSE
VSSAXG_SENSE

SC1U6D3V2KX-GP

C1317
SC10U10V5KX-2GP

FDI

C1316
SC10U10V5KX-2GP

OF 9

SC1U10V2KX-1GP

+1.05V_VTT

GRAPHICS

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

POWER

AUBURNDALE

CPU1G

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

C1318
SC22U6D3V5MX-2GP

C1319
SC10U10V5KX-2GP

1
2

C1325
SC10U10V5KX-2GP
B

C1329

C1328

C1327

C1326

C1330
SC22U6D3V5MX-2GP

DY

SC2D2U10V5KX-2GP

1.35A

SC4D7U6D3V3KX-GP

L26
L27
M26

SC1U25V5KX-1GP

VCCPLL VTT1
VCCPLL VTT1
VCCPLL VTT1

+1.8V_RUN

SC1U25V5KX-1GP

Please note that the VTT Rail Values


Arrandale for VTT=1.05V
Clarksfield for VTT=1.1V

C1324
SC10U10V5KX-2GP

VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1
VTT1

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

1
2

1
2

1
2

C1323
SC22U6D3V5MX-2GP

C1322
SC10U10V5KX-2GP

SC10U10V5KX-2GP

SC10U10V5KX-2GP

C1321

PEG & DMI

C1320

1.8V

18A

1.1V

+1.05V_VTT
+1.05V_VTT

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU - GFXCORE (6/7)

Size
A3

Document Number

Date:

Friday, March 19, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet
1

13

of

89

SSID = CPU
8

CPU1H

OF 9
9

VSS

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

OF 9

AUBURNDALE

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AT35 AR35
AT34

B35 A35
A34

3X

2X

NCTF
CPU1, Board Top View
4X

VSS

NCTF TEST PIN:


A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35,
AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AUBURNDALE

CPU1I

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

VSS_NCTF#AR34
VSS_NCTF#B34
VSS_NCTF#B2

AR34
B34
B2

VSS_NCTF#B1
VSS_NCTF#A35
VSS_NCTF#AT1
VSS_NCTF#AT35
RSVD_NCTF#AT33
RSVD_NCTF#AT34
RSVD_NCTF#AP35
RSVD_NCTF#AR35
RSVD_NCTF#AT3
RSVD_NCTF#AR1
RSVD_NCTF#AP1
RSVD_NCTF#AT2
RSVD_NCTF#C1
RSVD_NCTF#A3
RSVD_NCTF#C35
RSVD_NCTF#B35
RSVD_NCTF#A34
RSVD_NCTF#A33

B1
A35
AT1
AT35
AT33
AT34
AP35
AR35
AT3
AR1
AP1
AT2
C1
A3
C35
B35
A34
A33

1X

AT2
AT1 AR1

A3

C1 B1

TP_MCP_VSS_NCTFB1
TP_MCP_VSS_NCTFA35
TP_MCP_VSS_NCTFAT1
TP_MCP_VSS_NCTFAT35

1
1
1
1

TP1401
TP1404
TP1410
TP1407

TP_MCP_VSS_NCTFAT34 1

TP1409

TP_MCP_VSS_NCTFAR35 1

TP1408

TP_MCP_VSS_NCTFAR1

TP1412

TP_MCP_VSS_NCTFAT2
TP_MCP_VSS_NCTFC1
TP_MCP_VSS_NCTFA3

1
1
1

TP1411
TP1402
TP1403

TP_MCP_VSS_NCTFA34

TP1405

All NCTF pins should be Test


Points and should be routed as
trace.

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU - VSS (7/7)

Size
A3

Document Number

Date:

Friday, March 19, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet
1

14

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Reserve

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

15

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Reserve

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

16

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Reserve

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

17

of

89

1
2

1
2
1

M_VREF_CA_DIMM1
M_VREF_DQ_DIMM1

126
1
30

9,19 DDR3_DRAMRST#
MA_VTT

203
204

1
2
2

ODT0
ODT1
VREF_CA
VREF_DQ

1
2

C1826
SC1U10V2KX-1GP

SC1U10V2KX-1GP

C1825

RESET#
VTT1
VTT2

SA0_DIMM1
SA1_DIMM1

77
122
125

DY
+1.5V_SUS

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

C1802

DY

C1803

If SA0 DIM0 = 1, SA1_DIM0 = 0


SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32
C

SODIMM A DECOUPLING
+1.5V_SUS

C1810

DY

DY
2

C1809

C1819

1
2

C1818

C1817

C1801

C1808

C1807

+1.5V_SUS

Near Memory
+1.5V_SUS
Plane

C1827
C1828
C1829
C1830

+1.5V_RUN_CPU

DY2

SCD1U16V2ZY-2GP

DY2

SCD1U16V2ZY-2GP

DY2

SCD1U16V2ZY-2GP

DY2

SCD1U16V2ZY-2GP

Near CPU
+1.5V_RUN
Plane

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

62.10017.N61

DDR3-204P-42-GP

Title

Main:62.10017.N61

DDR III Socket - DM1

Size
Document Number
Custom

2nd:62.10017.F91

Date:
5

C1816

C1815

1
2

C1814

C1806

C1813

C1805

Layout Note:
Place these Caps near
SO-DIMMA.

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

C1804

DY

TC1801

0904 SA

197
201

1
2

1
2
1
2

1
2
1

C1824
SC1U10V2KX-1GP

SC1U10V2KX-1GP

C1823

199

SC10U6D3V3MX-GP

116
120

10 M_ODT0
10 M_ODT1

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Note:
If SA0 DIM0 = 0, SA1_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30

SC1U10V2KX-1GP

MA_VTT

12
29
47
64
137
154
171
188

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

PCH_SMBDATA_MEM 19,23,40,58
PCH_SMBCLK_MEM 19,23,40,58

+3.3V_RUN

SC10U6D3V3MX-GP

Place these caps


close to VTT1 and
VTT2.

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

NC#1
NC#2
NC#/TEST

2 0R0402-PAD-2-GP
2 0R0402-PAD-2-GP

SC1U10V2KX-1GP

R1809
0R0603-PAD-2-GP

SA0
SA1

R1804 1
R1805 1

198

SC10U6D3V3MX-GP

C1822
SC10U10V5KX-2GP

10
27
45
62
135
152
169
186

VDDSPD

SODIMM1_1_SMB_DATA_R
SODIMM1_1_SMB_CLK_R

R1801
0R0402-PAD-2-GP

SC1U10V2KX-1GP

+0.75V_DDR_VTT

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

EVENT#

200
202

R1803
0R0402-PAD-2-GP

SC10U6D3V3MX-GP

+0.75V_DDR_VTT

SDA
SCL

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

SC10U6D3V3MX-GP

Place between DM1 and DM2.

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

M_CLK_DDR1 10
M_CLK_DDR#1 10

11
28
46
63
136
153
170
187

SCD1U16V2KX-3GP

C1821
SC2D2U16V3KX-GP

M_CLK_DDR0 10
M_CLK_DDR#0 10

102
104

SC10U6D3V3MX-GP

M_VREF_DQ_DIMM1

SA1_DIMM1

SCD1U16V2KX-3GP

1
2
R1808
0R0603-PAD-2-GP
C1820
SCD1U10V2KX-5GP

101
103

SA0_DIMM1

SCD1U10V2KX-5GP

M_CKE0 10
M_CKE1 10

SCD1U16V2KX-3GP

+V_DDR_MCH_REF

73
74

R1802

DY 10KR2J-3-GP

SC10U6D3V3MX-GP

C1812
SC2D2U16V3KX-GP

M_CS#0 10
M_CS#1 10

10

SC10U6D3V3MX-GP

M_VREF_CA_DIMM1

CK1
CK1#

BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

114
121

M_A_A[15..0]

SE330U2VDM-L-GP

1
2
R1807
0R0603-PAD-2-GP
C1811
SCD1U10V2KX-5GP

CK0
CK0#

M_A_RAS# 10
M_A_WE# 10
M_A_CAS# 10

10

SC2D2U16V3KX-GP

+V_DDR_MCH_REF

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

CKE0
CKE1

110
113
115

SCD1U10V2KX-5GP

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

CS0#
CS1#

M_A_DQS[7..0]

10 M_A_DQ[63..0]

RAS#
WE#
CAS#

10
+3.3V_RUN

NP1
NP2

109
108

NP1
NP2

10 M_A_BS0
10 M_A_BS1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

10

M_A_DQS#[7..0]

10 M_A_BS2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

M_A_DM[7..0]

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

SO-DIMMA
H = 9.2mm

DM1

SSID = Memory

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

18

of

89

1
2

ODT0
ODT1
VREF_CA
VREF_DQ
RESET#

2
1

VTT1
VTT2

SA0_DIMM2
SA1_DIMM2

77
122
125

DY
+1.5V_SUS

75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124

C1902

DY

C1903

SODIMM B DECOUPLING

2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
205
206

+1.5V_SUS

DY

C1921

C1920

DY

C1919

C1918

DY

C1917

C1916

C1915

Note:
SO-DIMMB SPD Address is 0xA4
SO-DIMMB TS Address is 0x34

Main:62.10017.P41

SO-DIMMB is placed farther from


the Processor than SO-DIMMA

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DDR III Socket - DM2

2nd:62.10017.F81

Size
Document Number
Custom
Date:

C1912

DY

C1911

C1910

C1909

C1908

C1907

C1901

C1906

Layout Note:
Place these Caps near
SO-DIMMB.

62.10017.P41

1
2

197
201

DDR3-204P-48-GP

C1925
SC1U10V2KX-1GP

C1924
SC1U10V2KX-1GP

C1923
SC1U10V2KX-1GP

C1922
SC1U10V2KX-1GP

Place these caps


close to VTT1 and
VTT2.

203
204

+3.3V_RUN

199

1
2

1
2

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R1904
0R2J-2-GP

PCH_SMBDATA_MEM 18,23,40,58
PCH_SMBCLK_MEM 18,23,40,58

SC1U10V2KX-1GP

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

2 0R0402-PAD-2-GP
2 0R0402-PAD-2-GP

SC10U6D3V3MX-GP

MB_VTT

R1905 1
R1906 1

SC1U10V2KX-1GP

30

9,18 DDR3_DRAMRST#

126
1

NC#1
NC#2
NC#/TEST

DY

SC10U6D3V3MX-GP

R1909
0R0603-PAD-2-GP

SODIMM2_1_SMB_DATA_R
SODIMM2_1_SMB_CLK_R

198

SC1U10V2KX-1GP

M_VREF_CA_DIMM2
M_VREF_DQ_DIMM2

200
202

R1903
0R0402-PAD-2-GP

SC10U6D3V3MX-GP

116
120

10 M_ODT2
10 M_ODT3

SA0
SA1

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

SCD1U16V2KX-3GP

12
29
47
64
137
154
171
188

EVENT#
VDDSPD

M_CLK_DDR3 10
M_CLK_DDR#3 10

11
28
46
63
136
153
170
187

SCD1U10V2KX-5GP

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

SDA
SCL

102
104

SCD1U10V2KX-5GP

10
27
45
62
135
152
169
186

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

SA0_DIMM2

SCD1U10V2KX-5GP

+0.75V_DDR_VTT

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

CK1
CK1#

SA1_DIMM2

SC10U6D3V3MX-GP

CK0
CK0#

SC10U6D3V3MX-GP

C1914
SC2D2U16V3KX-GP

R1902
10KR2J-3-GP

SC10U6D3V3MX-GP

C1913
SCD1U10V2KX-5GP

M_CLK_DDR2 10
M_CLK_DDR#2 10

10
10

SC10U6D3V3MX-GP

R1908
0R0603-PAD-2-GP

M_CKE2 10
M_CKE3 10

101
103

M_B_A[15..0]

M_VREF_DQ_DIMM2

73
74

M_B_DQS[7..0]

SC10U6D3V3MX-GP

M_CS#2 10
M_CS#3 10

+V_DDR_MCH_REF

114
121

+3.3V_RUN
10

C1905
SC2D2U16V3KX-GP

1
2

C1904
SCD1U10V2KX-5GP

M_VREF_CA_DIMM2

1
2
R1907
0R0603-PAD-2-GP

CKE0
CKE1

BA0
BA1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

M_B_RAS# 10
M_B_WE# 10
M_B_CAS# 10

SC2D2U16V3KX-GP

+V_DDR_MCH_REF

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

10

M_B_DQS#[7..0]

SCD1U10V2KX-5GP

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

CS0#
CS1#

M_B_DM[7..0]

110
113
115

10 M_B_DQ[63..0]

RAS#
WE#
CAS#

NP1
NP2

109
108

NP1
NP2

10 M_B_BS0
10 M_B_BS1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
A16/BA2

10 M_B_BS2

98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
79

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

SSID = Memory

DM2 SO-DIMMB
H = 5.2mm

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

19

of

89

SSID = PCH

4 OF 10

PCH1D

L_BKLTEN
L_VDD_EN

Y48

L_BKLTCTL

AB48
Y45

L_DDC_CLK
L_DDC_DATA

AB46
V48

L_CTRL_CLK
L_CTRL_DATA

AP39
AP41

LVD_IBG
LVD_VBG

AT43
AT42

LVD_VREFH
LVD_VREFL

AV53
AV51

LVDSA_CLK#
LVDSA_CLK

BB47
BA52
AY48
AV47

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

BB48
BA50
AY49
AV48

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AP48
AP47

LVDSB_CLK#
LVDSB_CLK

AY53
AT49
AU52
AT53

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AY51
AT48
AU50
AT51

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

AA52
AB53
AD53

CRT_BLUE
CRT_GREEN
CRT_RED

LVDS

V51
V53

CRT_DDC_CLK
CRT_DDC_DATA

Y53
Y51

CRT_HSYNC
CRT_VSYNC

AD48
AB51

DAC_IREF
CRT_IRTN

CRT_IREF

SDVO_STALLN
SDVO_STALLP

BJ48
BG48

SDVO_INTN
SDVO_INTP

BF45
BH45

T51
T53

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

BG44
BJ44
AU38

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

DDPC_CTRLCLK
DDPC_CTRLDATA

Y49
AB49

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

BE44
BD44
AV40

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

BC46
BD46
AT38

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

IBEXPEAK-M-GP-NF

R2019
1KR2J-1-GP

BJ46
BG46

DDPD_CTRLCLK
DDPD_CTRLDATA

CRT

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK
SDVO_CTRLDATA

Digital Display Interface

T48
T47

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

PCH - LVDS/CRT/DDI (1/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

20

of

89

+3.3V_RUN

U2101A

1
3
2
TSLVC08APW -1-GP
RN2105

SRN8K2J-2-GP-U

2
1

3
4

PLTRST1# 9,58,80
PLTRST2# 32,34,58,72

+3.3V_RUN
INT_PIRQA#
INT_PIRQC#
PCI_STOP#
PCI_IRDY#

U2101B

4
6
5
TSLVC08APW -1-GP

10
9
8
7
6

14

SRN33J-5-GP-U
RN2101
PCI_FRAME# 1
PCI_DEVSEL# 2
INT_PIRQD#
3
4
5
+3.3V_RUN

14

SRN8K2J-2-GP-U

+3.3V_RUN

U2101C

9
RN2103
FFS_PCH_INT
PCIE_MCARD2_DET#
LVDS_CBL_DET#

8
7
6
5

PCI_PLTRST#

TSLVC08APW -1-GP RN2106


2
1

SRN8K2J-4-GP
BT_DET#
2
100KR2J-1-GP

1
R2108

3
4

PLTRST3# 37,38,70
PLTRST4# 35,64,76

SRN33J-5-GP-U

14
C

U2101D

12
11
13
TSLVC08APW -1-GP

CAM_MIC_CBL_DET#
2
100KR2J-1-GP

1
R2124

For WWAN

76 PCIE_MCARD2_DET#
73

BT_DET#

TP2102

AY9
BD1
AP15
BD8

NV_DQS0
NV_DQS1

AV9
BG8

NV_DQ0/NV_IO0
NV_DQ1/NV_IO1
NV_DQ2/NV_IO2
NV_DQ3/NV_IO3
NV_DQ4/NV_IO4
NV_DQ5/NV_IO5
NV_DQ6/NV_IO6
NV_DQ7/NV_IO7
NV_DQ8/NV_IO8
NV_DQ9/NV_IO9
NV_DQ10/NV_IO10
NV_DQ11/NV_IO11
NV_DQ12/NV_IO12
NV_DQ13/NV_IO13
NV_DQ14/NV_IO14
NV_DQ15/NV_IO15

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

NV_ALE
NV_CLE

BD3
AY6

NV_RCOMP

AU2

NV_RB#

AV7

Pair

J50
G42
H47
G34

C/BE0#
C/BE1#
C/BE2#
C/BE3#

NV_WR#0_RE#
NV_WR#1_RE#

AY8
AY5

USB0 @ MB (Charger)

USB1 @ MB

USB2 @ IO Board

USB3 @ IO Board

WLAN

Bluetooth

Not available for HM55

Not available for HM55

DOCK1

DOCK2

10

73 CAM_MIC_CBL_DET#
37,40 FFS_INT1

1
2
R2110
0R0402-PAD-2-GP

Finger Printer

11

Camera

12

TP2104

PCCard/SmartCard/ExpCard

13

WWAN

TP2105
RN2107
SRN22-3-GP
2
3
1
4

G38
H51
B37
A44

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_REQ0#
PCI_REQ1#
PCIE_MCARD2_DET#
BT_DET#

F51
A46
B45
M53

REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#

F48
K45
F36
H53

PCIRST#

23 CLK_PCI_LOOPBACK

R2115

Dock

B41
K53
A36
A48
K6

PCIRST#

E44
E50

SERR#
PERR#

PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#

A42
H44
F46
C46

IRDY#
PAR
DEVSEL#
FRAME#

PCI_PLOCK#

D49

PLOCK#

PCI_STOP#
PCI_TRDY#

D41
C48

STOP#
TRDY#

PCH_PME#

M7

PME#

D5

PLTRST#

CLK_PCI_5028_R
CLK_PCI_EC_R
CLK_PCI_DOCK_R

22R2J-2-GP
CLK_PCI_LOOPBACK_R
2
22R2J-2-GP

N52
P53
P46
P51
P48

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USBRBIAS#

B25

USBRBIAS

D25

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14

N16
J16
F16
L16
E14
G16
F12
T15

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

NV_CLE

Set to Vss when low.


Set to Vcc when high.

+V_NVRAM_VCCQ

DMI termination voltage


Weak internal pull-up
Do not pull low
Check list 1.6
If not implemented, the dual channel
NAND interface signals, including
NV_RCOMP, can be left as No Connect

R2103

DY 1KR2J-1-GP
NV_CLE
D

+V_NVRAM_VCCQ

Danbury Technology:
Disabled when Low.
Enable when High.
NV_ALE
NV_CLE

R2105

DY 1KR2J-1-GP
NV_ALE

USB

AV11
BF5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

PCI_SERR#
PCI_PERR#

PCI_PLTRST#

R2117

NV_WE#_CK0
NV_WE#_CK1

INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#

LVDS_CBL_DET#
PCH_PIRQF#
CAM_MIC_CBL_DET#
FFS_PCH_INT

54 LVDS_CBL_DET#

38 CLK_PCI_5028
37 CLK_PCI_EC
74 CLK_PCI_DOCK

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

10
7

1
2
3
4

5 OF 10

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

+3.3V_RUN
PCI_REQ1#
PCI_SERR#
PCI_TRDY#
PCI_PERR#

10
9
8
7
6

PCH1E

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

1
2
3
4
5

DMI Termination Voltage

14

+3.3V_ALW _PCH

RN2102
PCI_REQ0#
PCH_PIRQF#
INT_PIRQB#
PCI_PLOCK#

NVRAM

SSID = PCH

USB

PCI

USBP6USBP6+
USBP7USBP7+

1
1
1
1

USBP0- 63
USBP0+ 63
USBP1- 63
USBP1+ 63
USBP2- 76
USBP2+ 76
USBP3- 76
USBP3+ 76
USBP4- 64
USBP4+ 64
USBP5- 73
USBP5+ 73
TP2106
TP2107
TP2101
TP2103
USBP8- 74
USBP8+ 74
USBP9- 74
USBP9+ 74
USBP10- 78
USBP10+ 78
USBP11- 73
USBP11+ 73
USBP12- 32,34,72
USBP12+ 32,34,72
USBP13- 76
USBP13+ 76

Device

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB_RBIAS_PN

1
2
R2112
22D6R2F-L1-GP

USB_OC#0_1_R
USB_OC#2_3_R
USB_OC#4_5
USB_OC#6_7
USB_OC#8_9
USB_OC#10_11
USB_OC#12_13
PCH_OC7#

R2113
R2114

2 0R0402-PAD-2-GP
2 0R0402-PAD-2-GP

1
1

USB_OC#0_1 63
USB_OC#2_3 76

USB_OC#0_1_R 58
USB_OC#2_3_R 58
USB_OC#4_5 58
USB_OC#6_7 58
USB_OC#8_9 58
USB_OC#10_11 58
USB_OC#12_13 58
PCH_OC7# 58

IBEXPEAK-M-GP-NF
RN2104
USB_OC#0_1_R
PCH_OC7#
USB_OC#6_7
USB_OC#2_3_R

1
2
3
4
5

+3.3V_ALW _PCH

10
9
8
7
6

+3.3V_ALW _PCH
USB_OC#12_13
USB_OC#8_9
USB_OC#10_11
USB_OC#4_5

SRN10KJ-L3-GP
PCI_GNT0#
A

R2121

DY

1KR2J-1-GP

DY

1KR2J-1-GP

R2120

PCI_GNT1#

BOOT BIOS Strap


PCI_GNT#0 PCI_GNT#1

A16 swap override Strap/Top-Block


Swap Override jumper

BOOT BIOS Location

LPC

Reserved (NAND)

PCI

SPI(Default)

<Core Design>

Wistron Corporation
PCI_GNT3#
1
R2122

DY

PCI_GNT#3

2
4K7R2J-2-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

Low = A16 swap


override/Top-Block
Swap Override enabled
High = Default

Title
Size
A3

PCI_GNT[3:0]#: Internal pull high during Strap

Date:
5

PCH - PCI/USB/NVRAM (2/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

21

of

89

SSID = PCH
3 OF 10

BC24
BJ22
AW20
BJ20

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

8
8
8
8

DMI_CTX_PRXP0
DMI_CTX_PRXP1
DMI_CTX_PRXP2
DMI_CTX_PRXP3

BD24
BG22
BA20
BG20

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

8
8
8
8

DMI_PTX_CRXN0
DMI_PTX_CRXN1
DMI_PTX_CRXN2
DMI_PTX_CRXN3

BE22
BF21
BD20
BE18

8
8
8
8

DMI_PTX_CRXP0
DMI_PTX_CRXP1
DMI_PTX_CRXP2
DMI_PTX_CRXP3

BD22
BH21
BC20
BD18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BH25

DMI_ZCOMP

+1.05V_VTT
DMI_IRCOMP_R
2
49D9R2F-GP

1
R2203

BF25

FDI

DMI_CTX_PRXN0
DMI_CTX_PRXN1
DMI_CTX_PRXN2
DMI_CTX_PRXN3

DMI

PCH1C
8
8
8
8

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

FDI_INT

BJ14

FDI_FSYNC0

BF13

FDI_FSYNC1

BH13

FDI_LSYNC0

BJ12

FDI_LSYNC1

BG14

DMI_IRCOMP

+3.3V_RUN

+3.3V_RUN

R2205

9,38,58 XDP_DBRESET#

1
R2201

PM_SYSRST#_R
2
0R0402-PAD-2-GP

T6

SYS_RESET#

WAKE#

1
R2207

PM_PW ROK
2
0R0402-PAD-2-GP

M6

SYS_PWROK

CLKRUN#/GPIO32

1
R2209

PW ROK
2
0R0402-PAD-2-GP

1
R2210

ME_PW ROK
2
0R0402-PAD-2-GP

K5

MEPWROK

PCH_LAN_RST#
10KR2J-3-GP

A10

LAN_RST#

J12

PCH_PCIE_W AKE#

Y1

CLKRUN#

+3.3V_ALW _PCH

R2204
1KR2J-1-GP

1
10KR2J-3-GP
PCH_PCIE_W AKE#

R2206
8K2R2J-3-GP

38

1
R2213

DRAM_PW ROK

9 DRAM_PW ROK
37 PCH_RSMRST#
37 ME_SUS_PW R_ACK
58 PM_PW RBTN#_R
37 SIO_PW RBTN#
37 AC_PRESENT

+3.3V_ALW _PCH

B17

D9

PWROK

DRAMPWROK

1
R2215

PCH_RSMRST#_R
2
0R0402-PAD-2-GP

1
R2217

ME_SUS_PW R_ACK_R
2
0R0402-PAD-2-GP

M1

SUS_PWR_DN_ACK/GPIO30

1
R2219

PM_PW RBTN#_R
2
0R0402-PAD-2-GP

P5

PWRBTN#

1
R2221

AC_PRESENT_R
2
0R0402-PAD-2-GP

P7

1
R2222

PCH_BATLOW #
2
8K2R2J-3-GP

A6

1
R2223

PCH_RI#
2
10KR2J-3-GP

C16

F14

RSMRST#

ACPRESENT/GPIO31

P8

PM_SUS_STAT# 1

SUSCLK/GPIO62

F3

PCH_SUSCLK

SLP_S5#/GPIO63

E4

PCH_SLP_S5#

1
R2214

2
0R0402-PAD-2-GP

SLP_S4#

H7

PM_SLP_S4#_R

1
R2216

2
0R0402-PAD-2-GP

SIO_SLP_S4# 38,50,72

SLP_S3#

P12

PM_SLP_S3#_R

1
R2218

2
0R0402-PAD-2-GP

SIO_SLP_S3# 9,35,38,50

SLP_M#

K8

SIO_SLP_M#_R

1
R2220

2
0R0402-PAD-2-GP

SIO_SLP_M# 38

N2

PM_SLP_DSW #

BJ10

H_PM_SYNC

F6

SIO_SLP_LAN#_R

TP23

BATLOW#/GPIO72
RI#

2
R2211
10KR2J-3-GP

SUS_STAT#/GPIO61

PMSYNCH
SLP_LAN#/GPIO29

CLKRUN# 36,37,38

R2208
8K2R2J-3-GP

CLKRUN#

DY

TP2202

RESET_OUT#_R

System Power Management

Option to " Disable "


clkrun. Pulling it
down
will keep the clks
running.

TP2201
SIO_SLP_S5# 37

TP2203
H_PM_SYNC

R2224

DY

SIO_SLP_LAN# 38

0R2J-2-GP

IBEXPEAK-M-GP-NF

+3.3V_ALW _PCH
R2225
0R0402-PAD-2-GP
1
2
+3.3V_ALW

R2226

ME_SUS_PW R_ACK_R
2
10KR2J-3-GP

U2201
37 RESET_OUT#

RESET_OUT#

SIO_SLP_S3#

SIO_SLP_S3#_R

GND

1 DY
R2227
0R2J-2-GP

VCC

DY

R2228

AC_PRESENT_R
10KR2J-3-GP

AC_PRESENT_R
10KR2J-3-GP

PCH_RSMRST#_R
10KR2J-3-GP

DY

RESET_OUT#_R
R2229

74LVC1G08GW -1-GP
A

R2231

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

PCH - DMI/FDI/PM (3/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

22

of

89

SSID = PCH
+3.3V_ALW _PCH
+3.3V_ALW _PCH
2 OF 10

PCIE_PTX_GLANRX_N6
2
PCIE_PTX_GLANRX_P6
2
SCD1U10V2KX-4GP

1
1

PCIe port 7 and 8 may not be available


for all Ibex Peak SKUs.

AU30
AT30
AU32
AV32

PERN3
PERP3
PETN3
PETP3

DY
R2307
-1.10/0310

Express
Card

BF33
BH33
BG32
BJ32

PERN5
PERP5
PETN5
PETP5

WPAN

BA34
AW34
BC34
BD34

PERN6
PERP6
PETN6
PETP6

AT34
AU34
AU36
AV36

PERN7
PERP7
PETN7
PETP7

BG34
BJ34
BG36
BJ36

PERN8
PERP8
PETN8
PETP8

PCIE_CLK_RQ0#
10KR2J-3-GP

P9

CLK_PCIE_LOM#
CLK_PCIE_LOM

AM43
AM45

35 CLK_PCIE_LOM#
35 CLK_PCIE_LOM

LOM_CLKREQ#

35 LOM_CLKREQ#

-1.10/0310

CLK_PCIE_R5U241#
CLK_PCIE_R5U241

32 CLK_PCIE_R5U241#
32 CLK_PCIE_R5U241

PCMCLK_REQ#

32,58 PCMCLK_REQ#

PCMCIA

PERN4
PERP4
PETN4
PETP4

SML0CLK

C6

PCH_SML0CLK

SML0DATA

G8

PCH_SML0DATA

SML1ALERT#/GPIO74

M14

PCH_GPIO74

SML1CLK/GPIO58

E10

KBC_SCL1

SML1DATA/GPIO75

G12

KBC_SDA1

LAN

CLKOUT_PCIE1N
CLKOUT_PCIE1P

LAN

PCIECLKRQ1#/GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P

+3.3V_ALW _PCH
KBC_SCL1 37
KBC_SDA1 37

CL_CLK1

T13

CL_CLK

TP2301

T11

CL_DATA 1

TP2302

CL_RST1#

T9

CL_RST# 1

TP2303

+3.3V_RUN

+3.3V_ALW _PCH

R2304

H1

PCH_GPIO47

AD43
AD45

CLK_PCIE_GPU#
CLK_PCIE_GPU

CLK_PCIE_GPU# 80
CLK_PCIE_GPU 80

CLKOUT_DMI_N
CLKOUT_DMI_P

AN4
AN2

PEG_CLK#_R
PEG_CLK_R

PEG_CLK#_R 9
PEG_CLK_R 9

CLKOUT_DP_N/CLKOUT_BCLK1_N
CLKOUT_DP_P/CLKOUT_BCLK1_P

AT1
AT3

+3.3V_RUN
RN2304
SRN4K7J-8-GP

18,19,40,58 PCH_SMBCLK_MEM

AW24
BA24

CLKIN_DMI#
CLKIN_DMI

CLKIN_DMI# 7
CLKIN_DMI 7

CLKIN_BCLK_N
CLKIN_BCLK_P

AP3
AP1

CLK_CPU_BCLK#
CLK_CPU_BCLK

CLK_CPU_BCLK# 7
CLK_CPU_BCLK 7

CLKIN_DOT_96N
CLKIN_DOT_96P

F18
E18

DREFCLK#
DREFCLK

DREFCLK# 7
DREFCLK 7

AH13
AH12

CLK_PCIE_SATA#
CLK_PCIE_SATA

CLK_PCIE_SATA# 7
CLK_PCIE_SATA 7

REFCLK14IN

P41

CLK_PCH_14M

CLK_PCH_14M 7

CLKIN_PCILOOPBACK

J42

CLK_PCI_LOOPBACK

CLK_PCI_LOOPBACK

XTAL25_IN
XTAL25_OUT

AH51
AH53

XTAL25_IN
XTAL25_OUT

XCLK_RCOMP

AF38

XCLK_RCOMP

CLKOUTFLEX0/GPIO64

T45

CLK_SIO_14M_R

CLKOUTFLEX1/GPIO65

P43

CLK_PCI_TPM_CHA_R

CLKOUTFLEX2/GPIO66

T42

CLK_PCI_TPM_R

CLKOUTFLEX3/GPIO67

N50

CLK48_PCH

CLKIN_DMI_N
CLKIN_DMI_P

RN2305
SRN2K2J-1-GP

U2301

-1.10/0310

PCH_SMB_CLK

DMN66D0LDW -7-GP
18,19,40,58 PCH_SMBDATA_MEM

PCMCIA

N4

R2301
1 DY
10KR2J-3-GP

CL_DATA1

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PCIECLKRQ0#/GPIO73

AM47
AM48

1 DY
R2303
10KR2J-3-GP

SRN10KJ-5-GP

10KR2J-3-GP

CLKOUT_PCIE0N
CLKOUT_PCIE0P

U4

1
2
3
4

PCH_GPIO60

PEG_A_CLKRQ#/GPIO47

AK48
AK47
1

J14

SML0ALERT#/GPIO60

BA32
BB32
BD32
BE32

+3.3V_ALW _PCH

WLAN

PCH_SMB_DATA 37
+3.3V_ALW _PCH

1
2

C2303
C2308

PERN2
PERP2
PETN2
PETP2

RN2303
SRN2K2J-2-GP

PCH_SMB_CLK 37

4
3

4
3

35 PCIE_PRX_GLANTX_N6
35 PCIE_PRX_GLANTX_P6
35 PCIE_PTX_GLANRX_N6_C
35 PCIE_PTX_GLANRX_P6_C

PCIE_PTX_EXPRX_N4
1EXP 2
PCIE_PTX_EXPRX_P4
1EXP 2
SCD1U10V2KX-4GP

PCH_SMB_DATA

1
2

1
2

C2312
C2311

PCH_SMB_CLK

C8

PCIE_CLK_RQ3#
PCH_GPIO11

4
3

72 PCIE_PRX_EXPTX_N4
72 PCIE_PRX_EXPTX_P4
72 PCIE_PTX_EXPRX_N4_C
72 PCIE_PTX_EXPRX_P4_C

PCIE_PTX_R5U241RX_N3
2
PCIE_PTX_R5U241RX_P3
2
SCD1U10V2KX-4GP

1
1

AW30
BA30
BC30
BD30

SMBus

C2307
C2304

H14

SMBCLK

Link

32 PCIE_PRX_R5U241TX_N3
32 PCIE_PRX_R5U241TX_P3
32 PCIE_PTX_R5U241RX_N3_C
32 PCIE_PTX_R5U241RX_P3_C

PCIE_PTX_W LANRX_N2
2
PCIE_PTX_W LANRX_P2
2
SCD1U10V2KX-4GP

1
1

PCH_GPIO11

SMBDATA

Controller

C2305
C2306

B9

SMBALERT#/GPIO11

WWAN

PEG

64 PCIE_PRX_W LANTX_N2
64 PCIE_PRX_W LANTX_P2
64 PCIE_PTX_W LANRX_N2_C
64 PCIE_PTX_W LANRX_P2_C

PCIE_PTX_W W ANRX_N1
2
PCIE_PTX_W W ANRX_P1
2
SCD1U10V2KX-4GP

1
1

PERN1
PERP1
PETN1
PETP1

PCI-E*

C2301
C2302

BG30
BJ30
BF29
BH29

From CLK BUFFER

76 PCIE_PRX_W W ANTX_N1
76 PCIE_PRX_W W ANTX_P1
76 PCIE_PTX_W W ANRX_N1_C
76 PCIE_PTX_W W ANRX_P1_C

RN2313

8
7
6
5

PCH1B

CLKIN_SATA_N/CKSSCD_N
CLKIN_SATA_P/CKSSCD_P

PCIECLKRQ2#/GPIO20

PCH_SMB_DATA

+3.3V_RUN
R2318

AH42
AH41

10KR2J-3-GP
PCIE_CLK_RQ3#

CLKOUT_PCIE3N
CLKOUT_PCIE3P

WPAN

A8

PCIECLKRQ3#/GPIO25

21

RN2310

Card

PCIECLKRQ4#/GPIO26

-1.10/0310
CLK_PCIE_MINI1#
CLK_PCIE_MINI1

64 CLK_PCIE_MINI1#
64 CLK_PCIE_MINI1

MINI1CLK_REQ#_PCH

AJ50
AJ52

CLKOUT_PCIE5N
CLKOUT_PCIE5P

H6

CLK_PCIE_MINI2#
CLK_PCIE_MINI2

76 CLK_PCIE_MINI2#
76 CLK_PCIE_MINI2

MINI2CLK_REQ#_PCH

WLAN

PCIECLKRQ5#/GPIO44

-1.10/0310
AK53
AK51

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

WWAN

P13

PEG_B_CLKRQ#/GPIO56

R2317

90D9R2F-1-GP

R2316

DY 1MR2J-1-GP

1
2
R2314 1
2 22R2J-2-GP
J
R2315
22R2J-2-GP
1C_TPM 2
R2309
22R2J-2-GP
R2313

1B_TPM 2

CLK_SIO_14M 38
CLK_JETW AY_14M 36

1
2

XTAL25_OUT

CLK_PCI_TPM 35,70

22R2J-2-GP

4
3

1 MINI2CLK_REQ#_PCH
2 MINI1CLK_REQ#_PCH

R2319

SRN22-3-GP

DY

PCMCLK_REQ#
10KR2J-3-GP

1 DY2
C2309
SC12P50V2JN-3GP

From Intel checklist


CLKOUTFLEX{3:0}
PCI Routing:
47- series resistor
39- series resistor
Non PCI routing:
33- series resistor
22- series resistor

CLK_SC_48M 34
CLK_FD_48M 75

RN2312

4
3

X2301
XTAL-25MHZ-96GP

DY

CLK_PCI_TPM_CHA 36

RN2314

IBEXPEAK-M-GP-NF

+3.3V_ALW _PCH

+1.05V_VTT

1
2
C2310
0R0402-PAD-2-GP

CLKOUT_PCIE4N
CLKOUT_PCIE4P Express

M9

XTAL25_IN

EXPCLK_REQ#_PCH

AM51
AM53

EXP

CLK_PCIE_EXP_N
CLK_PCIE_EXP_P

72 CLK_PCIE_EXP#
72 CLK_PCIE_EXP

3
4

Clock Flex

2
1
SRN0J-6-GP

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +V3.3A.


PCIECLKRQ{1,2} should have a 10K pull-up to +3.3S

(single load),
(for double load)
(single-load),
(for double-load)

SRN10KJ-5-GP
+3.3V_RUN

+3.3V_ALW _PCH

<Core Design>

+3.3V_RUN

Q2302
2N7002A-7-GP

76 MINI2CLK_REQ#

MINI2CLK_REQ#_PCH

58,64 MINI1CLK_REQ#

MINI1CLK_REQ#_PCH

72 EXPCLK_REQ#

EXP

Wistron Corporation

R2310
10KR2J-3-GP

Q2303
2N7002A-7-GP

Q2304
2N7002A-7-GP

+3.3V_RUN

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

EXPCLK_REQ#_PCH

PCH - PCIE/SMBUS/CLOCK/CL (4/9)

Size
A3
Date:
5

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

23

of

89

SSID = PCH

+RTC_CELL
+RTC_CELL
RN2401

1
RN2402
SRN33J-5-GP-U
2
1

C2402
SC1U10V3KX-3GP

3
4

1
2

DY

EC2401
SC33P50V2JN-3GP

PCH_RTCRST#

C14

RTCRST#

SRTCRST#

D17

SRTCRST#

SM_INTRUDER#

A16

INTRUDER#

PCH_INTVRMEN

A14

INTVRMEN

ACZ_BIT_CLK

A30

HDA_BCLK

ACZ_SYNC_R

D29

HDA_SYNC

RN2403
76
30
30,75
76

For EMI, RF Cap.

PCH_AZ_MDC_SYNC
PCH_AZ_CODEC_SYNC
PCH_AZ_CODEC_RST#
PCH_AZ_MDC_RST#

1
2
3
4

8
7
6
5

76 PCH_MDC_SDOUT
30 PCH_CODEC_SDOUT

2
1

3
4

ACZ_SPKR

30 ACZ_SPKR

ACZ_RST#_R

P1
C30

SPKR

PCH_CODEC_SDIN0 G30

76 PCH_MDC_SDIN1

PCH_MDC_SDIN1

F30

HDA_SDIN1

HDA_SDIN2

E32

HDA_SDIN2

HDA_SDIN3

F32

HDA_SDIN3

B29

HDA_SDO

ME_FW P

H32

HDA_DOCK_EN#/GPIO33

PCH_GPIO13

J30

HDA_DOCK_RST#/GPIO13

PCH_JTAG_TCK

M3

JTAG_TCK

PCH_JTAG_TMS

K3

JTAG_TMS

PCH_JTAG_TDI

K1

JTAG_TDI

PCH_JTAG_TDO

J2

JTAG_TDO

PCH_JTAG_RST#

J4

TRST#

TP2402

ACZ_SDATAOUT_R

HDA_SDIN0

38

2 ME_FW P
10KR2J-3-GP

ME_FW P

8K2R2J-3-GP

58 PCH_JTAG_TCK
58 PCH_JTAG_TMS
58 PCH_JTAG_TDI
58 PCH_JTAG_TDO

NO REBOOT STRAP

58 PCH_JTAG_RST#

1210 SB
DY

A34
F34

LPC_LDRQ0# 38
LPC_LDRQ1# 38

SERIRQ

AB9

R2407
8K2R2J-3-GP

IRQ_SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AK7
AK6
AK11
AK9

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AH6
AH5
AH9
AH8

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF11
AF9
AF7
AF6

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AH3
AH1
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AD9
AD8
AD6
AD5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AD3
AD1
AB3 SATA_PTX_DRX_N5_C
AB1 SATA_PTX_DRX_P5_C

SATA_PTX_HRX0-_C
SATA_PTX_HRX0+_C

C2406 1
C2407 1

2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP

SATA_PRX_HTX0- 59
SATA_PRX_HTX0+ 59
SATA_PTX_HRX0- 59
SATA_PTX_HRX0+ 59

2 SCD01U50V2KX-1GP
2 SCD01U50V2KX-1GP

SATA_PRX_OTX1- 59
SATA_PRX_OTX1+ 59
SATA_PTX_ORX1- 59
SATA_PTX_ORX1+ 59

ODD
SATA_PTX_ORX1-_C
SATA_PTX_ORX1+_C

C2408 1
C2409 1

SATA port 2 and 3 may not be available


for all Ibex Peak SKUs.

DOCKING eSATA
C2410
C2411

SATA_PRX_DTX_5SATA_PRX_DTX_5+
SATA_PTX_DRX_5SATA_PTX_DRX_5+

1Dock
2 SCD01U50V2KX-1GP
1Dock
2 SCD01U50V2KX-1GP

No Reboot Strap R23


HDA_SPKR

62 PCH_SPI_CS0#

Low = Default
High = No Reboot

62 PCH_SPI_CS1#
62 PCH_SPI_DO

SATAICOMPO

AF16

SATAICOMPI

AF15

SATAICOMP
1
R2409

1
R2415

62 PCH_SPI_DIN

PCH_SPI_CLK

BA2

SPI_CLK

PCH_SPI_CS0#

AV3

SPI_CS0#

PCH_SPI_CS1#

AY3

SPI_CS1#

SATALED#

T3

PCH_SPI_DO

AY1

SPI_MOSI

SATA0GP/GPIO21

Y9

HDD_DET#_R

SATA1GP/GPIO19

V1

PCH_GPIO19

PCH_SPI_DIN_R
33R2J-2-GP

Place near PCH side

2
37D4R2F-GP

2
2

1
R2414

2
0R0402-PAD-2-GP

HDD_DET#_R 58
HDD_DET# 59

Form DG1.5
TRST# on PCH does not belong to JTAG interface.
For ES1 silicon, an ext. pull up 3.3-V Sus is required
for bias internal state.
A 20-K/10-K voltage divider to this signal to 1.1 V.
However, from ES2 silicon onward,
this signal is a No Connect regardless
if JTAG interface on PCH is enabled or not.

+COIN_CELL

RTC1

2RTC_PW R_L 3
0R0402-PAD-2-GP

1
R2418

C2401
SC1U10V3KX-3GP

-1.10/0308

25 RTC_BAT_DET#

W=20mils

5
+COIN_CELLL_R 2
R2419
BAT54CW -1-GP

3
2

1
1KR2J-1-GP

1
4

Main:20.F1000.003

MLX-CON3-10-GP-U

2nd:20.D0210.103

20.F1000.003

<Core Design>

+3.3V_RUN

INTVRMEN

DY

R2431
1KR2J-1-GP

High=Enable

integrated VccLan1_05VccCL1_05

LAN100_SLP

High=Enable

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

Low=Disable
Low=Disable

Pull up +3.3V_M enable iAMT(DY disable)

Wistron Corporation

integrated VccSus1_05,VccSus1_5,VccCL1_5

ME_FW P
PCH_SPI_DO
8K2R2J-3-GP

Title

PCH - SPI/RTC/LPC/SATA/IHDA (5/9)

Size
A3
Date:

10KR2J-3-GP

PCH_GPIO19 58

D2401

W=20mils

10KR2J-3-GP

SATA_ACT#_R 66

+3.3V_RTC_LDO
+RTC_CELL

1
2
1
R2401

1
R2412
1
R2413

PCH_GPIO19

SPI_MISO

09/0416, SPI_MISO
From Intel checklist,
No series resistor required if routing length is 1.5"-6.5" if using 1 SPI device.
Use a 33- series resistors close to them PCH if using 2 SPI devices.

DY R2416
20KR2F-L-GP

DY 10KR2J-3-GP

AV1

HDD_DET#_R

IBEXPEAK-M-GP-NF

+3.3V_SUS

DY

74
74
74
74

+3.3V_RUN
62 PCH_SPI_CLK

1
R2421

35,36,37,38

ACZ_SPKR

2
1KR2J-1-GP

PCH_JTAG_RST#

LPC_LFRAME# 35,36,37,38,70

LDRQ0#
LDRQ1#/GPIO23

+1.05V_VTT

SPI

1
R2410

C34

35,36,37,38,70

+3.3V_RUN

+3.3V_RUN

JTAG

+3.3V_ALW _PCH

SATA

+3.3V_RUN

1
R2432

FWH4/LFRAME#

HDA_RST#

30 PCH_CODEC_SDIN0

TP2401

1
R2408

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

HDD

SRN33J-7-GP

RN2404
SRN33J-5-GP-U

LPC_LAD[0..3]

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

D33
B33
C32
A32

RTCX1
RTCX2

SRTCRST# new signal Pin

76 PCH_AZ_MDC_BITCLK
30 PCH_AZ_CODEC_BITCLK

ACZ_BIT_CLK

B13
D13

1
2
X-32D768KHZ-46GP

LPC_LAD[0..3]

1 OF 10

PCH1A
PCH_RTCX1
PCH_RTCX2

C2405

SC12P50V2JN-3GP

SC15P50V2JN-2-GP

C2403

INTVRMEN- Integrated SUS


1.1V VRM Enable
High - Enable internal VRs

LPC

1
2
R2405
330KR2F-L-GP

PCH_INTVRMEN

RTC

X2401

G2401
GAP-OPEN

SM_INTRUDER#

IHDA

SRN20KJ-GP-U

1
2
R2402
1MR2J-1-GP

4
3
2

PCH_RTCX2
2
10MR2J-L-GP

1
R2404

1
2

C2404
SC1U10V3KX-3GP
2
1

PCH_RTCX1

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

24

of

89

SSID = PCH

TACH1/GPIO1

D37

TACH2/GPIO6

PCH_GPIO7

J32

TACH3/GPIO7

SIO_EXT_SMI#

F10

GPIO8

PCH_GPIO6

37 SIO_EXT_SMI#

PCH_GPIO12

38 SIO_EXT_W AKE#
58 PCH_GPIO16

DY
2

C2501
SC47P50V2JN-3GP

60 SPEAKER_DET#

77 LED_BD_DET#
58 LED_BD_DET#_R

R2506
0R0402-PAD-2-GP

GPIO15

1
2
3
4

PCH_GPIO22
PCH_GPIO1
PCH_GPIO6
PCH_GPIO7

8
7
6
5

BCLK_CPU_N_R

BCLK_CPU_N_R

AM1

BCLK_CPU_P_R

BCLK_CPU_P_R 9

C2503
SC47P50V2JN-3GP
RN2503

1
2
3
4

SIO_EXT_SCI#_R
PCH_GPIO37
PCH_GPIO16

8
7
6
5

DY
2

76 USB_MCARD2_DET#

40 FFS_INT2_R
38,58 TEMP_ALERT#

AB12

GPIO27

LED_BD_DET#_R

V13

GPIO28

STP_PCI#

M11

STP_PCI#/GPIO34

PCH_GPIO37

PECI
RCIN#

TP1

BA22

SATA3GP/GPIO37

TP2

AW22

TP3

BB22

SDATAOUT0/GPIO39

TP4

AY45

USB_MCARD2_DET#

H3

PCIECLKRQ6#/GPIO45

TP5

AY46

PCH_GPIO46

F1

PCIECLKRQ7#/GPIO46

TP6

AV43

FFS_INT2_R

AB6

SDATAOUT1/GPIO48

TP7

AV45

TEMP_ALERT#

AA4

SATA5GP/GPIO49

TP8

AF13

GPIO57

TP9

M18

TP10

N18

TP11

AJ24

TP12

AK41

TP13

AK42

TP14

M32

TP15

N32

TP16

1
R2522

2 RTC_BAT_DET#_R
10KR2J-3-GP

M30

TP17

N30

TP18

H12

+3.3V_ALW _PCH

TP19

AA23

RN2504

1
2
3
4

SIO_EXT_SMI#
PCH_GPIO46
USB_MCARD2_DET#
PCH_GPIO12

8
7
6
5

NC_1

AB45

NC_2

AB38

NC_3

AB42

NC_4

AB41

NC_5

T39

TP_VSS_NCTF22
TP_VSS_NCTF21
TP_VSS_NCTF11

TP_VSS_NCTF23

TP_VSS_NCTF43

TP2515
TP2517
TP2518

1
1
1

TP_VSS_NCTF32
TP_VSS_NCTF41
TP_VSS_NCTF42

1
1
1

+3.3V_ALW _PCH

1
R2516

SIO_EXT_W AKE#
1KR2J-1-GP

4
3

PCIE_MCARD1_DET#
BIO_DET#
SRN100KJ-6-GP

LED_BD_DET#_R
100KR2J-1-GP

TP_VSS_NCTF33
TP_VSS_NCTF31
TP_VSS_NCTF12

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

NCTF

1
1
1

TP2519

TP2516
TP2514
TP2509

SRN10KJ-6-GP

TP_VSS_NCTF13

1
2

4
3

H_THERMTRIP# 9,39

Place close to PCH

SATA2GP/GPIO36

SLOAD/GPIO38

RN2508

H_PW RGD 9,58


PCH_THERMTRIP_R

AB13

F8

+1.05V_VTT
37

SATACLKREQ#/GPIO35

P3

TP2513

STP_PCI#
8K2R2J-3-GP

1
R2515

BD10

V3

TP2512
TP2511
TP2508

USB_MCARD1_DET#
2
100KR2J-1-GP

1
R2514

BE10

THRMTRIP#

SIO_RCIN#

AB7

RSVD

SPEAKER_DET#
2
100KR2J-1-GP

1
R2513

PROCPWRGD

TPM_ID1

TP2510

H_PECI 9

T1

SRN56J-4-GP

SRN10KJ-6-GP
+3.3V_RUN

BG10

TPM_ID0

BIO_DET#

78 BIO_DET#

SCLOCK/GPIO22
GPIO24

SIO_A20GATE 37

AM3

Y7

4
3

-1.10/0310

CLKOUT_BCLK0_P/CLKOUT_PCIE8P

H10

1
2

SRN10KJ-5-GP

CLKOUT_BCLK0_N/CLKOUT_PCIE8N

58 PCH_GPIO37

SRN10KJ-6-GP
+3.3V_RUN

U2

TP2501
TP2504

TACH0/GPIO17

1 R2532 2
0R0402-PAD-2-GP

58 RTC_BAT_DET#_R

1
1

SATA4GP/GPIO16

V6
24 RTC_BAT_DET#

RN2502

A20GATE

AF48
AF47

RN2507
SIO_A20GATE
SIO_RCIN#

F38

+3.3V_RUN

LAN_PHY_PWR_CTRL/GPIO12

T7

PCH_SRC7_DMI_LAI_N
PCH_SRC7_DMI_LAI_P

TP2502
TP2503

AA2

TP_ONDIE_PLL_VR

DY
2

C2502
SC47P50V2JN-3GP

K9

1
1

SPEAKER_DET#

PCIE_MCARD1_DET#

64 USB_MCARD1_DET#

CLKOUT_PCIE7N
CLKOUT_PCIE7P

PCH_SRC6_XDP_N
PCH_SRC6_XDP_P

AH45
AH46

PCH_GPIO16

PCH_GPIO22
64 PCIE_MCARD1_DET#

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CPU

BMBUSY#/GPIO0

C38

GPIO

37 SIO_EXT_SCI#

Y3

MISC

SIO_EXT_SCI#_R
2
0R0402-PAD-2-GP
PCH_GPIO1

1
R2502

+3.3V_RUN

6 OF 10

PCH1F

58 SIO_EXT_SCI#_R

INIT3_3V#
TP24

INIT3_3V#

P6

TP2506

C10

IBEXPEAK-M-GP-NF

TPM ID

PCH1, Board Top View

TPM_ID1
(0)
TPM_ID1
(1)

4X

1X

BJ2
BJ1 BH1

B2
D1

A4

TPM_ID0
(1)

R2526
100KR2J-1-GP

B_TPM

TPM_ID0

C_TPM

RSVD

NONE

B_TPM

B_TPM and DisableBTPM


R2527
100KR2J-1-GP

CTPM and Disable B_TPM

NCTF

TPM_ID0
(0)

2X

<Core Design>

Wistron Corporation

TPM_ID1

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

C_TPM

R2531
100KR2J-1-GP

R2529
100KR2J-1-GP

Title
Size
A3
Date:

3X

+3.3V_RUN

TP_ONDIE_PLL_VR
DY 2 8K2R2J-3-GP
Internal pull up GPIO27 to
enable VccVRM

1
R2528

B53 A53
A52

+3.3V_RUN

BJ53 BH53
BJ52

1
R2521

1
2
RN2506

PCH - GPIO/CPU/MISC (6/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

25

of

89

SSID = PCH

+3.3V_RUN
+VCCA_DAC_1_2

357mA
1
DY 2
L2604
IND-1UH-2-GP

BJ18

VCCFDIPLL

C2621
SC10U6D3V5MX-3GP

AM23

VCCIO

CRT

+3.3V_RUN

357mA
C2611
SCD1U10V2KX-5GP
C

AT16

VCCDMI

AU16

+1.05VS_VCC_DMI

+1.05V_VTT

2
R2607

1
0R0402-PAD-2-GP

C2617
SC1U10V3KX-3GP

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

+3.3V_RUN

DY R2608
0R2J-2-GP

+V_NVRAM_VCCQ

VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND
VCCPNAND

+1.8V_RUN

VCCDMI

35mA
61mA

156mA

R2609
0R0402-PAD-2-GP

AT24

VCCVRM

C2618
SCD1U10V2KX-5GP

+3.3V_RUN

AM8
AM9
AP11
AP9

VCCME3_3
VCCME3_3
VCCME3_3
VCCME3_3

85mA

PCH_VCCME3_3

2
R2610

1
0R0402-PAD-2-GP

C2620
SCD1U10V2KX-5GP

DY

VCCVRM[1]

AD35
1

VCC3_3

VCCAFDI_VRM AT22

AB35

VCC3_3

FDI

+1.05VS_VCCAPLL_FDI

1
2

+1.05V_VTT

AB34

VCC3_3

+1.5VS_+1.8VS

C2619
SCD1U10V2KX-4GP

VCC3_3

DY

AN35

AP43
AP45
AT46
AT45

VCCIO
VCCIO

VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS
VCCTX_LVDS

L2602
0R0603-PAD-2-GP

69mA

AN30
AN31

AH39

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

AH38

+3.3V_RUN

VCCAPLLEXP

AF51

C2602

1
2

C2616
SC4D7U6D3V3KX-GP

C2615
SC4D7U6D3V3KX-GP

C2614
SC4D7U6D3V3KX-GP

C2613
SC4D7U6D3V3KX-GP

SC22U6D3V5MX-2GP

C2612

3.208A

BJ24
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

AF53

VSSA_DAC

HVCMOS

+1.05V_VTT

VCCIO

AE52

DMI

DY

C2610
SC10U6D3V5MX-3GP

AK24

VCCADAC
VSSA_DAC

VCCALVDS

NAND / SPI

1
DY 2
L2603
IND-1UH-2-GP

42mA

+1.05VS_VCCAPLL_EXP

AE50

VSSA_LVDS

PCI E*

+1.05V_VTT

LVDS

+1.05V_VTT

DY

7 OF 10

VCCADAC

POWER

VCC CORE

1
2

SC1U10V2KX-1GP

C2603

VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE
VCCCORE

C2605

SC10U6D3V5MX-3GP

C2606
SC10U6D3V3MX-GP

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

SCD1U10V2KX-5GP

PCH1G

1.524A

SCD01U16V2KX-3GP

+1.05V_VTT

C2604

+1.05V_VTT
IBEXPEAK-M-GP-NF

+1.5VS_+1.8VS

196mA
VCCAFDI_VRM

R2611
0R0402-PAD-2-GP
+1.5VS_+1.8VS

<Core Design>

+1.8V_RUN

Wistron Corporation

1
2
R2612
0R0603-PAD-2-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

PCH (7/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

26

of

89

DY

AP53

VCCACLK

AF23

VCCLAN

AF24

VCCLAN

POWER

V24
V26
Y24
Y26

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

VCCSUS3_3

U23

VCCIO

V23

<1mA V5REF_SUS

F24

Y39

VCCME

C2712
SC1U10V2KX-1GP
C2714
SCD1U10V2KX-4GP

Y41

VCCME

Y42

VCCME

C2716
SC1U10V2KX-1GP

72mA +1.05VS_VCCA_A_DPL
73mA +1.05VS_VCCA_B_DPL

C2721
SC1U10V2KX-1GP

1
2

C2720
SC1U10V2KX-1GP

DCPRTC

AU24

VCCVRM

BB51
BB53

VCCADPLLA
VCCADPLLA

BD51
BD53

VCCADPLLB
VCCADPLLB

AH23
AJ35
AH35

VCCIO
VCCIO
VCCIO

AF34

VCCIO

+1.5VS_+1.8VS

+1.05V_VTT

C2719
SC1U10V2KX-1GP

V9

AH34

VCCIO

AF32

VCCIO

V12

V5REF

K49

VCC3_3

J38

VCC3_3

L38

VCC3_3

M36

VCC3_3

N36

VCC3_3

P36

VCC3_3

U35

VCC3_3

AD13

USB

DCPSST

Y22

DCPSUS

+5VS_PCH_VCC5REF

1
R2701
C2713
SC1U10V2KX-1GP

VCCSUS3_3

U19

VCCSUS3_3

U20

VCCSUS3_3

U22

C2727
SCD1U10V2KX-4GP

VCCSUS3_3

+3.3V_RUN

C2728
SCD1U10V2KX-4GP

V15

VCC3_3

V16

VCC3_3

Y16

VCC3_3

SATA

163mA

PCI/GPIO/LPC

+3.3V_ALW _PCH

1mA

C2718
1

2
100R2J-2-GP

AK3
AK1

VCCIO

AH22

VCCVRM

AT20

VCCIO

AH19

VCCIO

AD20

VCCIO

AF22

VCCIO
VCCIO
VCCIO
VCCIO

AD19
AF20
AF19
AH20

VCCIO
VCCIO
VCCIO
VCCIO

AB19
AB20
AB22
AD22

VCCME
VCCME
VCCME
VCCME

AA34
Y34
Y35
AA35

+3.3V_RUN

SCD1U10V2KX-4GP

C2722
SC1U10V2KX-1GP DY

+1.05V_VTT

L2704

1
C2723

DY

32mA

IND-10UH-30-GP

DY SC1U10V2KX-1GP

C2731

V_CPU_IO

AU18

+1.05V_VTT

C2725
SC1U10V2KX-1GP

+1.05V_VTT

+3.3V_ALW _PCH

IBEXPEAK-M-GP-NF

HDA

VCCRTC

RTC

+3VS_+1.5VS_HDA_IO

A12

VCCSUSHDA

C2734

L30

6mA

1
2

V_CPU_IO

R2707

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

C2732
SC1U10V2KX-1GP
Title
Size
A3
Date:

1
0R0402-PAD-2-GP

C2733

SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

C2737
SC1U10V2KX-1GP

2mA

+RTC_CELL

2
A

C2730

SC1U10V2KX-1GP

C2729
SC4D7U6D3V3KX-GP

SC1U10V2KX-1GP

AT18

CPU

+1.05V_VTT

1
R2702
C2715
SC1U10V2KX-1GP

P18

+5V_RUN

C2717
SCD1U10V2KX-4GP

+1.5VS_+1.8VS

C2726
SCD1U10V2KX-4GP

D2701
SDMK0340L-7-F-GP

2
100R2J-2-GP

+3.3V_RUN

+1.05V_PCH_DcpSUS

C2724
SCD1U10V2KX-4GP

+5V_ALW _PCH
+5VALW _PCH_VCC5REFSUS

+1.05VS_VCCAPLL

VCCSATAPLL
VCCSATAPLL

+1.5V_PCH_DcpSST

+3.3V_RUN
D2702
SDMK0340L-7-F-GP

+1.05V_VTT

1
2

COIL-10UH-9-GP
C2736
SC22U6D3V5MX-2GPDY

+1.05VS_VCCA_B_DPL

+VCCRTCEXT

L2703

COIL-10UH-9-GP
C2735
SC22U6D3V5MX-2GPDY

2
1

+1.05VS_VCCA_A_DPL

L2702

C2701
SCD1U10V2KX-4GP

VCCME

V42

SC1U10V2KX-1GP

DY

+1.05V_VTT

C2711

+3.3V_ALW _PCH

VCCME

VCCME

V41

+3.3V_ALW _PCH

VCCME

V39

VCCME

AF42

VCCME

AF41

VCCME

AF43

PCI/GPIO/LPC

1
2

C2706

SC1U10V2KX-1GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

C2710

1.998A

VCCME

AD41

VCCME

AD39

C2708
SCD1U10V2KX-4GP

AD38

+3.3V_ALW _PCH

DCPSUSBYP

Clock and Miscellaneous

+1.05V_VTT

C2705

C2707
SC1U10V2KX-1GP

Y20

C2709
SCD1U10V2KX-4GP

+1.05V_VTT

10 OF 10

VCCIO
VCCIO
VCCIO
VCCIO

DCPSUSBYP

VCCACLK

VCC_LAN_PCH
R2708
0R0402-PAD-2-GP

AP51

(344mA)
D

C2703

SC1U10V2KX-1GP

IND-10UH-30-GP

PCH1J

DY

+1.05VS_VCCA_CLK

L2701

52mA

+1.05V_VTT

SSID = PCH

PCH (8/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

27

of

89

SSID = PCH

8 OF 10

PCH1H

AB16

VSS

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

IBEXPEAK-M-GP-NF
A

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

9 OF 10

PCH1I

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

IBEXPEAK-M-GP-NF

Size
A3
Date:
5

PCH (9/9)

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

28

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Reserve

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

29

of

89

SSID = AUDIO
+VDDA

DY

2
10KR2J-3-GP

AUD_NB_MUTE

1
2

PUMP_CAPP

U3002
AUD_DMIC_CLK_Y

VCC

DMIC_CLK/GPIO1
DMIC0/GPIO2

OE#
A
GND

74LVC1G125DC-GP

SPDIF_OUT_0
EAPD

35

CAP-

36

CAP+

AVSS
AVSS
AVSS

42

PVSS

49

GND

PC_BEEP

12

MONO_OUT

25

AUD_HP_JACK_L_2
AUD_HP_JACK_R_2

60
60

AUD_SPK_R- 60
AUD_SPK_R+ 60

CAP2

22

AUD_CAP2

VREFFILT

21

AUD_VREFFLT

V-

34

AUD_V_B

VREG

37

AUD_VREG

C3021

1 ACZ_SPKR_R R3013
SCD1U10V2KX-4GP
R3016
1 EC_BEEP
SCD1U10V2KX-4GP

1
1

AUD_HP_JACK_R_2

1
1

DY

DY

1
2

2
R3024

DY
2N7002A-7-GP

Low -> Mute

1
100KR2J-1-GP

DY

AO3418-GP
Q3001

60

YD version need d-pop circuit


UA version no need d-pop circuit
Now is YD version

<Core Design>

Wistron Corporation

AO3418-GP
Q3005

+3.3V_RUN

DY

1
2

HP_NB_SENSE

Q3003
AO3418-GP

2
D

2
2

Q3002
AO3418-GP
G

AUD_HP_L_Q

1
2

From EC

AUD_HP_JACK_L_2

Q3004
AUD_NB_MUTE

R3023
39K2R2F-L-GP

Q3006
DMN66D0LDW-7-GP
C3027
SCD1U10V2KX-4GP

From PCH

BEEP 37

AUD_HP_R_Q

AUD_SENSE_A
R3001
20KR2F-L-GP

75
75

ACZ_SPKR 24

HP_CODEC_MUTE

AUD_MIC_SWITCH

DY

AUD_DOCK_MIC_IN_L_C
AUD_DOCK_MIC_IN_R_C

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

MIC_SWITCH
AUD_HP_NB_SENSE

38,60
Title
Size
Document Number
Custom
Date:

75
75

For Codec pop noise

Place this block


close to Audio Codec Pin13

C3026
SC1KP50V2KX-1GP

PCH_AZ_CODEC_SDOUT1

AUD_DOCK_HP_OUT_L_C
AUD_DOCK_HP_OUT_R_C

2
499KR2F-1-GP
2
499KR2F-1-GP

R3020
100KR2J-1-GPDY

1
R3022
47R2J-2-GP

DY

1Dock2

R3015
DUMMY-C2

+VDDA

R3021
2K49R2F-GP

1Dock2

DOCK MIC
C3020

+15V_ALW

PCH_CODEC_SDOUT

1Dock2

DOCK HP

AUD_DOCK_HP_OUT_L_C1
1
1Dock2
SC1U16V3KX-2GP
1 2KR2F-3-GP AUD_DOCK_HP_OUT_R_C1 C3042 1Dock
2
2KR2F-3-GP
C3040
SC1U16V3KX-2GP
AUD_DOCK_MIC_IN_L_C1
2
2 Dock 1
Dock
SC1U16V3KX-2GP
AUD_DOCK_MIC_IN_R_C1 R3019 2 Dock 1 2KR2F-3-GP
2
Dock
SC1U16V3KX-2GP
R3028
2KR2F-3-GP

Dock
Dock

Close to codec

Azalia I/F EMI

1Dock2

AUD_PC_BEEP

EC3001DY
SC22P50V2JN-4GP

AUD_DOCK_HP_OUT_L_C1
C3041
AUD_DOCK_HP_OUT_R_C1
C3038
AUD_DOCK_MIC_IN_L_C1
C3043
AUD_DOCK_MIC_IN_R_C1
C3037

60

Speaker

AUD_SPK_L+ 60
AUD_SPK_L- 60

AUD_PC_BEEP
Trace width>15 mils

AUD_DMIC_CLK

2
100R2J-2-GP

17
18

C3010
SC10U6D3V3MX-GP

PORT_F_L
PORT_F_R

AUD_DOCK_HP_OUT_L
2
AUD_DOCK_HP_OUT_R R3029 2
R3030
AUD_DOCK_MIC_IN_L
1
AUD_DOCK_MIC_IN_R
C3039 1
C3036

15
16

C3009
SC1U10V3KX-3GP

PORT_E_L
PORT_E_R

C3008
SCD1U10V2KX-4GP

43
44

92HD81B1A5NLGXUAX8-GP

SPKR_PORT_D_RSPKR_PORT_D_R+

AUD_SPK_RAUD_SPK_R+

2 60D4R2F-GP
2 60D4R2F-GP

Ext. MIC

Earphone

U3001 change to UA version.


R3017

C3007
SC1U10V3KX-3GP

AUD_SPK_L+
AUD_SPK_L-

R3007 1
R3008 1

MIC_IN_L_2 60
MIC_IN_R_2 60
AUD_VREFOUT_B

40
41

2 SC2D2U25V5KX-1GP
2 SC2D2U25V5KX-1GP

73 AUD_DMIC_CLK_G

SPKR_PORT_D_L+
SPKR_PORT_D_L-

DVSS

33
30
26

0R2J-2-GP
R3018

19
20
24

DMIC1/GPIO0/SPDIF_OUT_1

47

DY

DY

1
2
3

PORT_C_L
PORT_C_R
VREFOUT_C

75

C3011 1
C3012 1

SC1KP50V2KX-1GP

HDA_RST#

48

7
+3.3V_RUN

AUD_HP_OUT_L
AUD_HP_OUT_R

HDA_SYNC

PUMP_CAPN
C3017
SC2D2U25V5KX-1GP

HP1_PORT_B_L
HP1_PORT_B_R

31
32

HDA_SDO

AUD_SENSE_B

1
R3010

38 AUD_NB_MUTE

AUD_EXT_MIC_L
AUD_EXT_MIC_R
AUD_VREFOUT_B

HP0_PORT_A_L
HP0_PORT_A_R
VREFOUT_A_OR_F

28
29
23

+3.3V_RUN

AUD_SENSE_A
AUD_SENSE_B

2
4
46

13
14

2
0R0402-PAD-2-GP

SENSE_A
SENSE_B

+5V_RUN

AUD_DMIC_CLK
AUD_DMIC_IN0_R

39
45

11

PVDD
PVDD

C3025
SC1U6D3V2KX-GP

10

1.35A

27
38

HDA_SDI

1
8

AVDD
AVDD

2
0R0402-PAD-2-GP

Close to codec

C3024
SC10U6D3V5MX-3GP

1
R3009

73 AUD_DMIC_IN0

PCH_CODEC_SDIN0_R

66mA

+5V_RUN

1
R3002

Digi. MIC

120mA

HDA_BITCLK

PCH_AZ_CODEC_RST#

24,75 PCH_AZ_CODEC_RST#

120mA

DVDD_IO

PCH_AZ_CODEC_SYNC

24 PCH_AZ_CODEC_SYNC

3
PCH_AZ_CODEC_BITCLK

PCH_CODEC_SDOUT

24 PCH_CODEC_SDOUT

DVDD

2 33R2J-2-GP

DVDD_CORE

C3023
SC10U6D3V5MX-3GP

R3006 1

24 PCH_CODEC_SDIN0

C3001
SC10P50V2JN-4GP

1
2

1
2

24 PCH_AZ_CODEC_BITCLK

DY

U3001

R3005
10KR2J-3-GP

1 2

DY

C3003
SC10U6D3V5MX-3GP

C3022
SC4D7U6D3V3KX-GP

PCH_AZ_CODEC_BITCLK

DY

AUD_DVDDCORE

C3005
SCD1U10V2KX-4GP

C3004
SC1U6D3V2KX-GP

Close to codec

Close to codec
C3006
SCD1U10V2KX-4GP

Close to codec

+3.3V_RUN

C3002
SCD1U10V2KX-4GP

+3.3V_RUN

Audio Codec

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

30

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Reserve

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

31

of

89

SSID = 1394
+3.3V_RUN_CB

C3206
SCD1U10V2KX-4GP

C3205
SCD1U10V2KX-4GP
2
1

C3204
SCD1U10V2KX-4GP
2
1

C3203
SCD1U10V2KX-4GP
2
1

C3202
SC10U6D3V5MX-3GP
2
1

+3.3V_RUN

1
R3201

2
0R0805-PAD-2-GP

PCIE_VOUT/VIN

+3.3V_RUN_CB

U3201

SDMSXD_VCC trace = 40mil

D7
VCC_SD
2
SC1U10V2KX-1GP

1
C3219

M10
N10

23 PCIE_PTX_R5U241RX_N3_C
23 PCIE_PTX_R5U241RX_P3_C
RXC_R5U241

Close to AVCC_3V_R5U241

C3212
SCD1U10V2KX-4GP

C3211
SC1U6D3V2KX-GP
2
1

C3209

23 PCIE_PRX_R5U241TX_N3
23 PCIE_PRX_R5U241TX_P3

+3.3V_RUN_CB

21,34,58,72

2SCD1U10V2KX-4GP
2
SCD1U10V2KX-4GP

1
1

C3210

PLTRST2#

R3202

PCIE_PRX_R5U241TX_N3_C
PCIE_PRX_R5U241TX_P3_C

CPO_R5U241
RREF_R5U241
CB_RST#_R
2
0R0402-PAD-2-GP

B5
A5

TPB0N
TPB0P

B6
A6
C7

71 TPBIAS0
1

CPS
2
0R0402-PAD-2-GP

D4

1394_XI
1394_XO_R

1 R3222 2
0R0402-PAD-2-GP

SDBWP#

CPO_R5U241

C3201
SC1500P50V2KX-2GP

R3223
23,58 PCMCLK_REQ#

PCMCLK_REQ#_C

0R0402-PAD-2-GP

RXC_R5U241

A8
B8
A11
B11
B9
A9

C3214
SCD1U10V2KX-4GP

CBS_SPK
C3215
SCD022U16V2KX-3GP

GBRST#

71
SDWP
71 SD_MMC_DAT1
71 SD_MMC_DAT0

1
R3218 1
R3217

RREF_R5U241

R3207 close to U3201


trace need Shield GND

R3207
5K1R2F-2-GP

71 SD_MMC_CLK

2
2 33R2J-2-GP
33R2J-2-GP

R3205

71 SD_MMC_CMD

SD_MMC_DAT1_R
SD_MMC_DAT0_R
SD_MMC_CLK_R

33R2J-2-GP

R3214

-1.10/0302
SD_MMC_CMD_R

0R0402-PAD-2-GP

1
R3220 1
R3219

71 SD_MMC_DAT3
71 SD_MMC_DAT2

2
2 33R2J-2-GP
33R2J-2-GP

SD_MMC_DAT3_R
SD_MMC_DAT2_R

+3.3V_RUN_CB

3 in 1 SD,SDHC/
MMC
/
MMC+
/

R3208
2

L10
L11
M12

TPA0N
TPA0P

Close to chip

N13
N12

71
71

R3203

L9

71
71

+3.3V_RUN_CB

SDMSXD_VCC

D8
M8
N8

23 CLK_PCIE_R5U241#
23 CLK_PCIE_R5U241

D13

CBS_SPK

47KR2F-GP

Flash
use 4
use 1
use 8

Card
bit
bit
bit

71 SD_MMC_CD#

SD_MMC_CD#

C9
A10
B10
G10
H10
K13
K12
J13
J12
J11
H11
J10
L13
K9
K10
H13
H12
G13
G12
F13
F12
D12
D10
C13
C12
B13
C11
A13
B12
A12
F11
G11

PCIE_VOUT
PCIE_VOUT
MF_VOUT
AVCC_3V
SD18C
REFCLKN
REFCLKP
RXN
RXP
RXC
TXN
TXP

CDATA0
CDATA1
CDATA2
CDATA3
CDATA4
CDATA5
CDATA6
CDATA7
CDATA8
CDATA9
CDATA10
CDATA11
CDATA12
CDATA13
CDATA14
CDATA15

CPO
RREF
PERST#
TPAN0
TPAP0
TPBN0
TPBP0
TPBIAS0
CPS

IORD#
IOWR#

XI
XO

OE#
WE#
GND
GND
GND
GND

CE1#
CE2#
BVD1
BVD2

GND
GND
GND
MFCD2#
NC#H10

CD1#
CD2#
VS1#
VS2#

UDIO0
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5

REG#
RDY/IREQ
WP#/IOIS16#
RESET
WAIT#
INPACK#

SPKROUT
WAKE#
GBRST#
TEST

VPPEN0
VPPEN1
VCC5EN#
VCC3EN#

MFIO0
MFIO1
MFIO2
MFIO3
MFIO4
MFIO5
MFIO6
MFIO7
MFIO8
MFIO9
MFIO10
MFIO11
MFIO12
MFIO13
MFIO14

CBS_CAD26
CBS_CAD25
CBS_CAD24
CBS_CAD23
CBS_CAD22
CBS_CAD21
CBS_CAD20
CBS_CAD18
CBS_CC/BE1#
CBS_CAD14
CBS_CAD9
CBS_CAD12
CBS_CC/BE2#
CBS_CPAR
CBS_CPERR#
CBS_CIRDY#
CBS_CCLK_R
CBS_CAD16
CBS_DATA18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#
CBS_CTRDY#
CBS_CFRAME#
CBS_CAD17
CBS_CAD19

N5
N6
N7
C5
A4
A3
A2
A1
M5
M6
M7
B4
C4
B3
B2
B1

CBS_CAD27
CBS_CAD29
CBS_DATA2
CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CAD28
CBS_CAD30
CBS_CAD31
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_DATA14
CBS_CAD8

D1
E1

CBS_CAD13
CBS_CAD15

C1
F4

CBS_CAD11
CBS_CGNT#

D5
D3

CBS_CC/BE0#
CBS_CAD10

K7
L6

CBS_CSTSCHNG
CBS_CAUDIO

D6
K8

CBS_CCD1#
CBS_CCD2#

E4
K5

CBS_CVS1
CBS_CVS2

L4
G4
L7
N1
N2
K6

CBS_CC/BE3#
CBS_CINT#
CBS_CCLKRUN#
CBS_CRST#
CBS_CSERR#
CBS_CREQ#

E10
D9

VPPEN0
VPPEN1

E11
F10

VCC5EN#
VCC3EN#

CBS_CC/BE1#

72

CBS_CC/BE2# 72
CBS_CPAR 72
CBS_CPERR# 72
CBS_CIRDY# 72

2 R3204 1
0R0402-PAD-2-GP

CBS_DATA18 72
CBS_CBLOCK# 72
CBS_CSTOP# 72
CBS_CDEVSEL# 72
CBS_CTRDY# 72
CBS_CFRAME# 72

CBS_DATA2

CBS_CCLK

72

Shield GND

72

CBS_CAD[0..31]
CBS_DATA14

72

72

IORD#=>USBD+
IOWR#=>USBDCBS_CGNT#

72

CBS_CC/BE0#

72

CBS_CSTSCHNG 72
CBS_CAUDIO 72
CBS_CCD1#
CBS_CCD2#
CBS_CVS1
CBS_CVS2

72
72
72
72

CBS_CC/BE3# 72
CBS_CINT# 72
CBS_CCLKRUN# 72
CBS_CRST# 72
CBS_CSERR# 72
CBS_CREQ# 72
VPPEN0
VPPEN1

72
72

VCC5EN#
VCC3EN#

72
72

+3.3V_RUN_CB
AGND
AGND

K11
L12
2

J3
C8

SDMSXD_VCC
+3.3V_RUN_CB

PCIE_VIN
PCIE_VIN
PCIE_VIN

M4
N4
N3
M3
L3
M2
M1
L1
E3
D2
C3
C2
K1
F1
G1
J2
H3
E2
F2
G2
F3
G3
J1
H4
K2
L2

GND
GND
GND
GND
GND
GND
GND
USBDM
USBDP
GND
GND
GND
GND

MFCD0#
MFCD1#

M9
N9
E13
E12
L8
L5
K4
H2
H1
A7
B7
C6
D11

R3206
47KR2F-GP
1

C3207
SCD1U10V2KX-4GP

C3208
SCD1U10V2KX-4GP
2
1

N11
M11
M13

CADR0
CADR1
CADR2
CADR3
CADR4
CADR5
CADR6
CADR7
CADR8
CADR9
CADR10
CADR11
CADR12
CADR13
CADR14
CADR15
CADR16
CADR17
CADR18
CADR19
CADR20
CADR21
CADR22
CADR23
CADR24
CADR25

GBRST#
USBP12USBP12+

USBP12- 21,34,72
USBP12+ 21,34,72

PCIE_VOUT/VIN

Close to VCC_3V_R5U241

+3.3V_RUN_CB

VCC_3V
VCC_3V
VCC_3V

K3
J4
C10

C3216
SC1U10V2KX-1GP

R5U242-CSP144P-GP-U

Global Reset (GBRST#)


Note:De-asserted before PERST# de-assertion

1394_XI

X3201

1394_XO

1 R3209 2
0R0402-PAD-2-GP

1394_XO_R

X-24D576MHZ-70GP

C3218
SC15P50V2JN-2-GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

<Core Design>
C3217
SC15P50V2JN-2-GP

Title

Shield GND

Flash Reader / 1394 / PCMCIA


Xtal for XO/XI as close as possible to R5U241

Size
C
Date:

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

32

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

Reserve

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

33

of

89

SSID = SmartCard

SmartCard Chip
+3.3V_RUN

SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP

SC1C3404

SC1C3406

+5V_RUN

1
C3405
1
C3407

SC2
SC2

RN3402
SCD1U10V2KX-4GP

1
2
3
4

SC4D7U6D3V3KX-GP

SC

8
7
6
5

SC_VCC

SRN15KJ-2-GP

USBP12-_C
USBP12+_C

21,32,58,72 PLTRST2#

UP_DN
UP_DP

12

RST#

3
4

23 CLK_SC_48M

MODE0/SC_LED
MODE1
MODE2

9
11
26
33

GND
GND
GND
GND

SC

27
24
23
22
25
13

SC_VCC
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#

RFIO_1
RFIO_0

15
14

7
30
31

SC_VCC 67
SC_RST# 67
SC_CLK 67
SC_C4 67
SC_IO 67
SC_DET# 67

SC_VCC confirm FAE


20 mils is OK

C3402

SC

C3403
C

Near OZ77CR6L

SC_C4
This pin connects to the C4 pin of the Smart Card connector.
It is required to support ISO7816-10 synchronous type 2 cards.

29

6
10

NC#7
NC#30
NC#31

SC
SC_EG_D- 67
SC_EG_D+ 67

SC_VCC
SC_RST#
SC_CLK
SC_C4
SC_IO
SC_DET#

OZ77CR6LN-GP-U1

R3409
4K7R2J-2-GP

SC_EG_DSC_EG_D+

48M_IN
NC#4

32
1
2

MODE0_LED

EGATE_DN
EGATE_DP

21
20

3_3VCC

17
16

SC_DP_DSC_DP_D+

19
18

3V_CPR

2
1K5R2J-3-GP

DP_DN
DP_DP

SC

SCD1U10V2KX-4GP

1 SC
R3403

5_0VCC
5_0VCC

SC4D7U6D3V3KX-GP

21,32,72 USBP1221,32,72 USBP12+

RN3403
SRN0J-6-GP
2
3
1
SC 4

5
28

VR_CPR_0
VR_CPR_1

Full Speed Device


C

U3401

2
1

CLK_SC_48M_C

DY

SC

MODE0 / SC_LED

C3401

VR filter.
An external capacitor shall connect to this terminal.

C3409
SC10P50V2JN-4GP

This terminal is an output indicating Smart Card activity;


capable to drive an external LED device.
The SC_LED terminal drives a low logic level during Smart Card data
read/write activity, and is capable to source 12mA of IOL current to
drive an external LED circuit.

SC

SC1U10V2KX-1GP
2

C3408

SC1U10V2KX-1GP

R3411
10KR2J-3-GP

DY
B

CLK_SC_48M

RFIO_0
RFIO_1

Contactless Smart Card Interface Signal 0 and 1.


This signal provides detection and data communication
with an external RF device.
If contactless is disabled, then this terminal shall be pulled-down
to GND through a pull-down resistor, or directly connected to GND.

When RST# is asserted, this terminal is sampled to select the


downstream port configuration for DP_DP and DP_DN (Internal Port 1).
When sampled low (4.7k), the downstream port device is removable.
When sampled high, the downstream port is a non-removable device.
Includes internal input pull-up resistor.

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

MODE1

Test Pin.

This terminal shall be externally connected to GND.

MODE2

Test Pin.

This terminal shall be externally connected to GND.

Title

Smart Card (OZ77CR6LN)

Size
Document Number
Custom
Date:

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

34

of

89

SSID = LOM

+3.3V_LAN
+3.3V_LAN

SRN2K2J-1-GP
LAN_SMBCLK

37

SMBCLK
SMBDATA

2
1

+3.3V_LAN_EN1

+3.3V_LAN_EN2

SI3456DDV-T1-GE3-GP

+3.3V_LAN

R3504

37

DY 470KR2J-2-GP

J1

E10
D10
F11

N4

+1.2V_PCIE_PLLVDD

L5

+1.2V_GPHY_PLLVDD

1
1
1
1
1

TP3507
TP3508
TP3509
TP3510
TP3511

G3
F2
D5
C6
C3
F10
N13

BIASVDDH
USB_PLLVDDL
PCIE_SDSVDD
PCIE_PLLVDDL
GPHY_PLLVDDL

TDI
TMS
TDO
TCK
TRST#
NB_GPHY_TVCOI
DK_GPHY_TVCOI

4
3

1
R3537

1
B_TPM

0R2J-2-GP

36 LOM_PCIE_RST#
24,36,37,38 IRQ_SERIRQ

0R2J-2-GP

1
R3539 1
R3543

+3.3V_LAN

CLK_PCI_TPM
1

RN3505

R3501

8
7
6
5

LPC_LAD2_BTPM
LPC_LAD1_BTPM
LPC_LAD0_BTPM
CLK_PCI_TPM

RN3506
1
2
3
4

8
7
6
5

L9
J8
K10
J10

LPC_LAD3_BTPM
LPC_LFRAME#_BTPM

2
2 10KR2J-3-GP
10KR2J-3-GP

L11
L8
L10
L2

TPM_GPIO0
TPM_GPIO1
TPM_GPIO2

K9
K8
J9

TP3513
TP3514

1
1

TP3515

TP3516

CTPM and DisableBTPM


SRN10KJ-6-GP

C3542
DY SC4D7P50V2CN-1GP
2

CLK_PCIGLAN

1
2
3
4

DY 22R2J-2-GP

LPC_LAD0_BTPM
LPC_LAD1_BTPM
LPC_LAD2_BTPM

CTPM and DisableBTPM


1

Reserve for EMI

NB_TRD0+
NB_TRD0NB_TRD1+
NB_TRD1NB_TRD2+
NB_TRD2NB_TRD3+
NB_TRD3-

LPC_LAD3_BTPM
LPC_LFRAME#_BTPM
LOM_PCIE_RST#_L

CTPM and DisableBTPM

1
2
L3504
BLM18AG601SN-3GP

1
C3526
SC4D7U6D3V3KX-GP

+1.2V_GPHY_PLLVDD
SCD1U10V2KX-4GP

2 C3527

2
1
C3528
SC4D7U6D3V3KX-GP

+1.2V_USB_PLLVDD
SCD1U10V2KX-4GP

2 C3529

1
2
L3505
BLM18AG601SN-3GP

U3506

LOM_SCLK
LOM_SO

1
2
L3507
BLM18AG601SN-3GP

8
7
6
5

VCC
RESET#
C
D

M25PE80-VMN6TP-GP

72.25P80.D01

Close to the power pins and


0.1u cap should be closer to Chip

XTALI
XTALO

LOM_XTALI
LOM_XTALO

M9
N9

LOM_XTAL1
2
200R2F-L-GP

1
R3514

CS#
NV_STRAP0
NV_STRAP1
SI
SO
SCLK
GPIO0
GPIO1
GPIO2

LCLK
LAD0
LAD1
LAD2
LAD3

SERIAL_DI
SERIAL_DO
LOW_PWR
PWR_DOWN

E3
E2
D3
F3
B8
C8
D8
D7

DOCK_LOM_SPD10LED_GRN#
DOCK_LOM_SPD100LED_ORG#

Place crystal less


than 0.75" (~1.9cm)
from LAN Controller

X3501
1

DK_LINKLED#
DK_SPD100LED#
DK_SPD1000LED#
DK_TRAFFICLED#
NB_LINKLED#
NB_SPD100L#
NB_SPD1000LED#
NB_TRAFFICLED#

74
74

NB_LOM_SPD10LED_GRN#
NB_LOM_SPD100LED_ORG#

1
R3515 1
R3516
1
R3517

NB_LOM_ACTLED_YEL#

C10

LOM_CS#

K2
M2

LOM_NV_STRAP0
LOM_NV_STRAP1

D9
C9
B9

LOM_SI
LOM_SO
LOM_SCLK

DY

1
R3519 1
R3520
1
R3521 1
R3523 1
R3524

DY
DY

R3518

N8
M8
C5

1
1

2
2 150R2F-1-GP
150R2F-1-GP
2
150R2F-1-GP

XTAL-25MHZ-96GP

2
4K7R2J-2-GP
2
2 4K7R2J-2-GP
4K7R2J-2-GP
2
2 4K7R2J-2-GP
2 4K7R2J-2-GP
4K7R2J-2-GP

DY
DY
DY

DOCK_LOM_ACTLED_YEL#
74
NB_LOM_SPD10LED_GRN#_R
76
NB_LOM_SPD100LED_ORG#_R
76
NB_LOM_ACTLED_YEL#_R

C3532
SC15P50V2JN-2-GP

C3533
SC15P50V2JN-2-GP

76

+3.3V_LAN

+3.3V_LAN

TP3512
TP3501

LOM_SERIAL_DI
1
DY 2
+3.3V_LAN
LOM_SERIAL_DO R3525 1
DY 2 4K7R2J-2-GP
R3527
4K7R2J-2-GP
LAN_LOW_PWR
J2
LAN_LOW_PWR 38
K11 SUPER_LOW_PWR
RN3501
VAUX_PRSNT
B6
2
3
+3.3V_LAN
R3536
H11 VMAIN_PRSNT
1
4
+3.3V_RUN
SRN1KJ-7-GP
0R0402-PAD-2-GP
J3
L3

R3531
1R2512J-1-GP

LFRAME#
LRESET#
SERIRQ
TPM_EN#
TPM_GPIO0
TPM_GPIO1
TPM_GPIO2/TPMSTATUS

C1
D1
D4
E1
E6
F1
G2
G4
H3
J6
J7
J11
K6
M10
N10

VAUXPRSNT
VMAINPRSNT
NB_RDAC
DK_RDAC
REGSUP12
REGSEN12
REGCTL12
REGIO_OUT12

NC#C1
NC#D1
NC#D4
NC#E1
NC#E6
NC#F1
NC#G2
NC#G4
NC#H3
NC#J6
NC#J7
NC#J11
NC#K6
NC#M10
NC#N10

PCIE_RXDP
PCIE_RXDN
PCIE_TXDP
PCIE_TXDN
REFCLK+
REFCLKREFCLK_SEL
PERST#
WAKE#
CLKREQ#

F13
G13
N11
M12
M11
N12

NB_LOM_RDAC
DOCK_LOM_RDAC

1K24R2F-GP
1K24R2F-GP

LOM_REGCTL12_PNP
LOM_REGCTL25_PNP

2
2

Dock

1
1 R3538
R3540

+1.2V_LOM
VDDC_IO
1
0R0402-PAD-2-GP

2
R3545

C3534
SCD1U10V2KX-4GP

C3535
SC4D7U6D3V3KX-GP

C3536
1

PCIE_PTX_GLANRX_P6_C
PCIE_PTX_GLANRX_N6_C
PCIE_PRX_GLANTX_P_C
PCIE_PRX_GLANTX_N_C

N5
M5
B3
B2
B5
C2

C3537
SCD047U10V2KX-2GP DY

2
SC1U10V2KX-1GP

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

CLK_PCIE_LOM
CLK_PCIE_LOM#
LOM_PCIE_RST#
LOM_CLKREQ#

PCIE_WAKE#

2
2

1
1 C3540
C3541

PCIE_PRX_GLANTX_P6
PCIE_PRX_GLANTX_N6

23
23
1
R3547
38,64,72

23
23
23
23

Design Current: 627mA


Q3501
NJT4030PT1G-GP

N7
M7
N3
M3

+3.3V_LAN_R

Logic High Voltage must


be 0.7V to 2.75V

+1.2V_LOM

C3538
SCD1U10V2KX-4GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

PLTRST4# 21,64,76
LOM_CLKREQ#

Wistron Corporation
R3546
10KR2J-3-GP

2
0R0402-PAD-2-GP

C3539
SC10U6D3V5KX-1GP

<Core Design>

+3.3V_RUN

GLAN - BCM5761E

23
Size
Document Number
Custom
Date:

LOM_CS#
LOM_SI

1
2
3
4

S#
Q
TSL#/W#
VSS

Numonyx

C3530
SC4D7U6D3V3KX-GP

BCM5761EA0KFBG-GP

SRN10KJ-6-GP

2 OF 2

E_SWITCH_CONT
ENERGYDET

R3544
10KR2J-3-GP

R3542
4K7R2J-2-GP

DY
DY
2

B_TPM

H8

R3534 LOM_PCIE_RST#_L
1B_TPM 2
IRQ_SERIRQ_R
1 R3535 2
LOM_TPM_EN#_R
0R0402-PAD-2-GP

R3530
4K7R2J-2-GP
38 LOM_TPM_EN#

B_TPM

SCD1U10V2KX-4GP

24,36,37,38,70 LPC_LAD3
24,36,37,38,70 LPC_LFRAME#

RN3507
1
SRN0J-6-GP 2

24,36,37,38,70
24,36,37,38,70
24,36,37,38,70

+1.2V_PCIE_SDSVDD

AT45DB081D-SSU-GP

RN3508
SRN0J-7-GP
8
7
B_TPM 6
5

2 C3525

1
2
L3503
BLM18AG601SN-3GP

1
C3519
SC4D7U6D3V3KX-GP

LPC_LAD0
LPC_LAD1
LPC_LAD2

1
2
3
4

CTPM and DisableBTPM

F4
C4

DK_TRD0+
DK_TRD0DK_TRD1+
DK_TRD1DK_TRD2+
DK_TRD2DK_TRD3+
DK_TRD3-

CLK_PCI_TPM

23,70 CLK_PCI_TPM

+3.3V_LAN

LOM_CABLE_DET

2
DY 0R2J-2-GP

E12
E13
D12
D13
C12
C13
B12
B13

NB_LOM_TRD0+
NB_LOM_TRD0NB_LOM_TRD1+
NB_LOM_TRD1NB_LOM_TRD2+
NB_LOM_TRD2NB_LOM_TRD3+
NB_LOM_TRD3-

1
R3522

2 C3518

38 DOCKED
38 LOM_CABLE_DETECT

DOCKED
SEL 0:RJ45.
SEL 1:Dock.

SCD1U10V2KX-4GP

R3548
100KR2J-1-GP

H12
H13
J12
J13
K12
K13
L12
L13

DOCK_LOM_TRD0+
DOCK_LOM_TRD0DOCK_LOM_TRD1+
DOCK_LOM_TRD1DOCK_LOM_TRD2+
DOCK_LOM_TRD2DOCK_LOM_TRD3+
DOCK_LOM_TRD376
76
76
76
76
76
76
76

Q3502
DMN66D0LDW-7-GP

+3.3V_LAN

Small PAD
+1.2V_PCIE_PLLVDD

IRQ_SERIRQ

GND

2
4

SIO_SLP_S3#

SIO_SLP_S3#

C3544
SCD1U10V2KX-4GP

Atmel

9,22,38,50

SI
SO
SCK

BCM5761EA0KFBG-GP
U3501B

74
74
74
74
74
74
74
74

1
8
2

LOM_CS#

1
1

G12

XTALVDDH

LOM_SO
LOM_SI
LOM_SCLK

+1.2V_LOM

5
4
3

WP#
CS#
RESET#

1
2

+1.2V_PCIE_SDSVDD

NB_GPHY_TVCOI
DY 2
DK_GPHY_TVCOI
DY 2 4K7R2J-2-GP
4K7R2J-2-GP
Populate resister for debug
R3512
R3513

L1

AVDDH
AVDDH
AVDDH

VCC

2
BLM18AG601SN-3GP

F12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AVDDL
AVDDL
AVDDL

+3.3V_LAN

U3505
6

1
L3508

+2.5V_BIASVDD

+3.3V_LAN

A1
A12
A13
B4
B10
D6
E5
E9
F6
F7
F8
F9
G5
G6
G7
G8
G9
G10
H4
H5
H6
H7
H10
J5
K1
K5
L6
M1
M4
M6
N1
N6

AUX_ON 37

8Mb for 5761E:


Main source: 72.45081.B01(Small PAD)
Second source: 72.45081.D01(Small PAD)

H1
G1

Close to LAN chip

VDDIO_USB

2
0R0402-PAD-2-GP

2
BLM18AG601SN-3GP

L7

AUX_ON_R 1
R3507

1
L3506

+2.5V_XTALVDD

+1.2V_USB_PLLVDD

C3524
SCD1U10V2KX-4GP

1
2

+3.3V_LAN

C3523
SCD1U10V2KX-4GP

C3522
SCD1U10V2KX-4GP

C3521
SCD1U10V2KX-4GP
2
1

C3520
SCD1U10V2KX-4GP
2
1

09/0529

E11
D11
C11

+2.5V_AVDD

2
BLM18AG601SN-3GP
1

1
L3501

+1.2V_AVDDL

1
2
C3517
SCD1U10V2KX-4GP

RN3504
SRN4K7J-8-GP

+3.3V_LAN

1
2
C3516
SCD1U10V2KX-4GP

SMBCLK
LOM_SMBCLK
LAN_SMBCLK1
SMBDATA
LOM_SMBDAT
LAN_SMBDATA1

1
2
C3515
SC4D7U6D3V3KX-GP

E8
A3
A5
C7
A4
A6

Design current: 89.6mA


Max current: 128mA

1
2
L3502
BLM18AG601SN-3GP

TP3503
TP3504
TP3505
TP3506

1
1
1
1

38

Put 0.1u cap close to Chip

HUSB_DN
HUSB_DP

APE_GPIO3
APE_GPIO4
APE_GPIO5
APE_GPIO6

LOM_SMB_ALERT#

+1.2V_LOM

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

TP3502

C3514
SC4D7U6D3V3KX-GP

SMB_CLK
APE_SMB_CLK0
APE_SMB_CLK1
SMB_DATA
APE_SMB_DATA0
APE_SMB_DATA1

APE_GPIO0
1
LOM_SMB_ALERT#

B7
B11
G11
D2
H2
K3
N2

C3513
SCD1U10V2KX-4GP

C3512
SCD1U10V2KX-4GP

C3511
SCD1U10V2KX-4GP

VDDIOPower Decoupling

VDDC_IO

1
M13

A11
A10
A9
A8
A7
A2
B1

1
2

1
2

VDDC_IO

APE_GPIO0
APE_GPIO1
APE_GPIO2
APE_GPIO3
APE_GPIO4
APE_GPIO5
APE_GPIO6

DMN66D0LDW-7-GP

+3.3V_LAN

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

4
3

E4
E7
F5
H9
J4
K4
K7
L4

C3510
SCD1U10V2KX-4GP

C3504
SCD1U10V2KX-4GP

C3509
SCD1U10V2KX-4GP

C3501
SCD1U10V2KX-4GP

1
2

C3508
SCD1U10V2KX-4GP

C3507
SCD1U10V2KX-4GP

1
2

C3503
SCD1U10V2KX-4GP

1
2

C3506
SCD1U10V2KX-4GP

C3505
SC4D7U6D3V3KX-GP

+3.3V_LAN

1 OF 2

U3501A

Core Power Decoupling

C3502
SC4700P50V2KX-1GP

R3505
4K7R2J-2-GP
2

LAN_SMBDAT

U3502

+1.2V_LOM

D 6
D 5
S 4

SRN2K2J-1-GP

DMN66D0LDW-7-GP

LOM_SMBDAT

3
4
RN3503

+3.3V_LAN

U3504
1 D
2 D
3 G

R3503
100KR2J-1-GP

+3.3V_ALW

R3502
100KR2J-1-GP

+15V_ALW

U3503
LOM_SMBCLK

1
2

Product : P802H /
71.05761.M02(Rev:B0)

4
3

LOM_SMBDAT
LOM_SMBCLK

+3.3V_ALW_2

RN3502

SYMBOL: 71.05761.00U

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

35

of

89

Symbol : Jetway, but linked to ZTE


Product : 71.08172.00W (ZTE)

SSID = TCM

TCM

+3.3V_RUN

U3601

1
2

3
5
12
13
14

BA1 NC#3
LCLK
LFRAME#
NC#5
GPIO15NC#12
LRESET#
GPIO16NC#13
SERIRQ
VR25
CLKRUN#
NC#14
PP
TESTBI/BADDBA0
TESTI

21
22
16
27
15
7
9
8

+3.3V_RUN

DY

R3601
10KR2J-3-GP

2
1

2
CLK_JETWAY_14M
R3604
0R0402-PAD-2-GP

23

DY

R3607
1KR2J-1-GP

C3605
SCD1U10V2KX-4GP

R3608
10KR2J-3-GP

+3.3V_RUN

CLK_PCH_14M_TCM
TCM_VR25

CLKRUN#_CTPM
TPM_PP
TCM_BA0
TCM_TEST1

TCM_BA1
TCM_PIN5

LPC_LFRAME#

DY

1
C3601

Z
2

71.08172.A0W
Symbol is J China TPM

R3610
10KR2J-3-GP

SC2D2U6D3V3KX-GP

TCM_BA0
R3613
1KR2J-1-GP

DY

0R2J-2-GP
R3614

R3612
10KR2J-3-GP

DY

SSX44-B-D-T-GP

DY

R3609
100KR2J-1-GP

22,37,38 CLKRUN#

11
18
25
4

C3604
SCD1U10V2KX-4GP

+3.3V_RUN

R3616
0R0402-PAD-2-GP
1
2 CLKRUN#_CTPM

GND
GND
GND
GND

C_TPM

C3603
SCD1U10V2KX-4GP

23 CLK_PCI_TPM_CHA
24,35,37,38,70 LPC_LFRAME#
35 LOM_PCIE_RST#
24,35,37,38 IRQ_SERIRQ

DY

LPCPD#
LAD0
LAD1
LAD2
LAD3 C_TPM

C_TPM

C3602
SC1U6D3V2KX-GP

DY

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

R3606
4K7R2J-2-GP

28
26
23
20
17

C_TPM

24,35,37,38,70
24,35,37,38,70
24,35,37,38,70
24,35,37,38,70

VDD
VDD
VDD

SP_TPM_LPC_EN_R

R3602
4K7R2J-2-GP
+3.3V_RUN

GPIO1 NC
GPIO2 NC
GPIO_EXPRESS_00

GPIO3

38 SP_TPM_LPC_EN

TCM_GPIO3

TP3601
R3615
0R0402-PAD-2-GP
1
2

10
19
24

1
2
6

Base
Address

BA1
PIN3

BA0
PIN9

EE/EF

7E/7F

2E/2F

4E/4F

1(default)
PIN12

FLASH

0
SRAM

J has internal PU with PIN12.

Default EE/EF as Amy recommended

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:
5

TCM

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

36

of

89

GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA
GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK
GPIO110/PS2_CLK2/GPTP-IN6
GPIO111/PS2_DAT2/GPTP-OUT6
GPIO112/PS2_CLK1A
GPIO113/PS2_DAT1A
GPIO114/PS2_CLK0A
GPIO115/PS2_DAT0A
GPIO154/I2C1C_DATA/PS2_CLK1B
GPIO155/I2C1C_CLK/PS2_DAT1B

C3710
SCD1U10V2KX-4GP
2
1

C3709
SCD1U10V2KX-4GP
2
1

C3708
SCD1U10V2KX-4GP
2
1

C3707
SCD1U10V2KX-4GP
2
1

C3706
SCD1U10V2KX-4GP
2
1

+3.3V_ALW

4
3

1
2

Dock

100KR2J-1-GP

RESET_OUT#
1
DY 2 8K2R2J-3-GP
R3724
09/0703
PCH side, pull down 8.2k

EC_XTAL1
EC_XTAL2
EC_32KHZ_OUT

X3701
+3.3V_ALW

1
3

2
1

C3712
SC4700P50V2KX-1GP

2
1
2

C3714
SC4700P50V2KX-1GP

BOARD_ID
SYSTEM_ID

Fonseca 14.1" DIS Revision


BOARD_ID

R3733
10KR2J-3-GP

BOARD_ID

SYSTEM_ID Cap. Value Cap. Value REV


4700pF
240k ohm X00
2k ohm

4700pF

130k ohm

X01

4700pF

4700pF

62k ohm

X02

4700pF

33k ohm

BGPO0
VCI_IN2#
VCI_OUT
VCI_IN1#
VCI_IN0#
VCI_OVRD_IN
VCI_IN3#

XTAL1
XTAL2
GPIO160/32KHZ_OUT

DOCK_SMB_DAT
DOCK_SMB_CLK
LCD_SMBDAT
LCD_SMBCLK
CKG_SMBDAT
CKG_SMBCLK
AUD_DOCK_SMBDAT
AUD_DOCK_SMBCLK
CHARGER_SMBDAT
CHARGER_SMBCLK
CARD_SMBDAT
CARD_SMBCLK
LAN_SMBDAT
LAN_SMBCLK

1
2
3
4

SRN100KJ-5-GP
DOCK_SMB_ALERT#
2 Dock 1
R3713
10KR2J-3-GP
RN3713
CARD_SMBDAT
4
1
CARD_SMBCLK
3
2
MSCLK
R3737

SRN2K2J-1-GP
1
100KR2J-1-GP

DY

10KR2J-3-GP

A59
B63
A60
A63
B67
B1
A1

EC_BGPO0
VCI_IN2#
ALW_ON
VCI_IN1#
POWER_SW_IN#
ACAV_IN
DOCK_PWR_SW#

C3719
SC4D7U6D3V3KX-GP

+3.3V_RUN

DOCK_SMB_DAT 74
DOCK_SMB_CLK 74
LCD_SMBDAT 54,81
LCD_SMBCLK 54,81
CKG_SMBDAT 7
CKG_SMBCLK 7
AUD_DOCK_SMBDAT 75
AUD_DOCK_SMBCLK 75
CHARGER_SMBDAT 45
CHARGER_SMBCLK 45
CARD_SMBDAT 72
CARD_SMBCLK 72
LAN_SMBDAT 35
LAN_SMBCLK 35

RN3718
ODD_DET#
H_SKTOCC#

1
2

4
3

SRN100KJ-6-GP

TP3717
+RTC_CELL

ALW_ON 46

RN3722
VCI_IN1#
VCI_IN2#

POWER_SW_IN# 39
ACAV_IN 39,45
DOCK_PWR_SW# 39

8
7
6
5

1
2
3
4

RN3719
POWER_SW_IN#
DOCK_PWR_SW#

+3.3V_ALW

1
2

4
3

POWER_SW#_MB 76
DOCK_PWR_BTN# 74

SRN10KJ-5-GP
C3720
Dock
SC1U6D3V2KX-GP

DY

RN3714
SRN2K2J-1-GP

C3701
SC1U6D3V2KX-GP

<Core Design>

DY
23 PCH_SMB_DATA

1 R3739

Wistron Corporation

LAN_SMBDAT

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

0R0402-PAD-2-GP
Title
23 PCH_SMB_CLK

1 R3740

LAN_SMBCLK

Size
Document Number
Custom

0R0402-PAD-2-GP

-1

Date:
5

8
7
6
5

SRN100KJ-5-GP

FWP#
R3703
33KR2J-3-GP

A3
B4
A4
B5
B7
A7
B48
B49
A47
B50
B52
A49
B53
A50

DELL PWR SW INF

X-32D768KHZ-40GPU

R3705
2KR2F-3-GP

GPIO003/I2C1A_DATA
GPIO004/I2C1A_CLK
GPIO005/I2C1B_DATA
GPIO006/I2C1B_CLK
GPIO012/I2C1H_DATA/I2C2D_DATA
GPIO013/I2C1H_CLK/I2C2D_CLK
GPIO130/I2C2A_DATA
GPIO131/I2C2A_CLK
GPIO132/I2C1G_DATA
GPIO140/I2C1G_CLK
GPIO141/I2C1F_DATA/I2C2B_DATA
GPIO142/I2C1F_CLK/I2C2B_CLK
GPIO143/I2C1E_DATA
GPIO144/I2C1E_CLK

R3732
10KR2J-3-GP

+3.3V_ALW

SMBUS INTERFACE

C3718
SC39P50V2JN-1GP

TP3709
DOCK_SMB_ALERT# 74
2
1
DY R3712
FFS_INT1 21,40
H_SKTOCC# 9
0R2J-2-GP
ME_SUS_PWR_ACK 22
1.5V_SUS_PWRGD 50
1
TP3713
1
TP3719
ALW_PWRGD_3V_5V 46
ODD_DET# 59
RESET_OUT# 22
1
TP3714
PCH_RSMRST# 22
AC_PRESENT 22
SIO_PWRBTN# 22

R3734

-1.10/0302

C3717
SC39P50V2JN-1GP

5
6
7
8

RN3708
BC_DAT_ECE1077
BC_DAT_ECE5028
BC_C_DAT
BC_DAT_EMC4022

MSDATA

MASTER CLOCK

NC#B17
NC#B34
NC#A46
NC#A48
NC#B51
NC#A64
NC#B68

TP3718

4
3
2
1

R3734 pull DN, Enable JTAG debug mode

HOST INTERFACE

A61
A62
B62

1
2
3
4

RN3720
CHARGER_SMBDAT
CHARGER_SMBCLK
AUD_DOCK_SMBCLK
AUD_DOCK_SMBDAT

PCH_ALW_ON

8
7
6
5

SRN2K2J-2-GP

DY

GPIO011/SMI#
GPIO061/LPCPD#
LDRQ#
SER_IRQ
LRESET#
PCI_CLK
LFRAME#
LAD0
LAD1
LAD2
LAD3
CLKRUN#
GPIO100/EC_SCI#

RN3701

1
DY 2
R3715
100KR2J-1-GP 24,35,36,38 IRQ_SERIRQ
21,38,70 PLTRST3#
21 CLK_PCI_EC
24,35,36,38,70 LPC_LFRAME#
24,35,36,38,70 LPC_LAD0
24,35,36,38,70 LPC_LAD1
24,35,36,38,70 LPC_LAD2
24,35,36,38,70 LPC_LAD3
22,36,38 CLKRUN#
25 SIO_EXT_SCI#

R3738

A6
A27
B29
A28
B30
A29
B31
A30
B32
A31
B33
A32
A33

SIO_EXT_SMI#
SIO_RCIN#
LPC_LDRQ#_MEC
IRQ_SERIRQ
PLTRST3#
CLK_PCI_EC
LPC_LFRAME#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
CLKRUN#
SIO_EXT_SCI#

25 SIO_EXT_SMI#
25 SIO_RCIN#

SRN10KJ-5-GP
PBAT_SMBDAT
PBAT_SMBCLK
CKG_SMBCLK
CKG_SMBDAT

+3.3V_ALW

BC-LINK

1
2

SRN2K2J-2-GP

1
2

DDR_HVREF_RST_GATE
CPU1.5V_S3_GATE

EC_GPIO001
DOCK_SMB_ALERT#
FFS_INT#
H_SKTOCC#
ME_SUS_PWR_ACK
1.5V_SUS_PWRGD
EC_GPIO017
EC_GPIO026
ALW_PWRGD_3V_5V
ODD_DET#
RESET_OUT#
EC_GPIO125
PCH_RSMRST#
AC_PRESENT
SIO_PWRBTN#

4
3

4
3

4
3

SRN100KJ-6-GP

B2
A2
B8
B18
A8
B9
A9
A14
B15
A17
B39
A44
B47
A54
B58

RN3705
HOST_DEBUG_TX
HOST_DEBUG_RX

DDR_ON 42,50
HOST_DEBUG_TX 64
HOST_DEBUG_RX 64,70
RUNPWROK 9,38,58
-1.10/0301
EN_INVPWR 54
TP3706
TP3708
TP3705
DDR_HVREF_RST_GATE 9
TP3707
CPU1.5V_S3_GATE 42
MSDATA 64,70
MSCLK
64,70
SIO_A20GATE 25
PS_ID
43
BAT1_LED# 66
BAT2_LED# 66

EP

RN3716

GPIO123/BCM_A_CLK
GPIO122/BCM_A_DAT
GPIO121/BCM_A_INT#
GPIO022/BCM_B_CLK
GPIO023/BCM_B_DAT
GPIO024/BCM_B_INT#
GPIO044/BCM_C_CLK
GPIO043/BCM_C_DAT
GPIO042/BCM_C_INT#
GPIO047/LSBCM_D_CLK
GPIO046/LSBCM_D_DAT
GPIO045/LSBCM_D_INT#
GPIO032/GPTP-IN3/BCM_E_CLK
GPIO31/GPTP-OUT2/BCM_E_DAT
GPIO30/GPTP-IN2/BCM_E_INT#

GPIO001/ECSPI_CS1
GPIO002/ECSPI_CS2
GPIO014/GPTP-IN7/HSPI_CS1
GPIO040/GPTP-OUT3/HSPI_CS2
GPIO015/GPTP-OUT7
GPIO016/GPTP-IN8
GPIO017/GPTP-OUT8
GPIO26/GPTP-IN1
GPIO27/GPTP-OUT1
GPIO041
GPIO107/nRESET_OUT
GPIO125/GPTP-IN5
GPIO126
GPIO151/GPTP-IN4
GPIO152/GPTP-OUT4

VR_CAP1

SRN100KJ-6-GP
AUX_ON
2
1
100KR2J-1-GP
R3720

DY

TP3716
68 BC_CLK_ECE1077
68 BC_DAT_ECE1077
68 BC_INT#_ECE1077
30
BEEP
22 SIO_SLP_S5#
38,45 ACAV_IN_NB

A43
B45
A42
A12
B13
A13
B20
A18
B19
A20
B21
A19
A16
B16
A15

SYSTEM_ID
BOARD_ID
DDR_ON
HOST_DEBUG_TX
HOST_DEBUG_RX
RUNPWROK
EN_INVPWR
EC_GPIO101
1
EC_GPIO103
1
EC_GPIO105
1
DDR_HVREF_RST_GATE
EC_GPIO104
1
CPU1.5V_S3_GATE
MSDATA
MSCLK
SIO_A20GATE
PS_ID
BAT1_LED#
BAT2_LED#
FWP#

GENERAL PURPOSE I/O

KBC_VR_CAP B12

DDR_ON
SUS_ON

BC_CLK_ECE5028
BC_DAT_ECE5028
BC_INT#_ECE5028
BC_CLK_EMC4022
BC_DAT_EMC4022
BC_INT#_EMC4022
EC_GPIO44
BC_C_DAT
EC_GPIO42
BC_CLK_ECE1077
BC_DAT_ECE1077
BC_INT#_ECE1077
BEEP
SIO_SLP_S5#
ACAV_IN_NB

A10
B10
B14
B44
B46
B26
A25
B36
B37
B38
A34
A35
A36
A40
B43
A45
A55
A57
B61
B65

EN_INVPWR

100KR2J-1-GP
RN3710
4
1
3
2

GPIO050/FAN_TACH1
GPIO051/FAN_TACH2
GPIO052/FAN_TACH3
GPIO053/PW M0
GPIO054/PW M1
GPIO055/PW M2
GPIO056/PW M3

VSS2
VSS5
VSS7
VSS8

R3741

BC_CLK_ECE5028
BC_DAT_ECE5028
BC_INT#_ECE5028
BC_CLK_EMC4022
BC_DAT_EMC4022
BC_INT#_EMC4022
TP3715

B22
A21
B23
B24
A23
B25
A24

B27
B60
B11
B28

38
38
38
39
39
39

DOCK_POR_RST#
SUS_ON
AUX_ON
BREATH_LED#
PCH_ALW_ON
EC_GPIO55
EC_GPIO56

AGND

-1.10/0301

1
1

FAN PWM & TACH

B17
B34
A46
A48
B51
A64
B68

1MR2J-1-GP

Dock
2

C3715
SCD1U10V2KX-4GP

C3716
DY SC4D7P50V2CN-1GP

42 SUS_ON
35 AUX_ON
R3711
66,74 BREATH_LED#
Dock
42 PCH_ALW_ON
TP3711
TP3712

GPIO145/JTAG_TDI
GPIO146/I2C1K_CLK/JTAG_TDO
GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK
GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS
JTAG_RST#

MEC5045-LZY-GP

0 = Reset JTAG I/F


1 = Disable
74 DOCK_POR_RST#

A51
B55
B56
A53
B57

B66

Place close
to Pin58

JTAG INTERFACE

JTAG_TDI
JTAG_TDO
JTAG_CLK
JTAG_TMS
JTAG_RST#

70 JTAG_TDI
70 JTAG_TDO
70 JTAG_CLK
70 JTAG_TMS

CLK_PCI5035

C3705
SCD1U10V2KX-4GP
2
1

GPIO021/RC_ID1
GPIO020/RC_ID2
GPIO025/UART_CLK
GPIO120/UART_TX
GPIO124/GPTP-OUT5/UART_RX
VCC_PRW GD
GPIO060/KBRST
GPIO101/ECGP_SCLK
GPIO103/ECGP_SIN
GPIO105/ECGP_SOUT
GPIO102/HSPI_SCLK
GPIO104/HSPI_MISO
GPIO106/HSPI_MOSI
GPIO116/MSDATA
GPIO117/MSCLK
GPIO127/A20M
GPIO153/LED3
GPIO156/LED1
GPIO157/LED2
FW P#

C1

MISC INTERFACE

VSS_RO

SCD1U10V2KX-4GP

A5
B6
A37
B40
A38
B41
A39
B42
B59
A56

68 CLK_TP_SIO
68 DAT_TP_SIO
74 CLK_KBD
74 DAT_KBD
74 CLK_MSE
74 DAT_MSE
44 PBAT_SMBDAT
44 PBAT_SMBCLK

R3710

VTT_PWRGD 52

RN3703

PS/2 INTERFACE

KBC_SDA1
KBC_SCL1

23 KBC_SDA1
23 KBC_SCL1

DY 10R2J-2-GP

2
10KR2J-3-GP
2
0R0402-PAD-2-GP

DOCK_SMB_CLK
DOCK_SMB_DAT

B54

C3713

DY

1
2

1
R3707
1
R3709

SRN2K2J-1-GP

CLK_PCI_EC

C3704
SCD1U10V2KX-4GP
2
1

JTAG_RST#

C3703
SCD1U10V2KX-4GP
2
1

U3701

A11
A22
B35
A41
A58
A52
B3
A26

CLK_KBD
DAT_KBD
CLK_MSE
DAT_MSE

8
7
6
5

SRN4K7J-10-GP

100R2J-2-GP

Dock

VBAT

1
2
3
4

B64

C3702
SCD1U10V2KX-4GP

RN3702

+3.3V_RUN
RUNPWROK

VTR
VTR
VTR
VTR
VTR
VTR
VTR
VTR

0R0402-PAD-2-GP

+5V_RUN

R3704
10KR2J-3-GP

2
1

1 R3702

+3.3V_ALW

R3706

+3.3V_ALW

SSID = KBC

+RTC_CELL

C3711
SC10U6D3V5MX-3GP

KBC - MEC5045

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

37

of

89

DY

WIRELESS_ON#/OFF
AUD_HP_NB_SENSE
DOCK_HP_DET
DOCK_MIC_DET

3.3V DELAY LDO


1.8V DELAY LDO
GFX 1.1V LDO
VGA_IDENTIFY
High = Discrete
Low = UMA
2

TP3809
TP3810
86 GFX_CORE_PWRGD
TP3816
TP3819
42,51 3.3V_RUN_GFX_ON
51 1.8V_RUN_GFX_ON
86 GFX_MEM_VTT_ON

1
1

+3.3V_ALW

TEMP_ALERT#
10KR2J-3-GP

R3815
100KR2J-1-GP

35 LAN_LOW_PWR
66 CAP_LED#
35 LOM_TPM_EN#
TP3817

1 R3817 2
0R0402-PAD-2-GP

TP3818
22 PCH_PCIE_WAKE#
64 WLAN_RADIO_DIS#

RN3804
0.75V_DDR_VTT_ON
1
RUN_ON
2
LCD_TST
3
CPU_VTT_ON
4
SRN100KJ-5-GP

8
7
6
5

GFX_CORE_ON
1
PBATT_OFF
2
SRN100KJ-6-GP
RN3807

1
2
3
4

8
7
6
5

1
1

B32
A31
B33
B15
A15
B16
A16

GPIOD1
GPIOD2
GPIOD3
GPIOD4
GPIOD5
GPIOD6
GPIOD7

SIO_GPIOE0
SIO_GPIOE1
GFX_CORE_PWRGD
SIO_GPIOE3
SIO_GPIOE4
3.3V_RUN_GFX_ON
1.8V_RUN_GFX_ON
GFX_MEM_VTT_ON

A1
B2
A2
B3
A3
B45
A42
B4

GPIOE0/RXD
GPIOE1/TXD
GPIOE2/RTS#
GPIOE3/DSR#
GPIOE4/CTS#
GPIOE5/DTR#
GPIOE6/RI#
GPIOE7/DCD#

SIO_GPIOF0
SIO_GPIOF1
SIO_GPIOF2
SIO_GPIOF3
SIO_GPIOF4
VGA_IDENTIFY
DOCK_IDENTIFY
LOM_SMB_ALERT#

A59
B62
A58
B61
A56
B59
A55
B58

GPIOF0/IRMODE/IRRX3A
GPIOF1/IRRX2
GPIOF2/IRTX2
GPIOF3/IRMODE/IRRX3B
GPIOF4
GPIOF5
GPIOF6
GPIOF7

LAN_LOW_PWR
CAP_LED#
LOM_TPM_EN#
SIO_GPIOG3
SIO_EXT_WAKE#_R
SIO_GPIOG5
PCH_PCIE_WAKE#
WLAN_RADIO_DIS#

B47
A45
B48
A46
B49
A47
B50
A48

GPIOG0
GPIOG1
GPIOG2
GPIOG3
GPIOG4
GPIOG5
GPIOG6
GPIOG7

WIRELESS_ON#/OFF
BT_RADIO_DIS#
WWAN_RADIO_DIS#
LOM_CABLE_DETECT
EXPRCRD_PWREN#
EXPRCRD_STDBY#
SLICE_BAT_PRES#
PWR_BTN_BD_DET#

64 WIRELESS_ON#/OFF
73 BT_RADIO_DIS#
76 WWAN_RADIO_DIS#
35 LOM_CABLE_DETECT
72 EXPRCRD_PWREN#
72 EXPRCRD_STDBY#
74 SLICE_BAT_PRES#
76 PWR_BTN_BD_DET#

RN3801

4
3

1
1
1
1
1

35 LOM_SMB_ALERT#

25 SIO_EXT_WAKE#

TP3811
TP3812
TP3813
TP3814
TP3815

1
1

TP3825
2

3.3V_RUN_GFX_ON
PANEL_BKEN_GPU
GFX_MEM_ON
LCDVDD_EN_GPU

1
1

IRTX
IRRX

B13
A13
A53
B57
B14
A14
B17
B18

GPIOH0
GPIOH1
SYSOPT1/GPIOH2
SYSOPT0/GPIOH3
GPIOH4
GPIOH5
GPIOH6
GPIOH7

B60
A57

IRTX
IRRX

R3820
10KR2J-3-GP

1
2
1

SRN10KJ-5-GP

1.8V_RUN_GFX_ON
100KR2J-1-GP

NOCRD_SC
2

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
PLTRST3#
CLK_PCI_5028
CLKRUN#
LPC_LDRQ0#
LPC_LDRQ1#
IRQ_SERIRQ
CLK_SIO_14M

VSS

B51

DLAD0
DLAD1
DLAD2
DLAD3
DLFRAME#
DCLKRUN#
DLDRQ1#
DSER_IRQ

B29
B28
A25
A24
B23
A19
B24
A20

D_LAD0
D_LAD1
D_LAD2
D_LAD3
D_LFRAME#
D_CLKRUN#
D_DLDRQ1#
D_SERIRQ

BC_INT#
BC_DAT
BC_CLK

A29
B31
A30

BC_INT#_ECE5028
BC_DAT_ECE5028
BC_CLK_ECE5028

PW RGD

A4

RUNPWROK

OUT65

B56

SP_TPM_LPC_EN

TEST_PIN

B19

TEST_PIN

CAP_LDO

B46

CAP_LDO

VSS
VSS
VSS
VSS
VSS
VSS

A9
A18
B27
B39
A44
B64

1
R3819

C3807
SCD1U10V2KX-4GP

ME_FWP 24
NB_AC_OFF 43,44,45
1.8V_RUN_PWRGD 51
TP3807
TEMP_ALERT# 25,58
RUN_ON 42,51,72,86
CPU_CATERR# 9
SPI_WP#_SEL 62
LPC_LAD[0..3]

24,35,36,37,70
C

Place close to
Pin.A28

LPC_LFRAME# 24,35,36,37,70
PLTRST3# 21,37,70
CLK_PCI_5028 21
CLKRUN# 22,36,37
LPC_LDRQ0# 24
LPC_LDRQ1# 24
IRQ_SERIRQ 24,35,36,37
CLK_SIO_14M 23

CLK_PCI_5028

D_LAD0 74
D_LAD1 74
D_LAD2 74
D_LAD3 74
D_LFRAME# 74
D_CLKRUN# 74
D_DLDRQ1# 74
D_SERIRQ 74

BC_INT#_ECE5028 37
BC_DAT_ECE5028 37
BC_CLK_ECE5028 37
RUNPWROK

R3812
10R2J-2-GP

DY

C3808
SC4D7P50V2CN-1GP

DY

Place close to
Pin.A32 CLK_SIO_14M

9,37,58

SP_TPM_LPC_EN 36

R3818
10R2J-2-GP DY

2
1KR2F-3-GP
C3809
SC4D7U6D3V3KX-GP

C3810
SC4D7P50V2CN-1GP

CRD_DET1
CRD_DET0
R3816
100KR2J-1-GP

NOCRD_PCC

CRD_DET1

CRD_DET0

Function

Low

Low

No Option Installed

DY

<Core Design>

Low

High

Smartcard

Wistron Corporation

High

Low

Cardbus

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

High

High

Express Card

Title
Size
Document Number
Custom
Date:

C3806
SC10U6D3V5KX-1GP

C3805
SCD1U10V2KX-4GP

C3804
SCD1U10V2KX-4GP

A27
A26
B26
B25
A21
B22
A28
B20
A23
A22
B21
A32

R3823
100KR2J-1-GP

1
R3834

R3811
100KR2J-1-GP

PCC_EXP SC_EXP
2

MODC_EN
GFX_MEM_VTT_ON

4
3

R3822
100KR2J-1-GP
RN3808

1
2

LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
PCICLK
CLKRUN#
LDRQ0#
LDRQ1#
SER_IRQ
14_318MHZ

AUX_EN_WOWL 64
TP_DET# 68
SIO_SLP_LAN# 22
1
TP3804
GPIO_PSID_SELECT 43
CRT_SWITCH 75
DOCK_HP_DET 75
DOCK_MIC_DET 75

C1

+3.3V_RUN
SRN100KJ-5-GP

ME_FWP
NB_AC_OFF
1.8V_RUN_PWRGD
SIO_GPIOK3
TEMP_ALERT#
RUN_ON
CPU_CATERR#
SPI_WP#_SEL

Dock

SRN100KJ-5-GP

1
R3831

TP3820
42 MODC_EN

A8
B9
B10
A10
B11
A11
B12
A12

1
2
3
4

8
7
6
5

ECE5028-LZY-GP

LID_CL_SIO#
CPU_VTT_ON
GFX_CORE_ON
CRD_DET0
CRD_DET1
SIO_GPIOD6
MODC_EN

1
2
3
4

R3835
100KR2J-1-GP

GPIOK0
GPIOK1
GPIOK2
GPIOK3
GPIOK4
GPIOK5
GPIOK6
GPIOK7

8
7
6
5

RN3806

69 LID_CL_SIO#
52 CPU_VTT_ON
86 GFX_CORE_ON

GFX CORE

AUX_EN_WOWL
TP_DET#
SIO_SLP_LAN#
SIO_GPIOJ3
GPIO_PSID_SELECT
CRT_SWITCH
DOCK_HP_DET
DOCK_MIC_DET

D_DLDRQ1#
D_SERIRQ
D_CLKRUN#

CLK_PCI50282

SP_TPM_LPC_EN
10KR2J-3-GP

B67
A64
A5
B6
A6
B7
A7
B8

RN3809

EP

DY

GPIOJ0
GPIOJ1
GPIOJ2
GPIOJ3
GPIOJ4
GPIOJ5
GPIOJ6
GPIOJ7

+3.3V_RUN

SIO_SLP_M# 22
0.75V_DDR_VTT_ON 50
SIO_SLP_S4# 22,50,72
SIO_SLP_S3# 9,22,35,50
IMVP_PWRGD 39,47
IMVP_VR_ON 47

DOCK_IDENTIFY

1
R3808

SIO_SLP_M#
0.75V_DDR_VTT_ON
SIO_SLP_S4#
SIO_SLP_S3#
IMVP_PWRGD
IMVP_VR_ON
DOCK_AC_OFF_EC

SRN100KJ-5-GP

GPIOB0/INIT#
GPIOB1/SLCTIN#
GPIOC2/SLCT
GPIOC3/PE
GPIOC4/BUSY
GPIOC5/ACK#
GPIOC6/ERROR#
GPIOC7/ALF#
GPIOD0/STROBE#
GPIOC1/PD7
GPIOC0/PD6
GPIOB7/PD5
GPIOB6/PD4
GPIOB5/PD3
GPIOB4/PD2
GPIOB3/PD1
GPIOB2/PD0

R3836
100KR2J-1-GP

B63
A60
A61
B65
A62
B66
A63

DY

A33
B36
A34
B37
A35
LCDVDD_EN_GPU
B38
A36
PSID_DISABLE#
A37
PANEL_BKEN_GPU
B40
DOCKED
A38
DOCK_DET#
B41
AUD_NB_MUTE
A39
MCARD_WWAN_PWRENB42
LCD_VCC_TEST_EN
A40
SIO_GPIOB4
B43
AUD_HP_NB_SENSE
A41
SIO_GPIOB2
B44

43 PSID_DISABLE#
54,81 PANEL_BKEN_GPU
35 DOCKED
44,74,75 DOCK_DET#
30 AUD_NB_MUTE
65 MCARD_WWAN_PWREN
54 LCD_VCC_TEST_EN
1
TP3824
30,60 AUD_HP_NB_SENSE
1
TP3808

+3.3V_RUN

+3.3V_RUN

USB_SIDE_EN#
EN_I2S_NB_CODEC#
GFX_MEM_ON
EN_DOCK_PWR_BAR

GPIOI1
GPIOI2
GPIOI3
GPIOI4
GPIOI5
GPIOI6
GPIOI7

63,76 USB_SIDE_EN#
75 EN_I2S_NB_CODEC#
42,51 GFX_MEM_ON
44 EN_DOCK_PWR_BAR
1
TP3822
54,80 LCDVDD_EN_GPU

GPIOA0
GPIOA1
GPIOA2
GPIOA3
GPIOA4
GPIOA5
GPIOA6
GPIOA7

CLK_SIO14M 2

1 DY
R3807
0R2J-2-GP

9,22,58 XDP_DBRESET#
54 LCD_TST

2 USB_SIDE_EN#
100KR2J-1-GP

B52
A49
B53
A50
B54
A51
B55
A52

1.5V VRAM
+3.3V_ALW

PBAT_PRES#
SCRL_LED#
NUM_LED#
SIO_GPIOA3
PBATT_OFF
MDC_RST_DIS#
PCIE_WAKE#
SIO_GPIOA7

DY

44 PBAT_PRES#
66 SCRL_LED#
66 NUM_LED#
TP3802
44 PBATT_OFF

SRN100KJ-5-GP

VCC1
VCC1
VCC1
VCC1
VCC1

U3801

B1
B34
B35
B68

SLICE_BAT_PRES#
TP_DET#
PCIE_WAKE#
PWR_BTN_BD_DET#

B5
A17
B30
A43
A54

74LVC1G08GW-1-GP

76 MDC_RST_DIS#
35,64,72 PCIE_WAKE#
TP3803

C3802

DY SCD1U10V2KX-4GP

NC#B1
NC#B34
NC#B35
NC#B68

RN3805

1
R3805

44

DOCK_AC_OFF_R

GND

ADock

C3803
SCD1U10V2KX-4GP

VCC

C3801
SCD1U10V2KX-4GP

37,45 ACAV_IN_NB

8
7
6
5

+3.3V_ALW

U3802
DOCK_AC_OFF_EC

+3.3V_ALW

+3.3V_ALW

SSID = KBC
1
2
3
4

SIO - MEC5028

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

38

of

89

SSID = Thermal
37 BC_DAT_EMC4022

BC Bus clock and data signal trace length


should be matched with +/- 0.1 inch.

37 BC_CLK_EMC4022

1
1

C3901
SC470P50V2JN-GP

REM_DIODE3_N, REM_DIODE3_P routing together.


Trace width / Spacing = 10 / 10 mil
Place near the bottom SODIMM

close to the
Guardian pins

SYS_IMON

Place C3902 close to the Q3902 as possible

Place C3906 close to Q3905

2
U3901

7
8

Place optimally between VGA and PCH


Place C3904 close to Q3901

81 GPU_THERM_DP

PORT 3

C3908
SC2200P50V2KX-2GP

close to the
Guardian pins

REM_DIODE1_P
REM_DIODE1_N

24
23

DP1/VREF_T
DN1/THERM

REM_DIODE4_P
REM_DIODE4_N

27
26

DP2/DN4
DN2/DP4

GPU_THERM_DP
GPU_THERM_DN

81 GPU_THERM_DN

30
29

C3919

SMDATA/BC_DATA
SMCLK/BC_CLK

22R2J-2-GP
+3.3V_SUS

C3918

SCD1U10V2KX-4GP

2
C3910

PCH_PWRGD#

1
SC1U6D3V2KX-GP
THERM_VDD_PWRGD 13
THERM_3V_PWROK# 12

1 R3901 2
0R0402-PAD-2-GP

VIN
VCP

25
31

ATF_INT#/BC_IRQ#
RTC_PW R3V
POW ER_SW #
ACAVAIL_CLR
GPIO3/PW M/THERMTRIP_SIO
SYS_SHDN#
VDD_PW RGD
3V_PW ROK#

9
20
21
15
19

DP3/DN5
DN3/DP5

THERM_B1

1
Q3906
MMBT3904-7-F-GP

3VSUS_THRM 1
R3914

17
18

THERMTRIP2#
THERMTRIP3#

THERMAL_VSET

28

VSET

23VSUS_THRM_1
4K7R2J-2-GP

32

ADDR_MODE/XEN

FAN1_VOUT

58 FAN1_VOUT

9,25 H_THERMTRIP#

58 FAN1_TACH_FB

VDD

THERMTRIP2#
THERMTRIP3#

1
R3913
2K2R2J-2-GP

+1.05V_VTT

R3915
953R2F-GP

1
2

C3911
SCD1U10V2KX-4GP

C3912
SCD1U10V2KX-4GP
2
1

Rset=953,Tp=88degree

C3913
SCD1U10V2KX-4GP

1
16

1
2

RN3901
SRN8K2J-3-GP

4
3

DY

+RTC_CELL
C3909

FAN1_TACH_FB
FAN1_DET#

2
3

VDD_HA
VDD_HB

VDD_L

4
5

FAN_OUTA
FAN_OUTB

10
11

TACH/GPIO1
GPIO2

+5V_RUN

R3928
5K62R2F-GP

R3905 ~ if use 4.7k


about 2% inaccuracy for IMON
Place near fork into U3901

SYS_IMON_4022
CPU_IMON_4022
R3905

TEST1
TEST2

2
R3907
BC_INT#_EMC4022
POWER_SW_IN#_4022
ACAV_IN
THERMTRIP_SIO
2
THERM_STP# R3909
R3912

1KR2F-3-GP

CPU_IMON 12,47
+3.3V_ALW

10KR2J-3-GP

BC_INT#_EMC4022

DY

DY

37

ACAV_IN 37,45
+3.3V_SUS

10KR2J-3-GP

THERM_STP# 46
+RTC_CELL

47KR2J-2-GP

14
22

GND_SLG

SC1U6D3V2KX-GP
2
1

R3906

DY
2

+3.3V_SUS
3VSUS_THRM

close to the
Guardian pins

C3905
SC2200P50V2KX-2GP

Q3901
MMBT3904-7-F-GP

DY
SC100P50V2JN-3GP

PORT 2 C3904

PORT
4
1

Skin Temp Sensor

Q3905
DY MMBT3904-7-F-GP

R3923
12K7R2F-GP

SCD22U25V3KX-GP

C3906
SC100P50V2JN-3GP

Q3905 and C3906 Place near DIMM

45

Q3902
MMBT3904-7-F-GP

1
2

C3902
SC100P50V2JN-3GP

Q3902 and C3902 Place under CPU

PORT 1

33

C3915
SCD1U10V2KX-4GP

2
1

POWER_SW_IN#_R

POWER_SW_IN#

37

R3924
0R2J-2-GP
1 DY
2

1N-Dock 2
R3925
0R2J-2-GP

1 R3921 2
0R0402-PAD-2-GP

37

DockBAT54A-3-GP

R3920
100KR2J-1-GP

FAN1_DET# 58

G
A

<Core Design>

Dock

C3916
C3917 DY
DY SCD1U10V2KX-4GP
SC10U10V5KX-2GP

D
1 R3926 2IMVP_PWRGD_R
0R0402-PAD-2-GP

38,47 IMVP_PWRGD

+RTC_CELL

POWER_SW_IN#_4022

1
2

+3.3V_RUN

THERM_VDD_PWRGD
PCH_PWRGD#

Q3908
2N7002A-7-GP

DOCK_PWR_SW#

D3901
+3.3V_RUN

R3927
100KR2J-1-GP

RN3902
SRN100KJ-6-GP

1 R3918 2
0R0402-PAD-2-GP

1
2

2
1

DOCK_PWR_SW#_R

09/0824, symbol updated

4
3

+3.3V_SUS

C3914
SC10U10V5KX-2GP

EMC4022-1-EZK-TR-1-GP-U

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Thermal, Fan controller

Size
Document Number
Custom
Date:
5

Thursday, March 18, 2010

Sheet
1

39

Rev

-1

Fonseca 14.1" DIS


of

89

SSID = User.Interface

Free Fall Sensor

1
C4002
SC1U10V3KX-3GP

C4001
SCD1U10V2KX-4GP

-1.10/0310

+3.3V_RUN

+3.3V_RUN
C

2
DY 0R2J-2-GP

14

SCL/SPC

INT1

FFS_INT1

CLK_SDATA_HDDFALL

13

SDA/SDI/SDO

INT2

FFS_INT2_R

HDD_FALL_SDO

12

SDO

+3.3V_RUN

DY

FFS_INT1 21,37

+3.3V_RUN

CS

3
11

GND
GND
GND
GND

RESERVED#3
RESERVED#11

2
4
5
10

R4005
100KR2J-1-GP

R4011
0R2J-2-GP

CLK_SCLK_HDDFALL

FALL_INT2

DE351DLTR8-GP

R4008
10KR2J-3-GP

DY
2

R4006
100KR2J-1-GP

DY

Q4002 +3.3V_RUN
DMN66D0LDW-7-GP

+3.3V_RUN

09/0422
(#1) Just pull +3.3V_RUN ~ Ref. Rothschild
(#2) FAE/ DY is ok, chip internal pull-up resistors
(#3) From spec, Slave ADdress(SAD) is 001110xb
Pull HIGH SAD is 0011101b
Pull GND SAD is 0011100b

1
R4004

R4001
100KR2J-1-GP

+3.3V_RUN

DY

VDD_IO

VDD

U4001

FFS_INT2_R

FFS_INT2 59

R4007

DY

2
0R2J-2-GP
FFS_INT2_R 25

18,19,23,58 PCH_SMBCLK_MEM

1
R4009

2
0R0402-PAD-2-GP

CLK_SCLK_HDDFALL

18,19,23,58 PCH_SMBDATA_MEM

1
R4010

2
0R0402-PAD-2-GP

CLK_SDATA_HDDFALL

HDD_FALL_INT2#
INT2 will pull as push pull and resverse R4006
CLK_SCLK_HDDFALL
CLK_SDATA_HDDFALL

7
7

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Note
(1) Keep all signals are the same trace width. (included VDD, GND).
(2) No VIA under IC bottom.

Title
Size
A3
Date:

Free Fall Sensor

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

40

of

89

SSID = Reset.Suspend

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Power On Logic

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

41

of

89

SSID = Reset.Suspend

G
2

4
3

6A

R4299
100R2F-L1-GP-U

Q4299
DMN66D0LDW-7-GP
R4204
20KR2J-L2-GP

C4203
SC10U10V5KX-2GP

SI3456DDV-T1-GE3-GP
C4202
SC4700P50V2KX-1GP

S G D

+3.3V_DELAY

Id: 2A
Rds: 0.15ohm

3.3V_ALW_1

D 6
D 5
S 4
1

3V_SUS_ENABLE

R4296
100KR2J-1-GP

+3.3V_SUS

U4202
1 D
2 D
3 G

+3.3V_ALW

Q4202
DMN66D0LDW-7-GP

+3.3V_ALW

Q4298
SI2301CDS-T1-GE3-GP

Design current: 1700mA


Max current: 2400mA

R4203
100KR2J-1-GP

1
2SUS_ON_3V#
R4202
100KR2J-1-GP
D G

For Discrete

+15V_ALW
1

+3.3V_ALW_2

37 SUS_ON

3.3V_DELAY_1

Design current: 2152mA


Max current: 3074.4mA

2
1
1

R4208
20KR2J-L2-GP

Optional RC network to fine tune PWR SEQ.

-1.10/0302

Design current: 1750mA


Max current: 2500mA

SI3456DDV-T1-GE3-GP

4.5A

DY
2

1.5V_RUN_DISCHARGE

1
2

38,51,72,86 RUN_ON

2
1
1
R4224

RUN_ON_1.5V
2
DY 0R2J-2-GP

2
DY 0R2J-2-GP

R4236

<Core Design>
C4219
SC4700P50V2KX-1GP

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

37 CPU1.5V_S3_GATE

1
R4235

2
0R0402-PAD-2-GP

Power Plane Enable

Size
Document Number
Custom

RUN_ON_1.5V#

Date:
4

2
2

1
R4234

100R2J-2-GP

2
1
1

G
37,50 DDR_ON

C4220

DY SC10U10V5KX-2GP
DY 20KR2J-L2-GP

SI4800BDY-T1-GP

Q4209
2N7002A-7-GP
R4233
1

6.5A

1
2
3
4

S G D
1.5V_CPU_ENABLE

+1.5V_RUN

R4225
100KR2J-1-GP

C4218
SC4700P50V2KX-1GP

+1.5V_RUN_CPU
8
7
6
5

1
Q4207
DMN66D0LDW-7-GP

R4223

+1.5V_SUS
U4207

1
1

C4217

DY SC10U10V5KX-2GP
DY 20KR2J-L2-GP

SIR460DP-T1-GE3-GP

+15V_ALW

D G S
6

1
2
3
4

RUN_ON_1.5V_CPU#
2 RUN_ON_1.5V_CPU#
100KR2J-1-GP

11A

S
S
S
G

1
R4226

1 2

R4222
100KR2J-1-GP

+3.3V_ALW_2

+1.5V_RUN
U4206
D
D
D
D

1.5V_RUN_CPU_DISCHARGE D

100R2J-2-GP

S G D

1.5V_RUN_ENABLE
2
0R0402-PAD-2-GP

+1.5V_SUS
8
7
6
5

1
4

1
R4229

DMN66D0LDW-7-GP
38,51 GFX_MEM_ON

R4237

Design current: 2400mA


Max current: 3500mA
+15V_ALW

C4201 DY
SC10U6D3V5MX-3GP

Q4210
2N7002A-7-GP

+1.5V_RUN_CPU

C4221
R4227
SCD1U10V2KX-4GP
DY 20KR2J-L2-GP

2
0R0402-PAD-2-GP

D G S

R4220 DY
100KR2J-1-GP

1
R4238

DY

2 RUN_ON_1.5V#
100KR2J-1-GP

C4215
SCD1U10V2KX-4GP

DY

C4213 DY
SC10U6D3V5MX-3GP

R4215 DY
100KR2J-1-GP

+5V_ALW_PCH

Q4208
2N7002A-7-GP

+3.3V_ALW_2

1
2

C4212
SCD1U10V2KX-4GP

+5V_ALW

Q4201

+3.3V_RUN

HDD use.

C4216

37 PCH_ALW_ON

C4207
SC10U6D3V5MX-3GP

C4209

+5V_RUN

HDD use.

DY SC4700P50V2KX-1GP

1
R4221

R4210
100KR2J-1-GP

4
3

R4219
C4214
DY 20KR2J-L2-GP
SC4D7U6D3V3KX-GP

S G D

Design current: 700mA


Max current: 1000mA

D 6
D 5
S 4

PCH_ALW_ENABLE

1
R4218
DY 100KR2J-1-GP
Q4206
DMN66D0LDW-7-GP

2
0R0805-PAD-2-GP

DY

38 MODC_EN

+3.3V_ALW_PCH

1
R4230
U4205
1 D
2 D DY
3 G

+15V_ALW

D G S

MODC_EN_5V

Design current: 682mA

+3.3V_ALW

2 PCH_ALW_ON_3V#

1
2

C4211
SC4700P50V2KX-1GP

C4206
SCD1U10V2KX-4GP

SI4800BDY-T1-GP
SCD1U50V3KX-GP

DY

1
2
3
4

S G D

38,51,72,86 RUN_ON
+3.3V_ALW_2

R4216
100KR2J-1-GP

6.5A

11A

SI4800BDY-T1-GP

Q4204
DMN66D0LDW-7-GP

DY

0R1210J-GP

U4201
8
7
6
5

1
1

1
4

C4210
R4213
DY SC10U6D3V5MX-3GP 20KR2J-L2-GP

3.3V_RUN_ENABLE

C4205
SC10U6D3V5MX-3GP
R4209
100KR2J-1-GP

D
D
D
D

D
D
D
D

Q4205
DMN66D0LDW-7-GP
1

MODC_EN#

D G S

1
2
3
4

+5V_ALW

C4222
SC10U6D3V5MX-3GPDY

U4204
8
7
6
5

R4212
100KR2J-1-GP

R4207
1

+15V_ALW

R4206
100KR2J-1-GP

+3.3V_RUN

G
S
S
S

+3.3V_ALW

+5V_MOD

+5V_RUN

+3.3V_ALW_2

Design current: 4297mA


Max current: 6138.5mA

38,51,72,86 RUN_ON
+3.3V_ALW_2

C4208
SC470P50V2JN-GP

C4204

DY SC10U10V5KX-2GP

SI4800BDY-T1-GP

RUN_ENABLE

S G D

+15V_ALW

C4299
SCD1U16V2KX-3GP

6.5A

1
2
3
4

8
7
6
5

G
S
S
S

U4203
R4201
100KR2J-1-GP

1
23.3V_RUN_ON#
R4211
100KR2J-1-GP

3.3V_DELAY_EN_1

10KR2F-2-GP

D
D
D
D

+5V_RUN
D
D
D
D

+5V_ALW

Q4203
DMN66D0LDW-7-GP
1

38,51 3.3V_RUN_GFX_ON

G
S
S
S

1
2RUN_ON_5V#
R4205
100KR2J-1-GP
D G

R4232
1

+15V_ALW

G
S
S
S

+3.3V_ALW_2

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

42

of

89

SSID = PWR.Support

DC_IN CONN

NAME DIFFERENCES*
MAXIM
INTERSIL
GND
NC
REF
VREF
CCS
ICOMP
CCI
NC
CCV
VCOMP
DAC
NC
IINP
ICM
VDD
VDDSMB
BATSEL
NC
FBSA
VFB
FBSB
NC
CSIN
CSON
CSIP
CSOP
DLO
LGATE
LDO
VDDP
LX
PHASE
DHI
UGATE
BST
BOOT
VCC
VCC
means no-connect

BQ24745
ICREF
VREF
EAO
EAI
FBO
CE
VICM
VDDSMB
NC
VFB
NC
CSON
CSOP
LGATE
VDDP
PHASE
UGSTE
BOOT
ICOUT

PIN 3,4

DC_IN+

PIN 4,5

DC_IN-

PIN 1

ID

PIN 6,7,8,9

GND

DY
2

1
PD4302
BAV99-4-GP

38

+3.3V_ALW

PS_ID_1

PQ4303
FDV301N-NL-GP

1
2
PR4306
33R2J-2-GP

PSID_DISABLE#

PR4313
0R2J-2-GP

PR4305
2K2R2F-GP

2
0R2J-2-GP

PD4301
BAV99-4-GP

DY

+5V_ALW
1
PR4303

PSID_DISABLE#_R

1N-Dock 2

+5V_ALW

PU4301

DY

PR4301
10KR2J-3-GP

2
2
3
G

PL4302
BLM18BD102SN1D-GP

PD4303
SM24DTCT-GP

PS_ID_IN_1

2
1
2

PSID_DISABLE#_1
1
PQ4302
MMBT3904-7-F-GP

PR4304
100KR2J-1-GP

PR4302
15KR2J-1-GP

+5V_ALW

TI
DUMMY
0.1uF
200P 10V
1uF 10V
309K 1%
0 5%
0 5%
0.1uF
0.1uF
DUMMY
DUMMY
DUMMY
RB751V-40
DUMMY
0 5%
0 5%
8.45K 1%
4.7K 5%
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
0 5%
200K 5%
7.5K 5%
51P 10V
2000P 10V
130P 10V
0.1uF
0.1uF
DUMMY
10k 5%
DUMMY
DUMMY
0 5%
DUMMY
DUMMY
0 5%

Adapter In
*PIN
PIN
1
3
4
5
6
7
8
11
14
15
16
17
18
20
21
23
24
25
26
"NC"

TABLE
MAXIM & INTERSIL BOM DIFFERENCES
REF DES
MAXIM
INTERSIL
R411
8.45K 1%
DUMMY
C98
0.01uF
0.1uF
C459
0.1uF 10V
DUMMY
C5
1uF 10V
DUMMY
R16
365K 1%
215K 1%
R434
0 5%
10 5%
R414
0 5%
10 5%
C473
DUMMY
0.22uF
C457
DUMMY
0.22uF
C442
0.01uF
DUMMY
C453
0.1uF 10V
DUMMY
C36
220pF 50V
DUMMY
D23
RB751V-40
DUMMY
C58
3.3nF
DUMMY
R64
1 1%
0 5%
R394
100 5%
0 5%
R110
0 5%
8.45K 1%
R401
10K 5%
2.2K 5%
C441
0.01uF
0.01uF
C449
0.01uF
0.01uF
R397
1K 5%
DUMMY
Q41
ISS355
DUMMY
C16
1uF 10V
1uF 10V
R30
33 1%
33 1%
R408
DUMMY
DUMMY
R400
DUMMY
DUMMY
R403
DUMMY
DUMMY
C450
DUMMY
DUMMY
C444
DUMMY
DUMMY
C448
DUMMY
DUMMY
C446
DUMMY
DUMMY
C483
DUMMY
DUMMY
R438
10K 1%
10K 1%
R412
DUMMY
DUMMY
R440
15.8K 1%
15.8K 1%
R407
DUMMY
10K 5%
R9
0 5%
10 5%
C482
DUMMY
DUMMY
C12
DUMMY
DUMMY
R435
0 5%
10 5%

NB_PSID_TS5A63157

74 DOCK_PSID

3
2
1

B0
A
DockVCC
GND
B1
S

4
5
6

PS_ID

37

GPIO_PSID_SELECT

38

NC7SB3157P6X-1GP
1 DY
PR4307
33R2J-2-GP

DCIN1
+DC_IN_SS

PR4309
1

PC4306

4K7R3J-2-GP
2

1 PC4305

SC10U25V6KX-1GP
2

PC4304

SCD1U50V3KX-GP
2

DY

R1

Dock

AO4407A-GP

R2

Dock

8
7
6
5

SCD1U50V3KX-GP
2

PQ4301
PDTA124EU-1-GP

2nd:22.10140.341

D
D
D
D

SCD01U50V2KX-1GP
PC4301
2
1

22.10140.321
Main:22.10140.321

PU4302
S
S
S
G

PC4307
SCD1U50V3KX-GP
2
1

SKT-JACK-190-GP-U

PD4304
1SMA24AT3-G-GP

PR4310
1MR3J-L-GP
2
1

9
8

1
2
3
4

PR4308
1MR3J-L-GP
2
1

PC4303
SCD022U50V3KX-GP
2
1

PC4302

DY

MAX 8731A/ISL88731

Adapter Trip Current R416


R502
R501
R504
(W)
(A)
65
3.17
57.6K 13.0K
105
24.9K
90
4.43
51.1K 17.8K
348
33.2K
*R504 is populated if ADAPT_TRIP_SEL is used
to program for the next lower adapter.

PQ4304
1
IN

Dock

Dock

PR4312
100KR2J-1-GP
1
2

Dock

3 OUT AC_OFF_R

G
2N7002A-7-GP

2 GND

R2
PQ4305
DDTC124EUA-7F-GP

NB_AC_OFF

38,44,45

D-Change
PC4308
SCD1U50V3KX-GP

BQ247451

R1

44 NB_AC_OFF_BJT

+DC_IN

200mil

PR4311
22KR3J-L-GP
1

EL4303
BLM41PG600-GP
2

JACK_PSID

5
2

+DC_IN_L

+DC_IN_L

200mil

SCD1U50V3KX-GP

4
6

PC4309
SCD1U10V2KX-4GP

Adapter Trip Current R416


R502
R501
R504
(W)
(A)
65
3.17
57.6K 12.4K
205
24.3K
90
4.43
51.1K 16.9K
499
32.4K
*R504 is populated if ADAPT_TRIP_SEL is used
to program for the next lower adapter.

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC IN Jack
Size
C
Date:
5

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

43

of

89

SSID = PWR.Support

+PWR_SRC_VCHGR

+DOCK_PWR_BAR
+PWR_SRC

PD4402
PDS1040-13-GP-U
2

Dock

8
7
6
5

+3.3V_ALW_2

1
2

1
2
3
4

PQ4404

DY

FDS6679AZ-GP
2N7002A-7-GP

PR4437
100KR2J-1-GP

Dock
DOCK_DET#

PQ4405

38,74,75

3
2

74 ACAV_DOCK_SRC#

+3.3V_ALW

2
1
PD4403

AC_OFF_1

Dock

Dock

PR4441
22KR2J-GP
1

PQ4409
4

Dock

5
6

43 NB_AC_OFF_BJT

PR4442

1
1

2
B

PQ4413

PQ4412
E

R1
Dock

ACAV_DOCK_SRC#

Dock

Dock

PQ4414
2N7002A-7-GP
G

EN_DOCK_PWR_BAR

38

Dock

1 PR4450 2 EN_DOCK_PWR_BAR#
0R0402-PAD-2-GP

Dock
2N7002A-7-GP

R2
PDTC115EU-GP-U

PR4449
47KR2J-2-GP

2
PQ4415
2N7002A-7-GP

45 ACAV_DOCK_SRC

EN_DOCK_PWR_BAR#

D
PQ4401
2N7002A-7-GP

Dock100KR2J-1-GP

PR4447
100KR2J-1-GP
1

Dock

PR4454
33KR2J-3-GP

PR4444
PR4443
100KR2J-1-GP

PDTA115EU-GP

Dock
D

BAT54CW-1-GP

Dock1

Dock

74

Dock
2

SDMK0340L-7-F-GP

PR4448
47KR2F-GP
2
1

PR4445
240KR2J-1-GP
2

38 DOCK_AC_OFF_R

DOCK_AC_OFF

PQ4411

E
Dock PR4446
Dock240KR2J-1-GP
2

1
C

DockK

PC4424
SCD47U25V3KX-1GP
2
1

1
2

Dock

R2

PD4404
D

R1

PD4409

Dock

+3.3V_ALW_2

+PWR_SRC

FDN358P-1-GP
S

38,43,45

1
DMN66D0LDW-7-GP

+DOCK_PWR_BAR

Dock

38 PBATT_OFF

NB_AC_OFF

+PWR_SRC

PQ4410

DY PC4423

SC1U25V3KX-1-GP

Dock

SDMG0340LC7F-GP-U

DY

2N7002A-7-GP
6

+5V_ALW

PQ4408
DDTC124EUA-7F-GP

1KR6J-1-GP

PQ4407

Dock

DMN66D0LDW-7-GP

3
4

PRN4402
SRN100KJ-6-GP

+DC_IN_SS

+NBDOCK_DC_IN_SS

2 GND

PR4440
22KR2J-GP
2
1

R1

R2

Dock

45

PR4439
47KR2J-2-GP

SW_GND

Dock

2
S

PQ4406
PDTA124EU-1-GP

R2

R1

1
IN

38 PBATT_OFF

3 OUT

PR4438
100KR2J-1-GP
1

AO4407A-GP

PR4435
1

PU4405

AO4407A-GP

Dock

2
DY10KR5F-2-GP

PC4422
SCD1U25V2ZY-1GP

PU4401
S 1
S 2
S 3
G 4

D
D
D
D

8
7
6
5

PR4436
240KR2J-1-GP
2
1

8
7
6
5

D
D
D
D

PC4421
SC2200P50V2KX-2GP

3
PU4404
S
S
S
G

1
2
3
4

+VCHGR

DY
PR4451

ACAV_DOCK_SRC

45

Dock

0R2J-2-GP
PD61

1'nd 83.R2004.C81
2'nd 83.00040.M81

PR4452
22KR2J-GP

SSID = RBATT
+3.3V_ALW
PD4401
2

Batt Connecter

PBAT_SMBDAT

3
1
BAV99-4-GP

BATT1

PD4406

2
10
1

PBAT_SMBCLK

+VCHGR

PRN4401

2
3
4
5
6
7
8
9
11

PBAT_SMBCLK1
PBAT_SMBDAT1

1
2

1
4
3

PBAT_SMBCLK
PBAT_SMBDAT

PBAT_PRES1#

37
37

BAV99-4-GP

SRN100J-3-GP
PBAT_ALARM#

PD4407
PR4453 1

2 100R2J-2-GP

PR4401
1

2 10KR2J-3-GP

PBAT_PRES#
+3.3V_ALW

38
PBAT_PRES#

SYN-CON9-19-GP

20.81329.009
1

BAV99-4-GP
PC4401
SCD1U50V3KX-GP

PC4425
SC2200P50V2KX-2GP
PD4408
2
PBAT_ALARM#

DY
1
BAV99-4-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DOCK DCIN/BATT Connector


Size
C
Date:
5

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

44

of

89

SSID = Charger

1
PR4544
100KR2J-1-GP
2

PC4523
SCD1U25V2ZY-1GP

PC4530
SC2D2U25V5KX-1GP

PC4529
SCD1U50V3KX-GP
2
1

PC4547
SC2D2U25V5KX-1GP
A
K

PC4546
SCD1U50V3KX-GP
2
1

PC4545
SC10U25V6KX-1GP
2
1

PC4544
SC10U25V6KX-1GP
2
1

PC4543
SC10U25V6KX-1GP
2
1

1
2

PC4528
SC10U25V6KX-1GP
2
1

5
6
7
8
D
D
D
D
G
S
S
S

PU4506
SI4800BDY-T1-GP

G
S
S
S
4
3
2
1

PC4533
SC2200P50V2KX-2GP
2
1

1
PC4542
SC10U25V6KX-1GP
2
1
2

PD4504
1SMA18AT3G-GP

MAX8731A_CSIN

CHG_AGND

DY

PR4572
1K8R6J-GP

DY
1 PR4571 2
0R0603-PAD-2-GP

DY

PR4564
0R0402-PAD-2-GP

MAX8731A_CSIP

1 PR4569 2
0R0402-PAD-2-GP

PR4559
4D7R6J-GP

+VCHGR_R

15

PR4570
1K8R6J-GP

GND

+VCHGR
VFB

2
PR4565
0R0402-PAD-2-GP

NC#16

DY

PC4557
SC1U6D3V2KX-GP

PU4504

CHG_AGND
16

29

PC4558
2
1

DY

PC4555
PC4556
SCD01U50V2KX-1GP SCD01U50V2KX-1GP

SCD1U10V2KX-4GP

DY

DY
2

DY

PC4553
SC56P50V2JN-2GP

FBO
EAI
EAO
VREF
CE
GND

PC4541
SC1000P50V3JN-GP-U

+VCHGR

DY
2

17

DY

charger current
1.4~6.3A

18

G
S
S
S

CSON
VICM

1
PC4551
SCD1U50V3KX-GP

19

4
3
2
1

PGND
CSOP

6
MAX8731A_CCI
5
MAX8731A_CCS
PR4567
4
7K5R2F-1-GP
MAX8731A_REF
3
1
1 PR4568 2 MAX8731A_DAC
7
0R0402-PAD-2-GP
12
1

PC4549
2 SC2200P50V2KX-2GP
2
1 2
PC4550
SC150P50V2JN-3GP1
2

NC#14

PR4562
200KR2F-L-GP
1
2

PC4554
SCD1U50V3KX-GP

14
CHG_AGND

DY

MAX8731A_IINP
MAX8731A_CCV

1MAX8731A_CCV1
2
1
PR4563
4K7R2J-2-GP

PC4552
SC220P50V2JN-3GP
2
1

PR4566
8K45R2F-2-GP
1

1 PR4560 2
0R0402-PAD-2-GP

4
3
2
1

D
D
D
D

5
6
7
8

PC4527
SC1U6D3V2KX-GP

SC220P50V2JN-3GP

PU4505
SI4800BDY-T1-GP

1
PR4543
100KR2J-1-GP
2

PC4548
SCD1U50V3KX-GP
1
2

PR4561
100KR2J-1-GP
2
1

39 SYS_IMON

DY

+3.3V_ALW

+VCHGR1
PL4501
IND-5D6UH-42-GP
1
2
1
2
PR4558
D01R2512F-3-GP

PC4539
SC3300P50V3KX-1GP
MAX8731A_LX1

D
D
D
D

DY

DY

CHAGER_SRC

PC4559
SCD1U50V3KX-GP

1
PC4540

20

1
2
PC4537
SCD1U50V3KX-GP

GAP-CLOSE-PWR

PG4530
GAP-CLOSE-PWR-3-GP
2
2
1

LGATE

1
2

PR4557
0R3J-0-U-GP
1
2

23

44

PG4529
GAP-CLOSE-PWR-3-GP
2
1

SDA

GAP-CLOSE-PWR-3-GP

DY

CHG_AGND
1
2
PC4536
SCD1U50V3KX-GP

24

SW_GND

UGATE
SCL

PC4522
SC2200P50V2KX-2GP

2
1

DY

ACOK

PHASE
9

25
21

CHG_AGND

PR4554
PD4503
SD103AWS-1-GP
0R3J-0-U-GP
1
2MAX8731A_BST1 K
A
MAX8731A_LDO

74
GAP-CLOSE-PWR
PG4524
1
2

DY

CHAGER_SRC

GAP-CLOSE-PWR-3-GP
PG4528
1
2
37 CHARGER_SMBDAT

BOOT
VDDP

27
26

MAX8731A_CSSP 1
2
PC4532
SCD1U50V3KX-GP
MAX8731A_CSSN

DY

GAP-CLOSE-PWR
PG4526
1
2

1 2

10

2
1

CSSN
ICOUT

VDDSMB

DOCK_DCIN_IS+

Dock

PU4507
SI4812BDY-T1-E3-GP

13

1
2

ACIN

28

4 D2

PC4521
SCD1U50V3KX-GP

DY
CSSP

GAP-CLOSE-PWR
PG4522
1
2

74

GAP-CLOSE-PWR
PG4523
1
2

5
6
7
8

MAX8731A_ACOK
1 PR4555 2
0R0402-PAD-2-GP
PG4527
1
2

5 S1

Dock

PG4520
2

GAP-CLOSE-PWR
PG4525
1
2

Dock

11

DCIN

DOCK_DCIN_IS-

1
2
PR4546
100KR2J-1-GP

PR4549
33R3J-2-GP
1

Dock
PC4531
SCD1U50V3KX-GP

22

PR4542
0R0402-PAD-2-GP

PR4541
0R2J-2-GP

PR4552
0R0402-PAD-2-GP

1
MAX8731A_DCIN
MAX8731A_ACIN

6 D1

PQ4505
SI3993DV-T1-GP

1
2
PC4525
SCD1U50V3KX-GP

CHG_AGND

37 CHARGER_SMBCLK

CHG_AGND

PC4538
SCD1U10V2KX-4GP
2
1

PR4556
15K8R3F-GP
2
1

DY

DY

BQ24745RHDR-GP

DY

2N7002A-7-GP

PQ4504
SI3993DV-T1-GP

ICREF

PC4526
2
1
2

DY

PQ4501

38,43,44

S2 2

PR4551
2 10KR2F-2-GP
1

PR4550
10KR2F-2-GP
2
1

SCD01U50V2KX-1GP
2
1

49K9R2F-L-GP
2

0R2J-2-GP
BAT54CW-1-GP
MAX8731A_REF
+3.3V_ALW
MAX8731A_LDO
PC4535

37,39 ACAV_IN

CHG_AGND

PR4548

+NBDOCK_DC_IN_SS
2
PD4502

PR4553

NB_AC_OFF
SCD1U50V3KX-GP

2N7002A-7-GP

2N7002A-7-GP

1
S
2

need 20mil

PR4547
300KR3F-GP
2
1

PR4545
200KR2F-L-GP
1

2N7002A-7-GP
G

G1 1

G2 3
SCD1U50V3KX-GP

Dock

PC4524

G
PQ4508

+DC_IN_SS

PR4538
PR4536
10KR2J-3-GP
33KR2J-3-GP
D 2
1 1
2

PR4537
160KR2F-GP
1
2
D
PQ4506

PQ4507

PR4540
33KR2J-3-GP
2
1

leakage A

2
2
1
PR4539
PR4535
10KR2F-2-GP 100KR2J-1-GP
1

+SDC_IN

CHAGER_SRC

PG4521
GAP-CLOSE-PWR-3-GP

G1

+DC_IN

S2

AO4407A-GP

+PWR_SRC

1
2
PR4501
D01R2512F-4-GP
PG4501
1
2
GAP-CLOSE-PWR-3-GP

D1

1
2
3
4

G2

S
S
S
G

PC4534
SC10U25V6KX-1GP
2
1

+SDC_IN

44 ACAV_DOCK_SRC

PU4501
D
D
D
D

S1

8
7
6
5

D2

+DC_IN_SS

CHG_AGND

CHG_AGND

PQ4509
ACAV_IN

2N7002A-7-GP

+5V_ALW

PU4508A

1 PR4577 2
0R0402-PAD-2-GP

ACAV_IN_NB

37,38

LM393ADR-1-GP

8
+

PR4576
100KR2J-1-GP
1

59KR2F-GP
PR4579
42K2R2F-L-GP

PC4501
SC100P50V2JN-3GP
2
1

2
PR4578
20KR2F-L-GP

PC4560
SCD1U50V3KX-GP
2
1

1MR2F-GP
+5V_ALW

+3.3V_ALW

PR4573
1

PR4575
1

PR4574
1

+3.3V_ALW

232KR2F-GP

+DC_IN_SS

DY
S

This Resistor
must be 1%
tolerance.

PD4501
A

PU4508B

7
LM393ADR-1-GP

leakage A

SDMK0340L-7-F-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Battery Charger
Size
C
Date:
5

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

45

of

89

SSID = PWR.Plane.Regulator_5v3p3v

51125_VCLK

3
51125_ENTIP1

GAP-CLOSE-PWR

2
3

1
2
1

PC4624
SC1U25V3KX-1-GP

PC4625
SCD1U25V3KX-GP

PD4604
BZT52C15S-GP

PQ4603
2N7002A-7-GP

DY

1
PC4627
SC18P50V2JN-1-GP

+5V_PWR

PG4624
GAP-CLOSE-PWR-3-GP

1
51125_ENTIP2

PR4657
200KR2J-L1-GP

DY

GAP-CLOSE-PWR
PG4625
1
2

+15V_ALW

2
0R0402-PAD-2-GP

PQ4601
2N7002A-7-GP

100KR2F-L1-GP

39 THERM_STP#

1
PR4637

DY

GAP-CLOSE-PWR
PG4623
1
2

PC4623
PQ4602 SC18P50V2JN-1-GP
2N7002A-7-GP

PR4638

2
10KR2J-3-GP

1
PR4656

37 ALW_ON

GAP-CLOSE-PWR
PG4622
1
2

PD4601
BAT54S-7F-GP

PC4626
SCD1U25V3KX-GP

GAP-CLOSE-PWR
PG4621
1
2

PD4602
BAT54-7-F-GP

DY
4

PD4603
BAT54S-7F-GP

PR4636
147KR2F-GP

PG4620
2

1
2

2
G

+PWR_SRC_5V/3V

PC4621
SCD1U25V3KX-GP

51125_ENTRIP

PC4601
SCD1U25V3KX-GP

PR4635
100KR2J-1-GP

+PWR_SRC

PC4622
SC1KP50V2KX-1GP

+3.3V_ALW_2

+PWR_SRC
+PWR_SRC_5V/3V
+PWR_SRC_5V/3V

PC4630 PC4631

51125_VREF

ALW_PWRGD_3V_5V

DY

PR4655
1
0R2J-2-GP

PC4640
SC560P50V-GP

25

PC4644

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L


Inductor: 3.3UH FDV0630-3R3M=P3 TOKO 31mohm Isat =6.9Arms 68.3R31A.10E
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37

1
2

GAP-CLOSE-PWR

1
PR4647
32K4R2F-1-GP

51125_FB1_R

DY

PR4649
100KR2J-1-GP

PR4651
21K5R2F-GP

Close to VFB Pin (pin2)

ALW_PWRGD_3V_5V

PC4645

GAP-CLOSE-PWR
PG4639
1
2

+3.3V_ALW

+5V_ALW_2

GAP-CLOSE-PWR
PG4637
1
2

PC4642
SC18P50V2JN-1-GP

DY

GAP-CLOSE-PWR
PG4634
1
2

PTC4604

-1.10/0322

DY
1 2

VREG5

VREG3

GAP-CLOSE-PWR-3-GP

18

PR4646
0R2J-2-GP

51125_VCLK

PTC4603

DY

PC4639

PG4635

PR4642
2D2R5F-2-GP

37

PR4654
1
0R2J-2-GP

15

PC4646

DY

51125_ENTIP1

SC22U6D3V5MX-2GP

SC10U6D3V3MX-GP

VCLK

17

2
1

SKIPSEL

SC4D7U6D3V5KX-3GP

51125_VREF
+3.3V_ALW_2

Close to VFB Pin (pin5)

GND

PG4641

PR4652
1
0R0402-PAD-2-GP
PR4653
1
0R0402-PAD-2-GP

TONSEL

74.51125.073

PR4650

+5V_ALW_2

GND

TPS51125RGER-GP

1
DY0R2J-2-GP

ENTRIP1

VREF

3D3V_AUX_S5_5_51125 8

14
51125_SKIPSEL

+3.3V_ALW_2

+3.3V_ALW_2

ENTRIP2

DY

PGOOD

1
2

51125_TONSEL

EN0

51125_FB1

23

PU4607

VFB1

VFB2

51125_FB2_R
PC4643
DYSC18P50V2JN-1-GP

51125_VO1

GAP-CLOSE-PWR
PG4633
1
2

2 51125_EN 13
820KR2F-GP
51125_ENTIP2 6

24

VO1

PR4645
0R2J-2-GP

PR4648
10KR2F-2-GP

IND-1D5UH-45-GP

5
6
7
8
51125_FB2

VO2

1
2
3
4

S
S
S
G

4
3
2
1

51125_DRVL1

4
3
2
1

1
2
3
4

51125_LL1

19

GAP-CLOSE-PWR
PG4630
1
2

+5V_PWR
PL4601

8
7
6
5
D
D
D
D

DY

5
6
7
8

VIN

16

8
7
6
5

D
D
D
D
S
S
S
G

1
2

SCD1U50V3KX-GP

20

1
2
0R3J-0-U-GP PR4640

51125_VO2

DY

DRVL1

51125_DRVH1

ST100U6D3VBM-7GP

1
PR4643

PC4641

LL1

DRVL2

51125_VBST1

21

ST220U6D3VDM-15GP

PU4606
FDS6676AS-GP

1 2

LL2

22

GAP-CLOSE-PWR
PG4628
1
2

Design Current = 8A
12.54A<OCP< 14.82A

SCD1U10V2KX-4GP

12

DRVH1

PG4626
2

GAP-CLOSE-PWR
PG4627
1
2

GAP-CLOSE-PWR-3-GP

11

VBST1

DRVH2

+5V_ALW

SCD1U50V3KX-GP

51125_LL2
51125_DRVL2

VBST2

SC10U25V6KX-1GP

9
10

SC10U25V6KX-1GP

51125_VBST2
1
2
0R3J-0-U-GP PR4639
51125_DRVH2

SCD22U10V2KX-1GP

GAP-CLOSE-PWR

SCD1U25V3KX-GP
PC4636
1
2

FDS6690AS-GP
S
S
S
G

DY

PC4638
SC330P50V3KX-GP

D
D
D
D

GAP-CLOSE-PWR-3-GP

GAP-CLOSE-PWR
PG4644
2
1

PR4641
DY
2D2R5F-2-GP

PG4632

PR4644
6K65R2F-GP

GAP-CLOSE-PWR
PG4642
2
1

PC4635
2
1

IND-1UH-98-GP

PU4603
FDS8884-GP

S
S
S
G

1
ST100U6D3VBM-7GP
PTC4605

PU4601

SCD1U25V3KX-GP

GAP-CLOSE-PWR
PG4640
2
1
GAP-CLOSE-PWR
PG4643
2
1

PU4602
FDS8880-NL-GP

+5V_PWR

PC4632 PC4633 PC4634

D
D
D
D

ST220U6D3VDM-15GP
PTC4601

GAP-CLOSE-PWR
PG4638
2
1

PC4637

GAP-CLOSE-PWR
PG4636
2
1

PL8602

DY

SCD1U10V2KX-4GP

GAP-CLOSE-PWR
PG4631
2
1

DY

SCD01U50V2KX-1GP

Design Current = 10.2A


16<OCP<18.9A
+3.3V_ALW
+3D3V_PWR
PG4629
2
1
+3D3V_PWR
GAP-CLOSE-PWR
PG4601
2
1

PC4629
SC10U25V6KX-1GP

SC10U25V6KX-1GP

PC4628

+3.3V_ALW_2

+3.3V_RTC_LDO

1 PR4601 2
0R0402-PAD-2-GP

SKIPSEL

VREG3 or VREG5

VREF(2V)

Operating
Mode

OOA Auto Skip

Auto Skip

I/P cap: 10U 25V K1206 X5R/ 78.10622.52L


Inductor: 2.2UH FDVE0630-2R2M=P3 TOKO 21mohm Isat =8.7Arms 68.2R21B.10A
O/P cap: 220U 6.3V PSLV0J227M(25) 25mOhm 2.236Arms NEC_TOKIN/77.C2271.00L
H/S: FDSS8884 SO-8/ 23mohm/30mOhm@4.5Vgs/ 84.08884.037
L/S: FDS6690AS SO-8/ 12mohm/15mOhm@4.5Vgs/ 84.06690.E37

GND
PWM only

TONSEL

CH1

CH2

GND

200kHz

265kHz

VREF

245kHz

305kHz

VREG3

300kHz

375kHz

VREG5

365kHz

460kHz

EN0
Operating
Mode

Open

820k to GND

enable both
LDOs, VCLK on
and ready to
turn on
switcher
channels

enable both LDOs,


VCLK off and
ready to turn on
switcher channels

GND

<Core Design>

Wistron Corporation

disable all
circuit

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

DCDC 5V/3D3V (TPS51125)

Size
Document Number
Custom
Date:
A

Rev

-1

Fonseca 14.1" DIS

Monday, March 22, 2010

Sheet
E

46

of

89

62883_VCCP

24

62883_PWM3

23

LGATE1

ISEN3

1
PR4780
1
PR4739
1
PR4708
1
PR4760
1
PR4707

2
2

VSUM+
VSUMISEN1
ISEN2

1
2

ST330U2VDM-4-GP

1
2

SE220U2VDM-12GP

1
2
+VCC_CORE_PHASE1

1
2

10KR2F-2-GP
2
3K65R3F-GP
2

1
2

ST330U2VDM-4-GP

2
1

PTC4708

PTC4701

ST330U2VDM-4-GP

ST330U2VDM-4-GP

1
2

1
2
PHASE3_R

PR4740
2D2R5J-1-GP

1SNUBBER_3
2
2

1
PR4763
1
PR4764
1
PR4747
1
PR4719
1
PR4765

PC4739
SC330P50V2KX-3GP

5
6
7
8
4
3
2
1

1
2

1
2

1
2

1
2

1
2

ISEN3

PG4714

DY

LGATE3

GAP-CLOSE-PWR-3-GP

PR4777

DY

PG4701

PR4703

DY

L-D36UH-1-GP

GAP-CLOSE-PWR-3-GP

1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

DY

SIR460DP-T1-GE3-GP
D
S
D
S
D
S
D
G

PR4710 PR4706

1KR2J-1-GP

PR4743 PR4727
1KR2J-1-GP

DY

1KR2J-1-GP

PR4768
1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

PU4708

DY

+VCC_CORE

PL4701

PHASE3

DY

PC4733

+VCC_CORE_PHASE3

UGATE3

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
PM_DPRSLPVR
PSI#
PR4715 PR4702

PC4732

4
3
2
1

PC4735

1
5
6
7
8

PC4731
SCD1U25V3KX-GP

PC4701

DY

1
2

1
2

PR4753

649R2F-GP

SCD1U50V3KX-GP

PHASE1_R

10KR2F-2-GP

SC10U25V6KX-1GP

10KR2F-2-GP
2

SC10U25V6KX-1GP

1R2F-GP
2

SC10U25V6KX-1GP

3K65R3F-GP
2

SI7686DP-T1-GP
D
S
D
S
D
S
D
G

PR4724

1KR2J-1-GP

DY

1KR2J-1-GP

PR4705 PR4769
1KR2J-1-GP

DY

1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

1KR2J-1-GP

DY

10KR2F-2-GP
2

NTC 10K close to Choke of Phase1

PU4701

PR4732 PR4713

PHASE2_R

VSUM-

1 PR4741 2
0R0402-PAD-2-GP
PR4709

1SNUBBER_1
2

PC4712
SC330P50V2KX-3GP

PR4728
2D2R5J-1-GP

1
2

ISEN1
PR4721
NTC-10K-26-GP

1SNUBBER_2
2

4
3
2
1
VSUM-

+VCC_CORE_PHASE2

9
3

ISEN2
VSUM+

ISL6208CRZ-TGP-U

DY

PHASE3
UGATE3
LGATE3

PC4726
SC330P50V2KX-3GP

7
8
4

+1.05V_VTT

2
5
6
7
8
4
3
2
1
5
6
7
8

1
BOOT

VCC

6208_FCCM

6208_PWM

LGATE2

PHASE
UGATE
LGATE
GND
GND

1
1

1VSUM_RR
2

FCCM

6208_PHASE3

PTC4706

+PWR_SRC

1
2

Intel support POC (Power On Configuration).

2
1
2

1
2
2
1

VSUM_RC
2
2

SCD22U25V3KX-GP
PC4709

UGATE1
20

BOOT1
19

IMON

2P

1
2
1

1
2

PWM

2D2R3J-2-GP
PC4723
SCD22U25V3KX-GP

DY

PG4713

PU4706

L-D36UH-1-GP
GAP-CLOSE-PWR-3-GP

+VCC_CORE

PG4712

PU4707

VSUM+

PR4750
2K61R2F-1-GP

PC4718

Design Current = 48A

GAP-CLOSE-PWR-3-GP

PC4734
1
2
SC1U10V2KX-1GP
PR4734
BOOT3
1
2

PC4717

PL4703

SIR460DP-T1-GE3-GP
D
S
D
S
D
S
D
G

12

PR4736

PC4742
SCD01U25V2KX-3GP

PC4716

PHASE2

1 PR4731 2
0R0402-PAD-2-GP

11KR2F-L-GP

PU4704

+5V_ALW

PC4730
SCD22U10V2KX-1GP

PC4741

PC4715

UGATE2

12,39

VSS_SENSE_R

SCD01U16V2KX-3GP

PC4727
SC1KP50V2KX-1GP

10KR2F-2-GP

PR4748

10KR2F-2-GP
2

PC4728

PR4723
0R0402-PAD-2-GP

1210 SB
SCD33U16V3KX-1GP

PC4711
SC330P50V2KX-3GP

1R2F-GP
2

2
2

PC4708

+1.05V_VTT

PR4776

PC4714
C4714

3K65R3F-GP
2

+PWR_SRC

PHASE1

PC4729
SCD22U25V3KX-GP

10KR2F-2-GP
2

PR4751
0R0603-PAD-2-GP

22
21

1
25

1 PR4754 2
+PWR_SRC
0R0402-PAD-2-GP
1
2
+5V_ALW
PR4759
1
1R2F-GP
2

PR4775
2D2R5J-1-GP

5
6
7
8
4
3
2
1
LGATE2

PR4786
DY 100KR2F-L1-GP
UGATE1 PR4722
BOOT1 1
2BOOT1_PHASE1
2D2R3J-2-GP
CPU_IMON
CPU_IMON

PR4725
82D5R2F-1-GP

12 VCC_SENSE

26

6K65R2F-GP

SC1U10V2KX-1GP

2KR2F-3-GP

PC4722

SC390P50V2KX-GP
2

PC4721
SC330P50V2KX-3GP

18

VIN

VDD

17

62883_VDD

16

ISUM+

ISUM-

RTN

SCD22U10V2KX-1GP

15

11

ISEN1

62883_ISUM- 14

VSEN

GND

ISEN1

PHASE1

ISL62883CHRTZ-T-GP

PR4712

12 VSS_SENSE

4K02R2F-GP

VSSP1

ISEN2

ISEN3

62883_VID0
31

ISEN3/FB2

10
41

VID0

62883_VID1
32
VID1

62883_VID2
33

LGATE1

PC4713
262883_FB_VSEN1
2

1210 SB

VID2

62883_VID3
34
VID3

62883_VID4
35
VID4

PWM3/LGATE1#

FB

PC4707

PC4736

1
PR4714
562R2F-GP

VCCP

COMP

VSUM-

PR4737 PR4701

5
6
7
8
4
3
2
1

H_VID0

H_VID1

H_VID2

H_VID3

H_VID4

H_VID5

H_VID6

62883_VID5
36
VID5

62883_VID6

2 PR4773 1
0R0402-PAD-2-GP
2 PR4718 1
0R0402-PAD-2-GP
2 PR4755 1
0R0402-PAD-2-GP
2 PR4746 1
0R0402-PAD-2-GP
2 PR4730 1
0R0402-PAD-2-GP
2 PR4762 1
0R0402-PAD-2-GP
2 PR4729 1
0R0402-PAD-2-GP
2 PR4766 1
0R0402-PAD-2-GP
62883_VR_ON

37

VR_ON

VID6

2 PR4735 1
0R0402-PAD-2-GP
62883_DPRSLPVR 2 PR4749 1
0R0402-PAD-2-GP

38

CLK_EN#

DPRSLPVR

39

62883_CLK_EN#

40

1
7

13

74.62883.B73

VW

12

1
2

LGATE2

PC4710
SCD22U25V3KX-GP

27

NTC

PHASE2

VSSP2

28

ISEN2

PR4770
1
DY

PTC4705

SCD1U50V3KX-GP

X01.09/1020

VR_TT#

2D2R3J-2-GP

SE100U25VM-11GP

SE100U25VM-11GP

PHASE2

UGATE2

RBIAS

29

1
PR4756
1
PR4767
1
PR4742
1
PR4716
1
PR4738

PG4706

1
262883_COMP_R
1
2
PC4740
PR4752
SC150P50V2JN-3GP
324KR2F-GP

UGATE2

VSUM-

GAP-CLOSE-PWR-3-GP

DY

1
2
PC4725
SC22P50V2JN-4GP

SCD1U50V3KX-GP

0R2J-2-GP
ISEN3

SC10U25V6KX-1GP

1
2
PC4738
SC33P50V2JN-3GP

PSI#

2B00T2_R

PTC4704

SC10U25V6KX-1GP

BOOT2

PR4772
1

L-D36UH-1-GP

SC10U25V6KX-1GP

DY

VSUM+
BOOT2

SC10U25V6KX-1GP

DY

SI7686DP-T1-GP
D
S
D
S
D
S
D
G

PR4744

ISEN2

PC4706
SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

PC4719
SC1KP50V2KX-1GP

PGOOD

ISEN1
+5V_ALW

30

SC1U10V2KX-1GP

ISEN3

DY

LGATE1

SC1U10V2KX-1GP

1 PR4704 2 62883_PGOOD
38,39 IMVP_PWRGD
0R0402-PAD-2-GP
1 PR4733 2 62883_PSI#
12
PSI#
0R0402-PAD-2-GP
1
2 62883_RBIAS
PR4781
147KR2F-GP
470K close to H/S MOSFET of Phase1
1
DY 2H_PROCHOT#_R
9 H_PROCHOT#
PR4771
PR4758
6266A_NTC_R
62883_NTC
NTC-470K-1-GP
4K02R2F-GP
1
2
1
2
DY
DY
PR4774
62883_VW
4K02R2F-GP
1 DY2
SCD01U25V2KX-3GP
62883_COMP
PC4737
1
2
PR4726
62883_FB
8K06R2F-GP

PU4703

PG4708

PU4705
PR4720
1K91R2F-1-GP

+VCC_CORE

GAP-CLOSE-PWR-3-GP

+3.3V_RUN

PC4705

PL4702

PHASE1

SIR460DP-T1-GE3-GP
D
S
D
S
D
S
D
G

PR4745
1K91R2F-1-GP

PC4704

UGATE1

NTC

PC4703
SC10U25V6KX-1GP

+3.3V_RUN

PU4702

SC10U25V6KX-1GP

PTC4703

DY

12

SI7686DP-T1-GP
D
S
D
S
D
S
D
G

H_VID[6..0]
PTC4702

PC4702

38

SSID = CPU.Regulator

12

IMVP_VR_ON

PM_DPRSLPVR
7 VR_CLKEN#

+PWR_SRC

+PWR_SRC

-1.10/0305

1R2F-GP
2
10KR2F-2-GP
2
10KR2F-2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

ISL62883_CPU_CORE_1

Document Number

Sheet
1

47

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Reserve

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

48

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

DC to DC 1.05V

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

49

of

89

SSID = PWR.Plane.Regulator_1p5v0p75v

13
12
11
0D75V_EN 10

23

DY

DH

+1.5V_SUS_P

VTTEN

LX

20 TPS51116_PHS
+PWR_SRC

VTTIN
DL

19 TPS51116_LGT

NC#7
PGND2

PGND1
PGND1

TON

VDDQS
VTT

FB

18
17
8

TPS51116_VDDQSNS

51116_VDDQSET
+5V_ALW

GAP-CLOSE-PWR
PG5008
1
2
GAP-CLOSE-PWR
PG5010
1
2

PU5002
SI7686DP-T1-GP

GAP-CLOSE-PWR
PG5001
1
2

GAP-CLOSE-PWR

GAP-CLOSE-PWR
PG5012
1
2
GAP-CLOSE-PWR
PG5013
1
2

Design Current = 13A


20.4 <OCP< 24.1A

GAP-CLOSE-PWR
PG5014
1
2
+1.5V_SUS_P

TPS51116_UGT

VTT
On

Lo

Hi

On

On

Off(Hi-Z)

Lo

Lo

Off

Off

Off

TPS51116_LGT

TPS51116_VDDQSNS
PR5014
30K1R2F-L-GP

VDDQ (V)

VTTREF and VTT

NOTE

GND

2.5

VVDDQSNS/2

DDR

V5IN

1.8

VVDDQSNS/2

DDR2

FB Resistors

Adjustable

VVDDQSNS/2

1.5 V < VVDDQ < 3 V

1
2

PTC5002

PTC5001

1
2

1
2

1
2

PC5019
SCD1U10V2KX-4GP

GAP-CLOSE-PWR

DY
2

PC5021
SC18P50V2JN-1-GP

PR5015
29K4R2F-GP
I/P cap: 10U 25V K1206 X5R/ 78.10622.52L
Close to
VFB=18Arms
Pin (pin5)
Inductor: 1.5UHPCMC063T-1R5MN Cyntec DCR:14~15mohm
Isat
68.1R510.10K
O/P cap: 330U 2.5V PSLV0E337M(15) 15mOhm 2.886Arms NEC_TOKIN/ 77.C3371.10L
H/S: FDS8880 SO-8/9.6mohm/ 12mOhm@4.5Vgs/ 84.08880.037
L/S: FDS8672S SO-8/ 5.3mOhm/7.0mohm@4.5Vgs/ 84.08672.A37
Switching freq-->400KHz

VDDQSET

GAP-CLOSE-PWR
PG5018
1
2

51116_VDDQSET

PC5018
SC4D7U6D3V5KX-3GP

2
1
PC5020
SC330P50V3KX-GP

ST220U2D5VDM-13GP

On

ST220U2D5VDM-13GP

VTTREF

On

GAP-CLOSE-PWR
PG5020
1
2

VDDR

DY

S3
S4/S5

S5
Hi

SIR460DP-T1-GE3-GP

Hi

PR5013
2D2R5F-2-GP

TPS51116_PHS_SET
S
S
S
G

S3

S0

DY

5
6
7
8

GAP-CLOSE-PWR
PU5003

State

GAP-CLOSE-PWR
PG5019
1
2

IND-1UH-80-GP

PC5017
SCD1U25V3KX-GP

GAP-CLOSE-PWR
PG5016
1
2

TPS51116_PHS

PG5017
GAP-CLOSE-PWR-3-GP

TPS51116_VBST 1

PL5001

+0.75V_DDR_VTT
PG5015
2

4
3
2
1

1
2

PC5016
SC10U6D3V5MX-3GP

1
2

PC5015
SC10U6D3V5MX-3GP

1
2

+0D75V_DDR_P

D
D
D
D

PC5014
SC10U6D3V5MX-3GP

1
2

PC5013
SCD1U10V2KX-4GP

4
3
2
1

S
S
S
G

+0D75V_DDR_P

PC5008
SCD033U16V3KX-GP

1 PR5012 2
0R0603-PAD-2-GP

GAP-CLOSE-PWR
PG5011
2
1
PC5012
SC4D7U25V5KX-GP

0R2J-2-GP

DY PC5007
SC1U10V3KX-3GP

GAP-CLOSE-PWR
PG5006
1
2

GAP-CLOSE-PWR
PG5009
2
1

+5116_PWR_SRC

D
D
D
D

+V_DDR_MCH_REF

DY

PC5011
SCD1U50V3KX-GP

REF
5

VSSA

25

+0D75V_DDR_P

VCCA

+1.5V_SUS
PG5002
2

GAP-CLOSE-PWR
PG5004
1
2

GAP-CLOSE-PWR
PG5007
2
1

PR5011

VTTS
GND

+5116_PWR_SRC
PG5003
2
1

GAP-CLOSE-PWR
PG5005
2
1

24

PC5005
SCD1U10V2KX-4GP

1
2

2 0R2J-2-GP

2 TPS51116_VBST

DY

DY

TPS51116RGER-GP-U
1

PC5006
SC1KP50V2KX-1GP

PR5005 1

EN/PSV

2 1M1R2J-GP

PC5004
SC1U10V3KX-3GP

NC#12

DY

1 PR5010 2
0R0402-PAD-2-GP

DY

22,38,72 SIO_SLP_S4#

0D75V_EN

21 TPS51116_UGT

+5V_ALW
PR5009 1

PC5001
SC1U10V3KX-3GP

9,22,35,38 SIO_SLP_S3#

2 0R2J-2-GP

0R3J-0-U-GP

+1.5V_SUS_P

2 0R0402-PAD-2-GP

PR5004 1

PC5010
SC10U25V6KX-1GP

RT: Non_ASM
TI: ASM

22 TPS51116_VBST1

37,42 DDR_ON

PR5003 1

PR5008

BST

PGD

DY

2 620KR2F-GP

38 0.75V_DDR_VTT_ON

PU5001

PC5009
SC10U25V6KX-1GP

PR5007 1

DY

PD5001
SDMK0340L-7-F-GP

5
6
7
8

37 1.5V_SUS_PWRGD

VDDP

ILIM

16

PR5006
20KR2F-L-GP

+5V_ALW

SC1KP50V2KX-1GP

15

+3.3V_ALW

PR5002
2 51116_VDD
10KR2F-2-GP
PC5002
1
2

14

+5V_ALW

PR5001
5D1R3J-GP

VDDP

SC1U10V3KX-3GP
PC5003
2
1

+5V_ALW

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

DC to DC 1.5V / 0.75V

Size
Document Number
Custom
Date:
5

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

50

of

89

+3.3V_SUS

SSID = PWR.Plane.Regulator_1p8v

PR5101
100KR2J-1-GP

LDO for +1.8V_RUN


1.8V_RUN_PW RGD

38 1.8V_RUN_PW RGD
D

+3.3V_SUS

+1.8V_LDOIN

VOUT = 0.8 *(1+Rtop/Rbot)

PG5102
1
2
GAP-CLOSE-PW R

+1.8V_RUN
Design current = 1.1A

PG5103
2

5
4
3
2
1
POK
NC#4
NC#3
GND
NC#1

GAP-CLOSE-PW R
PR5103
0R3J-0-U-GP
1
DY 2

21
20
19
18
17
16

GND
NC#20
ADJ
VOUT
VOUT
VOUT

+1D8V_RUN_P

+1.8V_RUN

GAP-CLOSE-PW R

DY
2

PG5108
2

SC22U6D3V5MX-2GP

2
1

1KR2F-3-GP

PC5106

+3.3V_SUS

PR5108
100KR2J-1-GP

LDO for +1.8V_DELAY

VOUT = 0.8 *(1+Rtop/Rbot)

6
7
8
9
10

21
20
19
18
17
16

+1D8V_DELAY_P

+1.8V_DELAY

1
2

1
2

2
1KR2F-3-GP

GAP-CLOSE-PW R

PC5112

PR5110
0R0603-PAD-2-GP

PR5111

DY

SC22U6D3V5MX-2GP

+5V_ALW

DY

PG5105
2

GAP-CLOSE-PW R
PG5107
1
2

1
PR5109
1K27R2F-L-GP PC5108

PC5111

1
2

PC5113
SC10U10V5KX-2GP

SCD1U10V2KX-4GP

DY

PC5114
SCD1U10V2KX-4GP

DY
2

PR5112
0R2J-2-GP

GND
NC#20
ADJ
VOUT
VOUT
VOUT

NC#6
EN
VIN
VIN
VIN

PU5102
RT9035-18GQW -GP-U

GAP-CLOSE-PW R

PC5109

5
4
3
2
1
PR5107
0R3J-0-U-GP
1
DY 2

PR5113
0R2J-2-GP
DY 2

PG5106
2

SC1KP50V2KX-1GP

POK
NC#4
NC#3
GND
NC#1

38,42 GFX_MEM_ON

DY

GAP-CLOSE-PW R

VDD
NC#12
NC#13
NC#14
NC#15

+1.8V_DELAY
Design current = 1.13A

11
12
13
14
15

1 PR5114 2
0R0402-PAD-2-GP

38,42 3.3V_RUN_GFX_ON

+1.8V_DELAY_IN
PG5104
1
2

SC22U6D3V5MX-2GP

+3.3V_SUS

38 1.8V_RUN_GFX_ON

PC5107
SC1U10V2KX-1GP

SSID = PWR.Plane.Regulator_1p8v

PR5106
0R0603-PAD-2-GP

PR5105

2
1

+5V_ALW

SC22U6D3V5MX-2GP

VDD
NC#12
NC#13
NC#14
NC#15

PR5104
1K27R2F-L-GP PC5105

PC5104

DY

11
12
13
14
15

PC5103

PG5101
2

GAP-CLOSE-PW R

NC#6
EN
VIN
VIN
VIN

SC10U10V5KX-2GP

DY DY

6
7
8
9
10

PC5101
SCD1U10V2KX-4GP

SCD1U10V2KX-4GP

PC5102

1 PR5102 2
0R0402-PAD-2-GP

38,42,72,86 RUN_ON

PU5101
RT9035-18GQW -GP-U

SC1KP50V2KX-1GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PC5110
SC1U10V2KX-1GP
Title
Size
A3
Date:

DC to DC 1.8V_RUN/1.8V_DELAY
Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

51

of

89

SSID = PWR.Plane.Regulator_1p05v

+PWR_SRC

+1.05V_VTT_PWR_SRC
PG5260
1
2

+1.05V_VTT_PWR_SRC

+1.05V_VTT_P

PC5266

5
6
7
8

PC5267

S
S
S
G
PL5201

51218_DRVH
51218_SW

+1.05V_VTT_P

1
2
IND-1UH-80-GP
1

PTC5306

1
2

1
2

1
2

1
2
1

2
VTT_SENSE

5
6
7
8
4
3
2
1

PC5273

DY SC330P50V2KX-3GP

PC5271 PTC5201

SE220U2VDM-8GP

DY

PC5270

SE220U2VDM-8GP

S
S
S
G

S
S
S
G

Frequency setting
420K -->300KHz
200K -->350KHz
100K -->390KHz
47K -->450KHz

PU5005

PR5292
2D2R5J-1-GP

PG5277

PU5004

D
D
D
D

PC5272
SC1U10V2KX-1GP

+5V_ALW

51218_DRVL

PR5291
470KR2F-GP TPS51218DSCR-GP-U1

+1.05V_VTT

+1.05V_VTT_P

+1.05V_VTT

PG5262
1
2

PG5263
1
2

GAP-CLOSE-PWR
PG5266
1
2

GAP-CLOSE-PWR
PG5267
1
2

GAP-CLOSE-PWR
PG5268
1
2

GAP-CLOSE-PWR
PG5270
1
2

GAP-CLOSE-PWR
PG5201
1
2

GAP-CLOSE-PWR
PG5271
1
2

GAP-CLOSE-PWR
PG5273
1
2

GAP-CLOSE-PWR
PG5274
1
2

GAP-CLOSE-PWR
PG5275
1
2

GAP-CLOSE-PWR
PG5276
1
2

GAP-CLOSE-PWR
PG5278
1
2

GAP-CLOSE-PWR

GAP-CLOSE-PWR

VTT_SENSE 12

11
10
9
8
7
6

SCD1U10V2KX-4GP

GND
VBST
DRVH
SW
V5IN
DRVL

SC4D7U6D3V5KX-3GP

PGOOD
TRIP
EN
VFB
CCM

Design Current = 22.7A


27.1<OCP<32A

GAP-CLOSE-PWR-3-GP

PC5201

1
2
3
4
5

D
D
D
D

SC1KP50V2KX-1GP

51218_VFB

SIR460DP-T1-GE3-GP

56K2R2F-2-GP
51218_TRIP
2

5
6
7
8

38 CPU_VTT_ON

PC5269
SCD1U25V3KX-GP
1

SIR460DP-T1-GE3-GP

GAP-CLOSE-PWR

PR5290
0R3J-0-U-GP
51218_VBST 1
251117B_LL1 2
51218_DRVH

4
3
2
1

PU5201

PR5289

4
3
2
1

37 VTT_PWRGD

GAP-CLOSE-PWR
PG5272
1
2

R1

PR5293
10KR2F-2-GP

PC5265

PC5268
SC4D7U25V5KX-GP

GAP-CLOSE-PWR
PG5269
1
2

D
D
D
D

PU5210
SI7686DP-T1-GP

SCD1U50V3KX-GP

GAP-CLOSE-PWR
PG5265
1
2

SC10U25V6KX-1GP

TPS51218 for +1.05V_VTT

SC10U25V6KX-1GP

GAP-CLOSE-PWR
PG5264
1
2

GAP-CLOSE-PWR
PG5261
1
2

51218_VFB

Vout=0.704V*(R1+R2)/R2

51218_DRVL

R2

PR5294
20KR2F-L-GP

+3.3V_ALW

PR5295
100KR2J-1-GP

VTT_PWRGD
A

H_VTTPWRGD_R

+1.05V_VTT

<Core Design>

PU5213

DMN66D0LDW-7-GP

Wistron Corporation

PR5297
1KR2J-1-GP

H_VTTPWRGD

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

1210 SB

Title

DC to DC +1.05V_VTT

H_VTTPWRGD 9

Size
Document Number
Custom
Date:
5

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet

52

of

DS2-Intel

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

CPU_GFXCORE

Size
Document Number
Custom
Date:
5

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

53

of

89

SSID = VIDEO
LED Location from left to right
HDD

BATTERY

50
1

LVDS_CBL_DET#

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
51

45

46

47

Near LCD1 CONN


+3.3V_RUN

eDP_LCD_HPD

81

1
1

R5412
R5411

+LCDVDD

DY
DY

2
2 0R2J-2-GP
0R2J-2-GP

+LCDVDD

DY

+3.3V_ALW

+3.3V_RUN
1
R5418

LBKLT_CTL_GPU 80
PANEL_BKEN_GPU 38,81

DY

LCD_SMBUS_PW R

2
0R2J-2-GP

1
2

LCD_PW M_R
2
0R0402-PAD-2-GP

1
2

R5410

For DPST function

R5405
R5406
10KR2J-3-GP DY DY 10KR2J-3-GP
2

LCD_TST_C
LCD_SMBDAT_1_R
LCD_SMBCLK_1_R
LCD_PW M
LCD_BL_EN

BAT1_LED_AMBER_P 66
BAT2_LED_BLUE_P 66
BREATH_PW RLED_P 66

eDP_AUX 81
eDP_AUX# 81

1 R5417 2
0R0402-PAD-2-GP

RN5402
SRN2K2J-1-GP

R5425
100KR2J-1-GP

RN5403
SRN2K2J-1-GP

U5401
LCD_SMBDAT_1
RN5404

LCD_DET_G

1
R5403

LCD_SMBDAT_1_R
LCD_SMBCLK_1_R

+3.3V_RUN

2
0R0402-PAD-2-GP

1
2

4
3

SRN100J-3-GP
R5424

+INV_PW R_SRC

4
3

LCD_TST 38

4
3

44

2
0R0402-PAD-2-GP

eDP_CTX_LRX_N0 80
eDP_CTX_LRX_P0 80

43

1
R5404

eDP_CTX_LRX_N1 80
eDP_CTX_LRX_P1 80

42

LVDS_CBL_DET# 21

41

C5403
SCD1U10V2KX-4GP

LCD1
48

2
1
C5402
SCD1U10V2KX-4GP

+LCDVDD

R5423

1
1

DY

eDP_AUX#
100KR2J-1-GP

DY

eDP_AUX
100KR2J-1-GP

LCD_SMBDAT 37,81

4
DMN66D0LDW -7-GP

LCD_SMBCLK_1

LCD_SMBCLK 37,81

49
IPEX-CONN40-2R-GP-U

LCD POWER
+3.3V_RUN

Q5401
1 D
2 D
3 G

C5410
SCD1U50V3KX-GP

D 6
D 5
S 4

+3.3V_ALW
1

SI3457BDV-T1-1GP

R5427
100KR2J-1-GP

38,80 LCDVDD_EN_GPU

R_PW R_SRC

LCDVDD_EN_GPU

38 LCD_VCC_TEST_EN

LCD_VCC_TEST_EN

2
D5401
BAT54C-7-F-GP

-1.10/0305
C_PW R_SRC

LCDVCC_EN

2
IN

R1

R2
Q5404
DDTC144EUA-7F-GP

2
47KR2J-2-GP

3 OUT

FPVCC_CTL3

1 GND

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
Document Number
Custom
Date:

Q5405
2N7002A-7-GP
37 EN_INVPW R

2
R5426
100KR2J-1-GP

1
R5419

1
3

C5412
SCD1U25V2ZY-1GP

LCDVDD_1

C5406

DMN66D0LDW -7-GP

Need confirm

2
1

C5411
SC1KP50V2KX-1GP

Q5402

+INV_PW R_SRC

+PW R_SRC

2
2
DY 100KR2J-1-GP

C5405

SCD1U10V2KX-4GP

1
R5416

-1.10/0301

U5402
1 D
2 D
3 G

R5415
100R3J-4-GP

SC10U6D3V5MX-3GP

SSID = Inverter

SI3456DDV-T1-GE3-GP
2
330KR2J-L1-GP
2 FPVCC_CTL1
SCD1U50V3KX-GP

1
R5414
1
C5404

LED BACKLIGHT CONVERTER POWER

D 6
D 5
S 4
1

+15V_ALW

+LCDVDD

20.F1093.040
2nd:20.F1289.040

LCD

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

54

of

89

SSID = VIDEO

1
R5506
1
R5507

CRT_G

C5507

SC6D8P50V2CN-GP

C5506

C5505

SC6D8P50V2CN-GP

1
SC6D8P50V2CN-GP

DY

CRT_B

C5504
SC22P50V2JN-4GP

C5503
SC22P50V2JN-4GP
2
1

C5502
SC22P50V2JN-4GP
2
1

DY

VSYNC_BUF
0R0402-PAD-2-GP
0R0402-PAD-2-GP

VSYNC_DOCK

74

0R0402-PAD-2-GP

HSYNC_DOCK

74

Layout Note:
*Pi-filter & 150 Ohm pull-down
resistors should be as close
as to CRT CONN.
* RGB signal will hit 75 Ohm
first, then pi-filter, finally
CRT CONN.

+5V_CRT_RUN

HSYNC_BUF
0R0402-PAD-2-GP

CRT_SW ITCH_HSYNC

1
R5504
1
R5505

DY

CRT_R

C5508
SCD1U10V2KX-4GP

14

75 CRT_SW ITCH_HSYNC

CRT_SW ITCH_VSYNC

R5501
150R2F-1-GP
2
1

BLUE_CRT

75 CRT_SW ITCH_VSYNC

L5502 1
2
BLM18BA220SN1D-GP
L5501 1
2
BLM18BA220SN1D-GP
L5503 1
2
BLM18BA220SN1D-GP

GREEN_CRT

R5502
150R2F-1-GP
2
1

75 BLUE_CRT

RED_CRT

R5503
150R2F-1-GP
2
1

75 RED_CRT
75 GREEN_CRT

R5508
HSYNC_BUF

HSYNC_5

JVGA_HS

33R2J-2-GP

14

U5501A
SSAHCT125PW R-GP
R5509

VSYNC_BUF

VSYNC_5

JVGA_VS

DY

DY C5501
2

C5509
SC100P50V2JN-3GP

U5501B
SSAHCT125PW R-GP

33R2J-2-GP

SC100P50V2JN-3GP

I2C

+5V_RUN
DAT_DDC2_CRT

75 DAT_DDC2_CRT

D5501
B0530W S-7-F-GP

CLK_DDC2_CRT

+5V_CRT_RUN

1
C5511
SC22P50V2JN-4GP

C5510
SC22P50V2JN-4GP

75 CLK_DDC2_CRT

FUSE5501
FUSE-3A32V-7-GP
+5V_CRT_RUN_R

MAX4885E has internal ESD protection


and internal level shift

-1.10/0310
AFTP5501
AFTP5502
AFTP5503
AFTP5504

CRT1

1
1
1
1

+5V_CRT_RUN_R
CRT_R
CRT_G
CRT_B

9
DAT_DDC2_CRT
CLK_DDC2_CRT
CRT_R
CRT_G
CRT_B

12
15
1
2
3

JVGA_VS
JVGA_HS

14
13

VCC_CRT

NC#4
NC#11

4
11

GND
GND
GND
GND
GND
GND
GND

5
6
7
8
10
16
17

DDCDATA_ID1
DDCCLK_ID3
CRT_RED
CRT_GREEN
CRT_BLUE
VSYNC
HSYNC
D-SUB-15-36-GP-U2

20.20431.015

CRT Connector
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

CRT

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

55

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Reserve

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

56

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Reserve

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

57

of

89

SSID = CPU

SSID = Thermal
1

+3.3V_RUN

R5802
10KR2J-3-GP

FAN1_TACH_FB
1

39 FAN1_TACH_FB

DY EC5801
SCD1U10V2KX-4GP

FAN1
5
FAN1_VOUT

DY

C5801
SC10U10V5KX-2GP

2
3
4
6

D5801
SDMK0340L-7-F-GP

AFTP5801

39 FAN1_VOUT

MLX-CON4-25-GP-U

CPU XDP

-1.10/0308

20.F1000.004
2nd:20.D0241.104

XDP1

XDP_OBS0
XDP_OBS1

9 XDP_OBS0
9 XDP_OBS1

9,25 H_PWRGD

XDP_OBS2
XDP_OBS3

9 XDP_OBS2
9 XDP_OBS3

R5803

TP5808
TP5810

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

1
1

XDP_OBS21
XDP_OBS20

PAD-2P-29-GP
R5804
22 PM_PWRBTN#_R

XDP_OBS6
XDP_OBS7

9 XDP_OBS6
9 XDP_OBS7

PAD-2P-29-GP

XDP_OBS4
XDP_OBS5

9 XDP_OBS4
9 XDP_OBS5

+1.05V_VTT

H_CPUPWRGD_XDP
PM_PWRBTN#_XDP
1

R5806

PAD-2P-29-GP
TP5815

9 H_PWRGD_XDP

PCIE_CLK_XDP_P
1 TP_PCIE_CLK_XDP_N

18,19,23,40 PCH_SMBDATA_MEM
18,19,23,40 PCH_SMBCLK_MEM

C5803
PAD-2P-29-GP

XDP_TCLK

9 XDP_TCLK

XDP_OBS16 1
XDP_OBS17 1

TP5802
TP5803

XDP_OBS8
XDP_OBS9

1
1

TP5804
TP5805

XDP_OBS10 1
XDP_OBS11 1

TP5806
TP5807

XDP_OBS18 1
XDP_OBS19 1

TP5809
TP5811

XDP_OBS12 1
XDP_OBS13 1

TP5812
TP5801

XDP_OBS14 1
XDP_OBS15 1

TP5813
TP5814

BCLK_ITP_P
BCLK_ITP_N

AFTP5802
AFTP5803
AFTP5804

+1.05V_VTT

C5802
PAD-2P-29-GP
C

BCLK_ITP_P
BCLK_ITP_N

9
9

1
R5805
1
R5807

XDP_RST#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

39 FAN1_DET#

FAN1_VOUT
FAN1_TACH_FB
FAN1_DET#

Place R near XDP1 CONN


within 2"

-1.10/0308

XDP_PREQ#
XDP_PRDY#

1
1
1

-1.10/0308
9 XDP_PREQ#
9 XDP_PRDY#

-1.10/0308

NP1
61
2
62
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
64
NP2

DY

PLTRST1# 9,21,80

0R2J-2-GP
2

H_CPURST# 9
XDP_DBRESET#

PAD-2P-29-GP

9,22,38

XDP_TDO 9
XDP_TRST# 9
XDP_TDI 9
XDP_TMS 9

R5808
2

+1.05V_VTT
1

PAD-2P-29-GP

-1.10/0308

PAD-60P-GP

ZZ.00PAD.Q81

SSID = PCH

A 33 ohm series resistor should be placed


within 1 inch (or 25.4 mm) of the PCH to
source terminate the interface.

PCH XDP
Place near XDP CONN

R5832

XDP_PWRBTN#_R

0R2J-2-GP +3.3V_RUN

18,19,23,40 PCH_SMBDATA_MEM
18,19,23,40 PCH_SMBCLK_MEM
24 PCH_JTAG_TCK

1
R5837

DY

PCH_JTAG_TCK_R

2
0R2J-2-GP

-1.10/0308

R5822
R5824

XDP_FN14
XDP_FN15

PCH_XDP_RST#
XDP_DBRESET#

R5828
R5826

+3.3V_RUN

PCH_JTAG_TDO_R
PCH_JTAG_RST#_R
PCH_JTAG_TDI_R
PCH_JTAG_TMS_R

DY

2
2
2
2

DY
DY
DY
DY

1
1 0R2J-2-GP
1 0R2J-2-GP
1 0R2J-2-GP
0R2J-2-GP

RTC_BAT_DET#_R
PCH_GPIO37 25

PCH_JTAG_TDO

1KR2J-1-GP

PCH_JTAG_TDI

R5815

DY

R5811

PCH_JTAG_TMS

25

PCH_GPIO16 25
TEMP_ALERT# 25,38

R5830

DY

DY

R5827

DY

R5831

PLTRST2# 21,32,34,72
XDP_DBRESET# 9,22,38
PCH_JTAG_TDO 24
PCH_JTAG_RST# 24
PCH_JTAG_TDI 24
PCH_JTAG_TMS 24

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

PAD-60P-GP

Title

ZZ.00PAD.Q81

Size
C
Date:

DY

1
1 33R2J-2-GP
33R2J-2-GP
1
1 33R2J-2-GP
33R2J-2-GP

DY
DY

PCMCLK_REQ# 23,32
MINI1CLK_REQ# 23,64
HDD_DET#_R 24
PCH_GPIO19 24

R5814

DY

DY
DY

2
2

R5833
R5834
R5835
R5836
R5838

2
2

25
25

XDP_FN12
XDP_FN13

DY
DY

LED_BD_DET#_R
SIO_EXT_SCI#_R

XDP_FN6
XDP_FN7

2
2

1
1 33R2J-2-GP
33R2J-2-GP
1
1 33R2J-2-GP
33R2J-2-GP
1
1 33R2J-2-GP
33R2J-2-GP

XDP_FN4
XDP_FN5

DY
DY

DY

2
2 33R2J-2-GP
33R2J-2-GP
2
2 33R2J-2-GP
33R2J-2-GP

R5818
R5820

DY
DY

2
2

9,37,38 RUNPWROK
22 PM_PWRBTN#_R

DY
DY

R5801
R5817

XDP_FN10
XDP_FN11

2
2

DY
DY

R5809
R5810

XDP_FN8
XDP_FN9

100R2F-L1-GP-U

1
R5821 1
R5823
1
R5825 1
R5829

XDP_FN16
XDP_FN17

200R2F-L-GP

21 USB_OC#12_13
21 PCH_OC7#

XDP_FN2
XDP_FN3

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

100R2F-L1-GP-U

21 USB_OC#8_9
21 USB_OC#10_11

XDP_FN0
XDP_FN1

100R2F-L1-GP-U

51R2F-2-GP
R5839

DY
DY

2
2 33R2J-2-GP
33R2J-2-GP
2
2 33R2J-2-GP
33R2J-2-GP

200R2F-L-GP

21 USB_OC#4_5
21 USB_OC#6_7

DY
DY

+3.3V_SUS

200R2F-L-GP

21 USB_OC#0_1_R
21 USB_OC#2_3_R
PCH_JTAG_TCK

1
R5812 1
R5816
1
R5813 1
R5819

Place near PCH side

+3.3V_SUS

NP1
61
2
62
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
63
64
NP2

XDP2

Place near PCH side

Reserve

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

58

of

89

SSID = SATA

SATA ODD Connector


ODD1

SATA_RX- and SATA_RX+ Trace


Length match within 20 mil

13
S1
S2
S3
S4
S5
S6
S7

24 SATA_PTX_ORX1+
24 SATA_PTX_ORX1D

24 SATA_PRX_OTX124 SATA_PRX_OTX1+

C5902 2
C5903 2

1 SCD01U50V2KX-1GP
1 SCD01U50V2KX-1GP

SATA_PRX_OTX1-_C
SATA_PRX_OTX1+_C

+5V_MOD

P1
P2
P3
P4
P5
P6
14

1
C5905
SCD1U10V2KX-4GP

C5904
SC10U6D3V5KX-1GP

37 ODD_DET#

SKT-SATA7P+6P-85-GP

62.10065.B01

SATA HDD Connector

Place near HDD CONN

1 SCD01U50V2KX-1GP
1 SCD01U50V2KX-1GP

SATA_PRX_HTX0-_C
SATA_PRX_HTX0+_C

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NP2
24

+3.3V_RUN

HDD_DET#

24 HDD_DET#

+5V_RUN
FFS_INT2

40 FFS_INT2

09/0603

SKT-SATA22P-20-GP

62.10065.261
A

Main:62.10065.261

FFS_INT2
#1) It is active High when Free Fall is detected,
allowing Pin.11 to be pulled high.
Pin.11 driven low on power up and then
held low unless free fall.

C5908

C5909

C5907

DY

SCD1U10V2KX-4GP

2
2

C5906

SC10U6D3V5KX-1GP

C5901
C5910

24 SATA_PRX_HTX024 SATA_PRX_HTX0+

DY

2
3
4
5
6
7

24 SATA_PTX_HRX0+
24 SATA_PTX_HRX0-

+5V_RUN

SCD1U10V2KX-4GP

+3.3V_RUN

HDD1

23
NP1
1

SATA HDD Interface comment


******************************
--- GND
RX+
RX--- GND
TXTX+
--- GND
******************************
------------ 3.3V
------------ 3.3V
------------ 3.3V
--- GND
--- GND / Dell Detected Pin
--- GND
------------ 5V
------------ 5V
------------ 5V
--- GND
Staggered spinup/activity (in supporting drives)
--- GND
------------ 12V
------------ 12V
------------ 12V
******************************

SC10U6D3V5KX-1GP

SSID = SATA

<Core Design>

2nd:62.10065.511

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

HDD / ODD Connector

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

59

of

89

SSID = AUDIO

SSID = AUDIO

AUD_VREFOUT_B

SPEAKER
SPK1

30
30
30
30

AUD_SPK_L+
AUD_SPK_LAUD_SPK_R+
AUD_SPK_R-

AUD_SPK_L+
AUD_SPK_LAUD_SPK_R+
AUD_SPK_R-

2
3
4
5
6

25 SPEAKER_DET#

SPEAKER_DET#

DY

AUDIO-JK128-GP

22.10088.F61

DY

DY

SC270P50V2JN-2GP
EC6008
2
1

8
SC270P50V2JN-2GP
EC6007
2
1

2
BLM18BD601SN1D-GP
EC6002 EC6003

600ohm 100MHz
200mA 0.5ohm DC

1
2
6
3
4
5
7
8
NP1
NP2

SC270P50V2JN-2GP
EC6006
2
1

MIC_IN_R_C

AFTP6002

SC270P50V2JN-2GP
EC6009
2
1

MIC_IN_L_C

SC470P50V2JN-GP
2
1

30 MIC_IN_R_2

MIC IN
MIC1

1
EL6002
1
EL6003

MIC_IN_R_2

AUD_MIC_SW ITCH

30 AUD_MIC_SW ITCH

SC470P50V2JN-GP
2
1

MIC_IN_L_2

30 MIC_IN_L_2

C6002

DY SC1U10V2KX-1GP
2

1
2

R6003
4K7R2J-2-GP

R6002
4K7R2J-2-GP

30 AUD_VREFOUT_B

MLX-CON6-10-GP-U

DY

20.F0693.006
Main:20.F0693.006
2nd:20.F0711.006

1
1
1
1
1

AFTP6003
AFTP6004
AFTP6005
AFTP6001
AFTP6006

AUD_SPK_L+
AUD_SPK_LAUD_SPK_R+
AUD_SPK_RSPEAKER_DET#

SSID = AUDIO

Earphone
B

30,38 AUD_HP_NB_SENSE

AUD_HP_NB_SENSE
LOUT1

AUD_HP_JACK_R_2

1
2

SC1000P50V3JN-GP-U

600ohm 100MHz
200mA 0.5ohm DC
C6001

AUD_HP_JACK_L_1

1
2
EL6004
1
2
EL6001 BLM18BD601SN1D-GP

C6003
SC1000P50V3JN-GP-U

AUD_HP_JACK_R_1

SC270P50V2JN-2GP
EC6005
2
1

30 AUD_HP_JACK_R_2

AUD_HP_JACK_L_2

SC270P50V2JN-2GP
EC6004
2
1

30 AUD_HP_JACK_L_2

1
2
6
3
4
5
7
8
NP1
NP2
AUDIO-JK128-GP

22.10088.F61

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Audio Jack / Speaker Connector

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

60

of

89

SSID = LOM

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
C
Date:
5

Document Number

LAN

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

61

of

89

SSID = Flash.ROM
09/0416, Pin.2
From Intel checklist,
SPI_CS0#/CS1#
No series resistor required
if routing length is 1.5"-6.5"
(with 1 or 2 SPI device)

1
2
3
4

CS#
DO/IO1
WP#/IO2
GND

VCC
HOLD#/IO3
CLK
DI/IO0

8
7
6
5

SPI_VCC
SPI_HOLD#
SPI_CLK_R
SPI_DO_R

1
1

1
PCH_SPI_CS0#_R
PCH_SPI_DIN
SPI_W P#_SEL_R

2
0R0402-PAD-2-GP

U6201

1
R6207

24 PCH_SPI_CS0#
24 PCH_SPI_DIN

1
R6206
3K3R2J-3-GP

R6205

DY 0R2J-2-GP
2

R6204
0R0402-PAD-2-GP

C6202
SCD1U10V2KX-4GP

C6201
SC10U6D3V5MX-3GP

DY
2

R6203

DY 0R2J-2-GP
2

R6202
3K3R2J-3-GP

+3.3V_RUN

+3.3V_ALW _PCH

+3.3V_RUN

+3.3V_ALW _PCH

09/0416, Pin.6
Intel checklist
No series resistor required if routing length is 1.5"-6.5"
(with 1 or 2 SPI device)

RN6201

1
2

PCH_SPI_CLK
PCH_SPI_DO

4
3

PCH_SPI_CLK 24
PCH_SPI_DO 24

SRN33J-5-GP-U
W 25Q16BVSSIG-GP

R6212

R6215
3K3R2J-3-GP

1
R6216

2
0R0402-PAD-2-GP

PCH_SPI_CS1#_R
PCH_SPI_DIN
SPI_W P#_SEL_R2

1
2
3
4

CS#
DO
WP#
VSS

VCC
HOLD#
CLK
DI

8
7
6
5

SPI_VCC2
SPI_HOLD#2
SPI_CLK_R
SPI_DO_R

1
R6201

DY 0R2J-2-GP

C6203
SCD1U10V2KX-4GP

DY

C6204
SC10U6D3V5MX-3GP

24 PCH_SPI_CS1#

2 SPI_W P#_SEL_R2
0R0402-PAD-2-GP

U6202

+3.3V_RUN

R6213
0R0402-PAD-2-GP

DY 0R2J-2-GP
2

R6211
3K3R2J-3-GP

1
R6214

+3.3V_ALW _PCH

+3.3V_RUN

+3.3V_ALW _PCH

2 SPI_W P#_SEL_R
0R0402-PAD-2-GP

1
R6210

SPI_W P#_SEL

38 SPI_W P#_SEL

W 25Q32BVSSIG-1-GP

-1.10/0305

#1 source: 72.25Q16.001 (2MB, Winbond)


#2 source: 72.25165.B01 (2MB, MXIC)
#3 source: 72.02516.A01 (2MB, Numonyx)
#1 source: 72.25Q32.A01 (4MB, Winbond)
#2 source: 72.25325.A01 (4MB, MXIC)
#3 source: 72.25P32.B01 (4MB, Numonyx)
#1 source: 72.25Q64.001 (8MB, Winbond)
#2 source: 72.25644.001 (8MB, MXIC)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Flash / EEPROM

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

62

of

89

SSID = USB

+5V_USB0

C6304

TC6301
ST150U6D3VDML3GP

(1A / Port)

C6303

C6301

DY

TPS2062AD-GP

100 mil

8
7
6
5

OC1#
OUT1
OUT2
OC2#

C6302
SC1U6D3V2KX-GP

GND
IN
EN1#
EN2#

1
2
3
4

SCD1U10V2KX-4GP

USB_OC#0_1 21

U6301

GAP-CLOSE-PWR-2U-GP
USB_5V_IN
2
GAP-CLOSE-PWR-2U-GP

GAP-CLOSE-PWR-2U-GP

USB Power

GAP-CLOSE-PWR-2U-GP

G6304

SCD1U10V2KX-4GP

G6301

+5V_ALW

G6303

SC4D7U10V5ZY-3GP

G6302
D

38,76 USB_SIDE_EN#

Dual USB Connector


+5V_USB0

+5V_USB0
USB1

11
9
1

EL6302

1
21 USBP021 USBP0+

USB_0-_R
USB_0+_R

ACM2012-900-2P-T-GP

EL6301

2
3
4
10
12

USB_01-_R
USB_01+_R

6
7
8

USBP1- 21
USBP1+ 21

ACM2012-900-2P-T-GP
SKT-USB-375-GP

22.10321.751
Main source: 22.10321.751
Second source: 22.10321.F61
B

OE#

Function

Disconnect

D=1D

D=2D

ED6301
USB_01-_R

1
2
3

USB_0-_R

ESD I/O1
GND
ESD I/O2

+5V_USB0

ESD I/O4
VP
ESD I/O3

6
5
4

USB_01+_R
USB_0+_R

IP4220CZ6-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

09/0429

Title
Size
Document Number
Custom
Date:

USB

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

63

of

89

SSID = Wireless
JMINI Pin

Debug Pin Name

EC Pin

16

HOST_DEBUG_TX

70

17

HOST_DEBUG_RX

71

19

8051_TX

82

42

8051_RX

81

-1.10/0318
R6413
0R3J-0-U-GP

DEBUG PINS

21 USBP4-

USBP4-_R

21 USBP4+

USBP4+_R

R6416
0R3J-0-U-GP

Close WLAN1
WLAN1

23,58 MINI1CLK_REQ#

DY

10KR2J-3-GP

35,38,72 PCIE_WAKE#
1 R6420 2
1 R6421 2
0R0402-PAD-2-GP

73 COEX2_WLAN_ACTIVE
73 COEX1_BT_ACTIVE

PCIE_WAKE#
0R0402-PAD-2-GP
COEX2_WLAN_ACTIVE_R
COEX1_BT_ACTIVE_R
MINI1CLK_REQ#
CLK_PCIE_MINI1#
CLK_PCIE_MINI1

23 CLK_PCIE_MINI1#
23 CLK_PCIE_MINI1

1
R6411

37,70 MSCLK

DY

HOST_DEBUG_RX
MS_CLK_1

37,70 HOST_DEBUG_RX
0R2J-2-GP
23 PCIE_PRX_WLANTX_N2
23 PCIE_PRX_WLANTX_P2

23 PCIE_PTX_WLANRX_N2_C
23 PCIE_PTX_WLANRX_P2_C
PCIE_MCARD1_DET#

25 PCIE_MCARD1_DET#

1
R6412

25 USB_MCARD1_DET#

2
DY 0R2J-2-GP

+3.3V_WLAN

+5V_RUN

1
G6401

+3.3V_ALW

1
G6402

Debug Only.

+5V_DBG_RUN
GAP-OPEN-PWR
+3.3V_DBG_ALW
GAP-OPEN-PWR

53
NP1
1

+3.3V_WLAN

3
5
7
9
11
13
15

4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
NP2
54

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+1.5V_RUN_CPU

HOST_DEBUG_TX

HOST_DEBUG_TX 37

WLAN_RADIO_OFF#
WLAN_PCIE_RST#

A
SDMK0340L-7-F-GP
1
0R0402-PAD-2-GP

+3.3V_WLAN

K
D6401
2
R6401

WLAN_RADIO_DIS#

38

PLTRST4# 21,35,76
C

+1.5V_RUN_CPU

WIMAX_LED# 66

USBP4-_R
USBP4+_R
USB_MCARD1_DET#
WIMAX_LED#
LED_WLAN_OUT#

R6402

+1.5V_RUN_CPU

R6415
0R2J-2-GP

0R2J-2-GP

DY

1
R6414

MSDATA 37,70

DY

+3.3V_WLAN

+3.3V_RUN

LED_WLAN_OUT#

66

SKT-MINI52P-8-GP-U

62.10043.391

C6408

RN6402

SRN100KJ-6-GP

+15V_ALW

4
3

C6407

1
2

C6406

SCD047U10V2KX-2GP
2
1

+1.5V_RUN_CPU

SCD047U10V2KX-2GP
2
1

C6405

SCD1U10V2KX-4GP
2
1

C6404

SCD047U10V2KX-2GP
2
1

C6401

SCD047U10V2KX-2GP
2
1

C6403

SCD1U10V2KX-4GP
2
1

C6402

+3.3V_WLAN

SCD1U10V2KX-4GP
2
1

SC4D7U6D3V3KX-GP
2
1

+3.3V_WLAN

+3.3V_ALW

+3.3V_WLAN
U6401
SI3456DDV-T1-GE3-GP

3.3V_WLAN_ENABLE#
D
D
G

D 6
D 5
S 4

1
2
3

C6410
SC4700P50V2KX-1GP

Wireless Switch

WLAN SW (Top View)

U6402
DMN66D0LDW-7-GP

3.3V_WLAN_ENABLE

R6417
200KR2J-L1-GP

-1.10/0317

-1.10/0302
SW1

OFF

ON

1
NP1
A

38 AUX_EN_WOWL

NP2
2

AFTP6402

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

SW-SLIDE7-2-GP
Title

62.40018.601
AFTP6401

-1.10/0302

WLAN / Serial Out Connector

Size
Document Number
Custom

WIRELESS_ON#/OFF_R

Date:
5

<Core Design>

R6419
100KR2J-1-GP

C
2

1
2

C6409
SC1U10V2KX-1GP

2 WIRELESS_ON#/OFF_R
0R0402-PAD-2-GP
1

COM

1
R6418

38 WIRELESS_ON#/OFF

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

64

of

89

SSID = Wireless

PCH1

BTB2

BTB1

WWAN
CONN

Page.76

SIM
SKT

IO Board Side

MB Board Side

RN6501

1
2

SRN100KJ-6-GP

4
3

+15V_ALW

+3.3V_ALW
+3.3V_RUN_W W AN

3.3V_W W AN_ENABLE#

D 6
D 5
S 4

SI3456DDV-T1-GE3-GP
C6501
SC4700P50V2KX-1GP

-1.10/0305
+3.3V_RUN_W W AN

U6502
DMN66D0LDW -7-GP

3.3V_W W AN_ENABLE

R6501
200KR2J-L1-GP

U6501
1 D
2 D
3 G

R6503
100R2J-2-GP

-1.10/0302
38 MCARD_W W AN_PW REN

W W AN_DIS

R6502
100KR2J-1-GP

3.3V_W W AN_ENABLE#

2N7002A-7-GP
Q6501

-1.10/0302

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

WWAN

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

65

of

89

SSID = User.interface

LED Location from left to right


(MB, Top View)
NUM
LED6603

+5V_ALW

CAPS

SCRLK

LED6602

LED6601

+3.3V_SUS
+5V_ALW

BREATH POWER LED


G

SCRLK LED
Q6602

CAP_LED

NUM LED

BREATH_PW RLED_R#

DY

+5V_RUN
Q6607

LED6603

2LED_NUM_R

EC6601
SCD1U10V2KX-4GP

2
NUM_LED

BREATH_PW RLED_P 54

DDTA143ECA-7-F-GP

Q6603
2N7002A-7-GP

EC6603
SCD1U10V2KX-4GP

R6608

R1

BREATH_PW RLED_R

BREATH_PW RLED_B 76

LED-B-98-GP

DY

680R2J-3-GP

A
1

R2

DDTA143ECA-7-F-GP

DY

24 SATA_ACT#_R

2
R6609

SATA_ACT_C#
1
20KR2J-L2-GP

LED-B-98-GP
EC6605
SCD1U10V2KX-4GP

HDD LED

E
HDD_LED

R6610
1KR2J-1-GP
1

DDTA143ECA-7-F-GP

HDD_LED_B 77

DY

EC6604
SCD1U10V2KX-4GP

+3.3V_W LAN

WI-MAX LED

680R2J-3-GP

+5V_ALW

LED6602

2LED_CAP_R

Q6606

EC6602
SCD1U10V2KX-4GP

R6606

DDTA143ECA-7-F-GP

NUM_LED_R#

37,74 BREATH_LED#

R1

4
3

SRN20KJ-GP-U

R2

1
2

38 CAP_LED#
38 NUM_LED#

CAP_LED_R#

2
120R2J-2-GP

LED-B-98-GP

DY

Q6605
RN6603

680R2J-3-GP

+5V_ALW

CAPS LED

2LED_SCRLK_R

DDTA143ECA-7-F-GP

LED6601

SCRLK_LED

1
R6624
R6604
330R2J-3-GP
2
1

Q6604

R6603

R1

R2

R1

R6602

1 SCRL_LED_R#
20KR2J-L2-GP

R1

R2
38 SCRL_LED#

R2

R6625
100KR2J-1-GP

DY
C

64 W IMAX_LED#

WWAN LED

D6602
BAT54A-3-GP

+3.3V_RUN

DY
2

R6613
100KR2J-1-GP

76 LED_W W AN_OUT#

+3.3V_W LAN

WLAN LED

R6614

+5V_RUN

DY100KR2J-1-GP

Q6609

1LED_W LAN_OUT_R# B
20KR2J-L2-GP

2
R6617

R1

64 LED_W LAN_OUT#

E
C

SDMK0340L-7-F-GP

LED_W AN_OUT_R

R6618
1KR2J-1-GP
2

LED_W LAN_OUT_B 77
B

DDTA143ECA-7-F-GP

Bluetooth LED

DY

EC6608
SCD1U10V2KX-4GP

+5V_RUN
Q6608
R2

+5V_ALW

73 BT_ACTIVE_K#

2
R6601

BAT2_LED_BLUE_B
1
1KR2J-1-GP

BT_ACTIVE_K#

2
R6611

1 BT_ACT_K_R#
20KR2J-L2-GP

R1

Battery LED (Blue)

E
BT_LED_R

R6612
1KR2J-1-GP
2

BT_LED_B 77

DDTA143ECA-7-F-GP

BAT2_LED_BLUE_B 77

R2

D6601

DY

Q6610
BAT2_LED_R#

E
BAT2_LED

2
R6620

BAT2_LED_BLUE_P
1
330R2J-3-GP

DDTA143ECA-7-F-GP

BAT2_LED_BLUE_P 54

SRN10KJ-5-GP

R1

37 BAT2_LED#
37 BAT1_LED#

1
2

R2

RN6601

4
3

EC6606
SCD1U10V2KX-4GP

DY
2

Battery LED (Amber)

EC6609
SCD1U10V2KX-4GP

+5V_ALW
Q6611
R1

RN6602

BAT1_LED

3
4

DDTA143ECA-7-F-GP

2
1

BAT1_LED_AMBER_B 77
BAT1_LED_AMBER_P 54

DY

<Core Design>

EC6610
SCD1U10V2KX-4GP

Wistron Corporation

SRN1KJ-7-GP

BAT1_LED_AMBER_B
BAT1_LED_AMBER_P

R2
BAT1_LED_R#

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

LED

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

66

of

89

SSID = SmartCard

-1.10/0317

Smartcard Socket

-1.10/0319
1

SmartCard
2

SC

C6705
SC390P50V2KX-GP

-1.10/0317

SC1

SC

SC1_VPP

-1.10/0319

R6707
10KR2J-3-GP

1
2

SC

C6702
SC1U10V2KX-1GP

SC

C6701
SCD1U10V2KX-4GP

34 SC_VCC

1
R6703 1
R6701

34 SC_RST#
34 SC_CLK

34

SC_IO

SC
SC

R6704

Pleace near SC1 CONN

SC
-1.10/0319

R6705

SC_RST#_R
2
2 220R2F-GP SC_CLK_R
0R2J-2-GP SC_DET#
SC_IO_R

SC

SC

2
10KR2J-3-GP

220R2F-GP

C6704
SC22P50V2JN-4GP

VCC

VPP

2
3
SW

RST
CLK
SW

RESERVED#4
RESERVED#8

SC

I/O

4
8

NP1
NP2

NP1
NP2

GND
GND

5
GND

220R2F-GP

SC

SC_EG_D+ 34
SC_C4 34
SC_EG_D- 34

R6702

SC1SKT1
1

DY

SMARTCARD-4P-GP-U

21.H0136.011

Belong to DIP, not SMT.

SMARTCARD-8P-1-GP

62.10024.C11

+3.3V_RUN

R6706
100KR2J-1-GP

DY

SC_DET#

SC1_VPP

SC_RST#_R

DY
1

SC
2

SCD1U10V2KX-4GP

C6703

TP6701

34 SC_DET#

C6706
SC270P50V2JN-2GP

-1.10/0318

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Smart Card Socket

Size
Document Number
Custom
Date:
5

Monday, March 22, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet
1

67

of

89

SSID = Touch.Pad

TouchPad Connector
TPAD1

BC_CLK_ECE1077
BC_DAT_ECE1077
BC_INT#_ECE1077

37 BC_CLK_ECE1077
37 BC_DAT_ECE1077
37 BC_INT#_ECE1077

3
4

RN6801
SRN4K7J-8-GP

DY

CLK_TP_SIO_1
DAT_TP_SIO_1
+5V_ALW

AFTP6802

1
17

ERN6801

1
2

37 DAT_TP_SIO
37 CLK_TP_SIO

DY

+3.3V_ALW

EC6803
SC100P50V2JN-3GP

2
1

DY

EC6802

+3.3V_ALW

SC100P50V2JN-3GP

EC6801

SC100P50V2JN-3GP

16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01

18
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

TP_DET#

38 TP_DET#

Touch PAD Module Side


TP_DET#
GND
GND
BC_CLK (ECE1077)
BC_DAT (ECE1077)
BC_INT# (ECE1077)
3.3V_ALW
3.3V_RUN (Internal
PS2_CLK
PS2_DATA
5V_RUN (Backlight,
5V_ALW
PWM (Backlight, No
GND (Backlight, No
GND
Diag_loop

NC)
No Use)
Use)
Use)

MLX-CON16-10-GP

4
3

20.K0227.016
1

DY
2

MLVG0402220NV09BP-GP

EL6801

EL6802
MLVG0402220NV09BP-GP

DY
2

SRN100J-3-GP

AFTP6801
AFTP6803
AFTP6804
AFTP6805
AFTP6806
AFTP6807
AFTP6808
AFTP6809

1
1
1
1
1
1
1
1

BC_DAT_ECE1077
BC_CLK_ECE1077
BC_INT#_ECE1077
+3.3V_ALW
CLK_TP_SIO_1
DAT_TP_SIO_1
+5V_ALW
TP_DET#

+3.3V_ALW

CLK_TP_SIO_1

ED6801
PRTR5V0U2X-GP

DY
<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

DAT_TP_SIO_1
Title
Size
A3
Date:
5

Touch Pad Connector

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

68

of

89

SSID = User.interface

+3.3V_ALW

Hall Sensor

+3.3V_ALW

C6902
SCD1U10V2KX-4GP
U6901

R6902
100KR2J-1-GP

AFTP6901

VDD

OUTPUT

VSS
1
R6901

2 LID_CL_SIO#_R
0R0402-PAD-2-GP

AFTP6903

EM-6781-T30-GP

38 LID_CL_SIO#

74.06781.07B

C6901
SCD047U10V2KX-2GP

1st : AKE 74.06781.07B


2nd : Allegro 75.03212.060

AFTP6902

LID_CL_SIO#_R

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

Hall Sensor

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

69

of

89

SSID = User.Interface

LPC Debug port


+3.3V_RUN
LDBG1
1
2
3
4
5
6
DY 7
8
9
10
11
12

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
R7008
CLK_PCI_TPM_C
R7002

DY

DY

0R2J-2-GP
0R2J-2-GP

LPC_LAD0 24,35,36,37,38
LPC_LAD1 24,35,36,37,38
LPC_LAD2 24,35,36,37,38
LPC_LAD3 24,35,36,37,38
LPC_LFRAME# 24,35,36,37,38
PLTRST3# 21,37,38
CLK_PCI_TPM 23,35

MLX-CON10-7-GP

20.D0183.110

JTAG Debug port

+3.3V_ALW

+3.3V_ALW

8
7
6
5

JTAG1

DY

RN7001
SRN10KJ-6-GP

DY
2

R7001
49D9R2F-GP

1
2
3
4

-1.10/0310

JTAG_PU

2
3
4
5
6

JTAG_TDI
JTAG_TMS
JTAG_CLK
JTAG_TDO

JTAG_TDI 37
JTAG_TMS 37
JTAG_CLK 37
JTAG_TDO 37

8
MLX-CON6-9-GP

20.D0198.106
B

+3.3V_ALW
JDBG2

DY

5
4
3
2

MSDATA
MSCLK
HOST_DEBUG_RX

MSDATA 37,64
MSCLK 37,64
HOST_DEBUG_RX 37,64

1
6
MLX-CON5-10-GP-U

20.D0198.105

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

JTAG Debug

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

70

of

89

SSID = 1394

Flash Reader Socket

SDMSXD_VCC
R7104
0R0603-PAD-2-GP

CARD1

32 SD_MMC_DAT0
32 SD_MMC_DAT3
32 SD_MMC_DAT1
32 SD_MMC_DAT2
32 SD_MMC_CMD
32 SD_MMC_CLK

R7105
150KR2J-GP

DY
2

C7103

1
2

C7102

SD_VCC

SCD1U10V2KX-4GP

SD_VCC

2
SC10U6D3V3MX-GP

SD_MMC_DAT0
SD_MMC_DAT3
SD_MMC_DAT1
SD_MMC_DAT2
SD_MMC_CMD
SD_MMC_CLK

7
1
8
9
2
5
NP1
NP2

Place near CARD1

VDD
DAT0
CD/DAT3
DATE1
DATE2
CMD
CLK
NP1
NP2

COMMON GROUND SWITCH


CARD DETECT SWITCH
WRITE PROTECT SWITCH
GROUND SWITCH

10
11
12
13

VSS
VSS
GND
GND

3
6
14
15

SD_MMC_CD#
SDW P

SD_MMC_CD# 32
SDW P 32

SKT-SDCARD-16-GP-U

20.I0086.001
Main:20.I0086.001

SDW P
SD_MMC_CD#
SD_MMC_CLK
SD_MMC_CMD
SD_MMC_DAT0
SD_MMC_DAT1
SD_MMC_DAT2
SD_MMC_DAT3

DY

EC7112
SC100P50V2JN-3GP

DY

EC7111
SC100P50V2JN-3GP
2
1

DY

EC7110
SC100P50V2JN-3GP
2
1

DY

EC7109
SC100P50V2JN-3GP
2
1

DY

SSID = 1394

R7108
56R2J-4-GP

1394 Connector

C7104
SCD01U16V2KX-3GP

R7107
56R2J-4-GP

-1.10/0302

TPA0P
TPA0N
TPB0P
TPB0N

TPB0N
TPB0P
TPA0N
TPA0P

R7106
R7101
R7109
R7113

1
1
1
1

1394
TPB0TPB0+
TPA0TPA0+

2
2 0R3J-0-U-GP
2 0R3J-0-U-GP
2 0R3J-0-U-GP
0R3J-0-U-GP

TPA0P
TPA0N
TPB0P
TPB0N

DY
2

2
32
32
32
32

Shield GND separately for pairs of


TPA+ & TPA- and TPB+ & TPB-

TPBIAS0

TPBIAS0

32

C7101
SCD33U10V3KX-3GP

DY

EC7108
SC100P50V2JN-3GP
2
1

For EMI

DY

EC7107
SC100P50V2JN-3GP
2
1

DY

EC7106
SC100P50V2JN-3GP
2
1

EC7105
SC100P50V2JN-3GP
2
1

R7111
56R2J-4-GP

TPB0TPB0+
TPA0TPA0+
GND
GND

SKT-1394-4P-26-GP-U1

R7110
56R2J-4-GP

1
2
3
4
5
6

22.10218.T41
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Close to U3201
Size
A3
Date:
5

Wistron Corporation

R7112
5K11R2F-L1-GP

C7105
SC270P50V2JN-2GP

TPB_EMI

<Core Design>

1394 Connector / Flash Socket

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

71

of

89

SSID = CARDBUS

PCMCIA1

FOX-CONN84-GP

62.10024.981

Close to Socket

CBS_CCLK 32
CBS_CIRDY# 32
CBS_CC/BE2# 32

SC1U6D3V2KX-GP
2
1

CBS_CCLK
CBS_CIRDY#
CBS_CC/BE2#
CBS_CAD18
CBS_CAD20
CBS_CAD21
CBS_CAD22
CBS_CAD23
CBS_CAD24
CBS_CAD25
CBS_CAD26
CBS_CAD27
CBS_CAD29
CBS_DATA2
CBS_CCLKRUN#

+5V_RUN
+CBS_VCC
+CBS_VPP

VPPEN0
VPPEN1

3
4

PCC
EN0
EN1

VCC5_IN
VCC5_IN

15
13

NC#6
NC#7
NC#10

VCC3_IN

11

VCC_OUT
VCC_OUT
VCC_OUT

14
12
9

VCC3_EN
VCC5_EN

2
1

C7208

PCC SC1U6D3V2KX-GP
2

VPPEN0
VPPEN1

U7201
32
32

+CBS_VPP

32

Close to Socket

PCC

FLG

VPP_OUT

16

PCC

+CBS_VCC
C

6
7
10
CBS_DATA2 32
CBS_CCLKRUN#

C7207

PCC

+3.3V_RUN

GND

SC10U6D3V5KX-1GP
2
1

PCC

32 CBS_CCD2#

CBS_CC/BE1# 32
CBS_CPAR 32
CBS_CPERR# 32
CBS_CGNT# 32
CBS_CINT# 32

C7210

C7209
PCC
PCC
SCD01U16V2KX-3GP

PCC

C7206
SCD1U10V2KX-4GP

PCC

C7205
SC10U6D3V5KX-1GP
2
1

PCC

C7201
SCD01U16V2KX-3GP
2
1

C7204
SCD01U16V2KX-3GP
2
1

Belong to DIP, not SMT.

CBS_CC/BE0# 32

+CBS_VPP

21.H0164.001

R5531V002-GP

32 CBS_CVS2
32 CBS_CRST#
32 CBS_CSERR#
32 CBS_CREQ#
32 CBS_CC/BE3#
32 CBS_CAUDIO
32 CBS_CSTSCHNG

2
4

CARDBUS-SKT104-GP-U

C7212
SCD01U16V2KX-3GP

32 CBS_CTRDY#
32 CBS_CFRAME#

CBS_CAD0
CBS_CAD1
CBS_CAD3
CBS_CAD5
CBS_CAD7
CBS_CC/BE0#
CBS_CAD9
CBS_CAD11
CBS_CAD12
CBS_CAD14
CBS_CC/BE1#
CBS_CPAR
CBS_CPERR#
CBS_CGNT#
CBS_CINT#

+CBS_VCC
+CBS_VPP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

32 CBS_DATA18
32 CBS_CBLOCK#
32 CBS_CSTOP#
32 CBS_CDEVSEL#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

C7211
SCD1U10V2KX-4GP

32 CBS_CVS1

PCC

NP1
NP2

32 CBS_DATA14

78
79
80
81
82
83
84

32 CBS_CCD1#

CBS_CAD13, CBS_CAD15 Can be used


as Express Card USB differential pair.

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

NP1
NP2

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
CBS_CTRDY#
53
CBS_CFRAME#
54
CBS_CAD17
55
CBS_CAD19
56
CBS_CVS2
57
CBS_CRST#
58
CBS_CSERR#
59
CBS_CREQ#
60
CBS_CC/BE3#
61
CBS_CAUDIO
62
CBS_CSTSCHNG 63
CBS_CAD28
64
CBS_CAD30
65
CBS_CAD31
66
CBS_CCD2#
67
68
CBS_CCD1#
CBS_CAD2
CBS_CAD4
CBS_CAD6
CBS_DATA14
CBS_CAD8
CBS_CAD10
CBS_CVS1
CBS_CAD13
CBS_CAD15
CBS_CAD16
CBS_DATA18
CBS_CBLOCK#
CBS_CSTOP#
CBS_CDEVSEL#

DY

69
70
71
72
73
74
75
76
77

CBUS1

Close to Socket

+CBS_VCC

3
1

32

69
70
71
72
73
74
75
76
77

C7203
SC270P50V2JN-2GP

PCC
2

1
2

C7202
SC270P50V2JN-2GP

Cardbus Socket

CBS_CCD2#
CBS_CAD[0..31]

PCC

Cardbus Connector

78
79
80
81
82
83
84

CBS_CCD1#

VCC3EN#
VCC5EN#

VCC3EN#
VCC5EN#

32
32

+CBS_VCC Short Current Limit, 1400mA


+CBS_VPP Short Current Limit, 300mA
-1.10/0303

SSID = ExpressCard

+3.3V_ALW

+1.5V_RUN_CPU +3.3V_RUN

+3.3V_RUN

RN7201

1
2

NewCard Connector

DY

CPUSB#
CPPE#

4
3

+3.3V_ALW
+1.5V_RUN_CPU

U7202

SRN100KJ-6-GP

NewCard Socket

+3.3V_CARD

2
3

+1.5V_CARD

12
11

3_3VIN EXP
3_3VOUT
1_5VIN
1_5VOUT

NC#4
NC#5
NC#13
NC#14
NC#16

4
5
13
14
16

+3.3V_CARD
+1.5V_CARD

AUXOUT
AUXIN

15
17

+3.3V_CARDAUX

RCLKEN

18

GND
GND

7
21

NEW 1

DY

EXPRCRD_STDBY#_R 1
EXPRCRD_RST#
6
PERST#
8
CPUSB#
2 0R2J-2-GP
9
CPPE#
2
10
0R0402-PAD-2-GP
19
20
DY 20R2J-2-GP EXPRCRD_SHDN#

STBY#
SYSRST#
PERST#
CPUSB#
CPPE#
OC#
SHDN#

TPS2231MRGPR-GP

EXPRCRD_CPPE#

C7216
SC4D7U6D3V5KX-3GP

1
2

C7215
SCD1U16V2ZY-2GP

EXP

EXP

C7220
SC10U10V5ZY-1GP

62.10081.321

EXP

+3.3V_CARD

C7217

EXP

+1.5V_CARD Max. 650mA, Average 500mA.


+3.3V_CARD Max. 1300mA, Average 1000mA
+3.3V_CARDAUX Max. 275mA

EXP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

Place them near to NEW1

Place them near to U7202


4

EXP
2

EXPRESSCARD-26P-14-GP

+1.5V_CARD

C7221
SCD1U16V2ZY-2GP

+3.3V_CARDAUX

USBP12+ 21,32,34
USBP12- 21,32,34

EXP

3
4

SRN0J-6-GP

C7214

DY

+3.3V_RUN

C7213

C7218
SC10U10V5ZY-1GP

RN7202

EXP

+1.5V_RUN_CPU

EXP

CARD_SMBDAT 37
CARD_SMBCLK 37

2
1

+3.3V_ALW

SCD1U16V2ZY-2GP
2
1

+1.5V_CARD

+3.3V_CARDAUX

PCIE_W AKE# 35,38,64

CPUSB#
USBP12+_R
USBP12-_R

22,38,50 SIO_SLP_S4#

+3.3V_CARD

EXPCLK_REQ# 23

DY 2K2R2J-2-GP

2 0R2J-2-GP
2 R7206
0R0402-PAD-2-GP

38 EXPRCRD_PW REN#

R7211
10KR2J-3-GP

1
R7205

DY

C7219
SCD1U16V2ZY-2GP

CLK_PCIE_EXP 23
CLK_PCIE_EXP# 23

1
27

DY
2

C7225
SCD1U16V2ZY-2GP

EXP

C7224
SC10U10V5ZY-1GP

+1.5V_CARD

R7208 1
1
R7209

1
R7210

PERST#
PCIE_W AKE#

DY

DY

R7204
2K2R2J-2-GP

PCIE_PRX_EXPTX_P4 23
PCIE_PRX_EXPTX_N4 23

EXPRCRD_CPPE#

C7226 DY
SC22P50V2JN-4GP

+3.3V_RUN

SCD1U16V2ZY-2GP
2
1

EXP

DY
2

EXP

C7222
SC10U10V5ZY-1GP

C7223
SCD1U16V2ZY-2GP

+3.3V_CARD

21,32,34,58 PLTRST2#
PCIE_PTX_EXPRX_P4_C 23
PCIE_PTX_EXPRX_N4_C 23

SCD1U16V2ZY-2GP
2
1

21.I0036.001
Belong to DIP, not SMT.

28
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

R7207 1
1

CARD-PUSH-2P-4-GP-U

38 EXPRCRD_STDBY#
38,42,51,86 RUN_ON
1
2
R7201
0R0402-PAD-2-GP

NEW 1SKT1
1
DY 2

Date:

PCMCIA / ExpressCard

Document Number

Sheet
1

72

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

of

89

User.interface
Camera Connector
+CAMERA_VDD CCD1

+CAMERA_VDD

R7304
R7305

AUD_DMIC_CLK_G_C
AUD_DMIC_IN0_C

1
1 0R2J-2-GP
33R2J-2-GP

1
11
+3.3V_RUN

+CAMERA_VDD

1
R7306

C7303
SCD1U10V2KX-4GP

30 AUD_DMIC_CLK_G
30 AUD_DMIC_IN0

2
2

CAM_MIC_CBL_DET#
USBP11+_R
USBP11-_R

21 CAM_MIC_CBL_DET#
D

C7302
SC4D7U6D3V3KX-GP
2
1

12
10
9
8
7
6
5
4
3
2

Close to connector

FOX-CON10-GP-U

2
0R0603-PAD-2-GP

20.F0711.010

USBP11+_R

21 USBP11+

EL7301
DLW 21HN900SQ2LGP-U
C

21 USBP11-

User.interface

AFTP7301
AFTP7302
AFTP7303
AFTP7304
AFTP7305
AFTP7306

USBP11-_R

MB BT CONN
Bluetooth Connector

1
1
1
1
1
1

+CAMERA_VDD
USBP11-_R
USBP11+_R
CAM_MIC_CBL_DET#
AUD_DMIC_CLK_G_C
AUD_DMIC_IN0_C

BT Module CONN

PIN

Define

PIN

Define

GND

GND

BT1

12
1

+3.3V_RUN

2
3
4
5
6
7
8
9
10

21 BT_DET#

38 BT_RADIO_DIS#
C7305
SC100P50V2JN-3GP DY

C7304
SCD1U10V2KX-4GP

1
2

C7301
SC2D2U6D3V3KX-GP
2
1

64 COEX1_BT_ACTIVE
64 COEX2_W LAN_ACTIVE

BT_RADIO_DIS#
BT_LED
+3.3V_RUN

12

USB_DP

USBP5-_R

11

USB_DN
B

GND

10

GND

BT_DET#

MOD_DET

BT_RADIO_DIS#

RADIO_DIS

COEX1_BT_ACTIVE

COEX1_BT_ACTIVE

+5V_RUN

COEX2_WLAN_ACTIVE

COEX2_WLAN_ACT

11

21.D0214.110

R7310
100KR2J-1-GPDY

+3.3V_RUN

10

LINK_IND

3.3V

+3.3V_RUN
COEX1_BT_ACTIVE
COEX2_W LAN_ACTIVE
USBP5+
USBP5BT_RADIO_DIS#
BT_LED
BT_DET#

BT_LED

BT_ACTIVE_K# 66

1
1
1
1
1
1
1
1

USBP5+_R

JST-CON10-12-GP

Close to CONN Pin.4

AFTP7307
AFTP7308
AFTP7309
AFTP7310
AFTP7311
AFTP7312
AFTP7313
AFTP7314

21 USBP5+
21 USBP5-

<Core Design>

Q7303
2N7002A-7-GP

Wistron Corporation

1 R7302 2BT_LED_C
0R0402-PAD-2-GP

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:

Bluetooth / Camera / DMIC

Document Number

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

73

Rev

-1
of

89

+DOCK_PWR_BAR

SSID = Docking

145
160

Dock

Clost to DK1

C7402
SCD1U50V3KX-GP

D7401

2
147

2
2

C7407
C7408

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPB_LANE_1P_GPU_R
DPB_LANE_1N_GPU_R

81 DPB_LANE_2P_GPU
81 DPB_LANE_2N_GPU

1
Dock
1
Dock

2
2

C7409
C7410

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPB_LANE_2P_GPU_R
DPB_LANE_2N_GPU_R

81 DPB_LANE_3P_GPU
81 DPB_LANE_3N_GPU

1
Dock
1
Dock

2
2

C7411
C7412

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPB_LANE_3P_GPU_R
DPB_LANE_3N_GPU_R
DPB_DOCK_AUX_SW
DPB_DOCK_AUX_SW#
DPB_DOCK_HPD

81 DPB_DOCK_HPD
+NBDOCK_DC_IN_SS

75 BLUE_DOCK

DPC_LANE_0P_GPU_R
DPC_LANE_0N_GPU_R

1
Dock
1
Dock

2
2

C7404
C7406

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPC_LANE_1P_GPU_R
DPC_LANE_1N_GPU_R

1
Dock
1
Dock

2
2

C7413
C7414

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPC_LANE_2P_GPU_R
DPC_LANE_2N_GPU_R

1
Dock
1
Dock

2
2

C7415
C7416

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPC_LANE_3P_GPU_R
DPC_LANE_3N_GPU_R

1
Dock
1
Dock

2
2

C7401
C7417

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPC_LANE_0P_GPU
DPC_LANE_0N_GPU

DPB_DOCK_AUX_SW
DPB_DOCK_AUX_SW#

81
81

DPC_LANE_1P_GPU
DPC_LANE_1N_GPU

81
81

DPC_LANE_2P_GPU
DPC_LANE_2N_GPU

81
81

DPC_LANE_3P_GPU
DPC_LANE_3N_GPU

81
81

DPB_DOCK_CA_DET
DPB_DOCK_HPD

DPC_DOCK_HPD

ACAV_DOCK_SRC#

DOCK_LOM_TRD0+
DOCK_LOM_TRD0DOCK_LOM_TRD1+
DOCK_LOM_TRD1DOCK_LOM_TRD2+
DOCK_LOM_TRD2DOCK_LOM_TRD3+
DOCK_LOM_TRD3-

81

44

DAT_DDC2_DOCK
CLK_DDC2_DOCK

75
75

156

DY

37

R7416
910KR2J-GP

157

Dock

C7420
SCD1U50V3KX-GP

Dock

DPC_DOCK_AUX_SW#

Q7406
DMN66D0LDW-7-GP

4DPC_DOCK_AUX_SW
3DPC_DOCK_AUX_SW#

Q7405
DMN66D0LDW-7-GP

Dock

DPC_DOCK_AUX_SW#_R

Dock

<Core Design>

Wistron Corporation

DPC_DOCK_AUX#

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

DPB_DOCK_AUX#

Dock

SRN10KJ-5-GP

DPC_DOCK_AUX
DPC_DOCK_EN_DET

R7433
1MR2J-1-GP

SRN10KJ-5-GP

1
2

DPC_DOCK_CA_DET

DPB_DOCK_AUX_SW
DPB_DOCK_AUX_SW#

RN7401
DPC_DOCK_AUX_SW_R

2
4

R7432

100KR2J-1-GP
Dock

Dock
3

6
1

4
3

+3.3V_DELAY
Q7407
DMN66D0LDW-7-GP

DPB_DOCK_AUX_SW#_R

DPC_DOCK_AUX# 1Dock2DPC_DOCK_AUX_SW#
C7439
SCD1U10V2KX-4GP

DPC_DOCK_AUX_SW

Dock

Dock
1

Q7404
DMN66D0LDW-7-GP

1
2

Q7402
DMN66D0LDW-7-GP

Dock

DPB_DOCK_AUX_SW#

R7429
1MR2J-1-GP

Dock

DPB_DOCK_AUX
DPB_DOCK_EN_DET

81 DPC_DOCK_AUX#

+15V_ALW

DPB_DOCK_CA_DET

DPB_DOCK_AUX_SW_R

Dock100KR2J-1-GP

RN7404

R7428

Dock

Dock
S G D

+3.3V_DELAY

S G D

DPC_DOCK_AUX
1Dock2DPC_DOCK_AUX_SW
C7444
SCD1U10V2KX-4GP

R7430

Q7408
DMN66D0LDW-7-GP

Dock

81 DPC_DOCK_AUX

DOCK_DET# 38,44,75

D G S

DPB_DOCK_AUX_SW

Q7403
DMN66D0LDW-7-GP

DPB_DOCK_AUX# 1Dock2DPB_DOCK_AUX_SW#
C7440
SCD1U10V2KX-4GP

SDMK0340L-7-F-GP

+15V_ALW

Dock

C7441
SCD1U25V3KX-GP

4
1

Dock

81 DPB_DOCK_AUX#

Dock

+3.3V_DELAY

DPB_DOCK_EN_DET#

Q7401
DMN66D0LDW-7-GP

DPB_DOCK_AUX
1Dock2DPB_DOCK_AUX_SW
C7443
SCD1U10V2KX-4GP

DY

Dock

to DOCK

81 DPB_DOCK_AUX

DPC_DOCK_EN_DET#

20.F1572.144
D G S

R7412
100KR2J-1-GP

Dock10KR2F-2-GP

JAE-CONN144D-3-GP-U

Dock10KR2F-2-GP

R7410
100KR2J-1-GP

D7403

+DOCK_PWR_BAR

150

+3.3V_ALW

From GPU

DY

152

1
R7431

DOCK_POR_RST#

45
45

+3.3V_DELAY

DOCK_DCIN_IS+
DOCK_DCIN_IS-

151

D7404
PESD24VS2UT-GP

+RTC_CELL

DOCK_LOM_TRD3+ 35
DOCK_LOM_TRD3- 35

38 SLICE_BAT_PRES#
+DOCK_PWR_BAR

2
2SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

37 DOCK_PWR_BTN#

DY SC4D7P50V2CN-1GP

1DY
1DY

37 DOCK_SMB_ALERT#
43 DOCK_PSID

EC7401

C7438
C7421
DOCK_LOM_TRD2+ 35
DOCK_LOM_TRD2- 35

1 2

37 DOCK_SMB_CLK
37 DOCK_SMB_DAT

DOCK_LOM_TRD1+ 35
DOCK_LOM_TRD1- 35

R7408
10R2F-L-GP

DY

Fonseca 14.1" DIS

Size
Document Number
Custom

Fonseca 14.1" DIS

Date:
5

DY

35

21 CLK_PCI_DOCK

BREATH_LED# 37,66
DOCK_LOM_ACTLED_YEL#

CLK_PCI_DOCK

DY

DOCK_LOM_TRD0+ 35
DOCK_LOM_TRD0- 35

38 D_SERIRQ
38 D_DLDRQ1#

96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

38 D_LFRAME#
38 D_CLKRUN#

DY

158

163
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
NP2
164
149

D_LAD2
D_LAD3

DY

38
38

----->Dock_2

C7442
SCD1U25V3KX-GP

D_LAD0
D_LAD1

DY

CLK_KBD 37
DAT_KBD 37

38
38

----->Dock_1

USBP9+ 21
USBP9- 21

155

DY

SATA_PTX_DRX_5+ 24
SATA_PTX_DRX_5- 24
USBP8+ 21
USBP8- 21

75 DAI_DI
75 DAI_DO#
75 DAI_12MHZ#

SATA_PRX_DTX_5+ 24
SATA_PRX_DTX_5- 24

75 DAI_BCLK#
75 DAI_LRCK#

Dock

1Dock2 C7427
1Dock2 C7424

DY

37 CLK_MSE
37 DAT_MSE

Dock eSATA
SATA_PRX_DTX_5+_C SCD01U50V2KX-1GP
SATA_PRX_DTX_5-_C SCD01U50V2KX-1GP

55 HSYNC_DOCK
55 VSYNC_DOCK

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94

75 GREEN_DOCK

162
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93

75 RED_DOCK

+5V_RUN

DPB_DOCK_CA_DET
DPB_DOCK_HPD

IP4280CZ10-GP

DPC_DOCK_AUX_SW
DPC_DOCK_AUX_SW#
DPC_DOCK_HPD

DYTMDS_D2+
NC#10
TMDS_D2NC#2
TMDS_GND TMDS_VDD
NC#7
TMDS_D1+
TMDS_D1NC#5

10
9
8
7
6

DY

159

DPB_DOCK_AUX_SW
DPB_DOCK_AUX_SW#

IP4280CZ10-GP

35

D7402

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

154

1
2
3
4
5

+5V_RUN

DPC_DOCK_CA_DET
DPC_DOCK_HPD

C7422
SC4D7P50V2CN-1GP
2
1

81 DPB_LANE_1P_GPU
81 DPB_LANE_1N_GPU

1
Dock
1
Dock

DOCK_LOM_SPD100LED_ORG#

DPC_DOCK_CA_DET

DPC_DOCK_AUX_SW
DPC_DOCK_AUX_SW#

C7419
SC4D7P50V2CN-1GP
2
1

DPB_LANE_0P_GPU_R
DPB_LANE_0N_GPU_R

44

1
2
3
4
5

C7432
SC4D7P50V2CN-1GP
2
1

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

DPC_DOCK_CA_DET
DPC_DOCK_HPD

C7423
SC4D7P50V2CN-1GP
2
1

81 DPB_LANE_0P_GPU
81 DPB_LANE_0N_GPU

C7403
C7405

DOCK_AC_OFF

DYTMDS_D2+
NC#10
TMDS_D2NC#2
TMDS_GND TMDS_VDD
NC#7
TMDS_D1+
TMDS_D1NC#5

10
9
8
7
6

C7435
SC4D7P50V2CN-1GP
2
1

2
2

2
161
4
6
8

3
5
7
NP1
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

DPB_DOCK_CA_DET

1
Dock
1
Dock

DPC_DOCK_AUX_SW
DPC_DOCK_AUX_SW#

+DOCK_PWR_BAR

C7437
SC4D7P50V2CN-1GP
2
1

35 DOCK_LOM_SPD10LED_GRN#

146

C7431
SC4D7P50V2CN-1GP
2
1

+DOCK_PWR_BAR

148

C7426
SC4D7P50V2CN-1GP
2
1

153

DK1

Thursday, March 18, 2010

Sheet
1

74

of

Rev

-1
89

VCC

CRT_HSYNC_GPU

SC1U10V2KX-1GP

DVDD

IOVDD

I2S_BCLK
I2S_DI#
CLK_12M_R

2
4
1

BCLK
DIN
MCLK

AUD_DOCK_HP_OUT_L_C
AUD_DOCK_HP_OUT_R_C

10
12

LINEL
LINER
RESET#

+3.3V_RUN_IOVDD

30 AUD_DOCK_HP_OUT_L_C
30 AUD_DOCK_HP_OUT_R_C
+5V_RUN

1 R7501 2
0R0603-PAD-2-GP

SCD1U10V2KX-4GP
2
1

1
2

32

C7511

Dock DockSCD1U10V2KX-4GP

81,83

C7514
SCD1U10V2KX-4GP

5
27
29

NC#20
NC#19
NC#22
NC#23
NC#28
NC#11
NC#13
NC#14
NC#16
NC#15
NC#30

20
19
22
23
28
11
13
14
16
15
30

Dock

DOCK_AUD_RST#

31

AUD_DOCK_SMB_CLK

SCL

AVSS
AVSS

17
26

AUD_DOCK_SMB_DAT

SDA

DRVSS

21

WCLK

C7513

I2S_LRCLK

CRT_MUX_SWITCH

GREEN_CRT

+3.3V_RUN

MB

1
2
3
4

VCONT
GND
DY
OUTPUT
VDD

GPAD

33

I2S_DO
AUD_DOCK_MIC_IN_L_C
AUD_DOCK_MIC_IN_R_C

Dock

U7505

1
2

Dock

DY

SCD1U10V2KX-4GP

Dock

AUD_DOCK_SMBDAT 37

5
4

DMN66D0LDW -7-GP
AUD_DOCK_SMBCLK

+3.3V_RUN

11

CLK

GND

TSLVC74APW R-1GP

10
PR

CLK_FD_12M

DY 20R2J-2-GP
R7523
CLK_12M
1
2
0R0402-PAD-2-GP

D7504

D7501

D7503

D7502

DY

DY

DY

BAV99-4-GP

BAV99-4-GP BAV99-4-GP

BAV99-4-GP

2N7002A-7-GP

+3.3V_RUN

U7507

U7402C

DAI_DI

U7402B

DY

DAI_DI_1

TSAHC14PW -GP

U7402D

DY

C7501
SCD1U10V2KX-4GP
I2S_BCLK
Dock
I2S_LRCLK
I2S_DO
I2S_12MHZ
DAI_DI_R

8
38 EN_I2S_NB_CODEC#

TSAHC14PW -GP

VCC

2
4
6
10
12
14

1A
2A
3A
4A
5A
6A

1
15

OE1#
OE2#

1
14

DY

DY

C7521
SCD1U10V2KX-4GP

16

1 R7529 2 DAI_OE2#
0R0402-PAD-2-GP

1Y#/1Y
2Y#/2Y
3Y#/3Y
4Y#/4Y
5Y#/5Y
6Y#/6Y

DAI_BCLK#_R
1
DAI_LRCK#_R R7513 1
DAI_DO#_R
R7514 1
R7515
I2S_DI#

GND

Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3

DAI_BCLK# 74
DAI_LRCK# 74
DAI_DO# 74
DAI_12MHZ# 74

<Core Design>

1 R7516 2
0R0402-PAD-2-GP

2
2 0R0402-PAD-2-GP
2 0R0402-PAD-2-GP
0R0402-PAD-2-GP

Dock

74HC366D-GP

TSAHC14PW -GP

3
5
7
9
11
13

Date:
5

+3.3V_RUN

DY

+3.3V_RUN

3
14

DY

TSAHC14PW -GP

CLK_12M_R
I2S_12MHZ

3
4

TSLVC74APW R-1GP

14

1
74

Dock

RN7502
SRN33J-5-GP-U

D7505
BAV99-4-GP

U7402A

2
1

Dock

13

GND

CLK

CLK_FD_24M

VCC
D

CL

4
PR

Dock

2
5

14
12

Frequency Divider (12M Output)

+3.3V_RUN

DOCK_MIC_DET 38

14

OSC_12MHZ 1
R7522

Dock

1
Q7501
DMN66D0LDW -7-GP

DOCK_HP_DET_R#

U7504B

Q7502
38,44,74 DOCK_DET#

DY

VCC
D

D
DOCK_HP_DET 38

14
2

CL

1
2

DOCK_MIC_DET_R#

Dock

U7504A

37

AUD_DOCK_SMB_CLK

AUD_DOCK_FD_CLR#

R7528
Dock39K2R2F-L-GP

AUD_DOCK_FD_LOOP2

R7521

Dock
100KR2J-1-GP

23 CLK_FD_48M

AUD_SENSE_B 30

C7519

Dock
SCD1U10V2KX-4GP

1
2

2
1
2

C7520
R7527
Dock
SC1KP50V2KX-1GPDock20KR2F-L-GP

SC1U6D3V2KX-GP

C7518

Dock

R7526
Dock2K49R2F-GP

AUD_DOCK_FD_LOOP1

Place this block


close to Audio Codec Pin14

AUD_SENSE_B

30
30

2
1

SRN2K2J-1-GP
AUD_DOCK_SMB_DAT

OSC_12MHZ

OSC-12MHZ-1-GP

DVSS

C7517

+VDDA

C7508

RN7501

3
4

CRT display

0
1

CRT_GREEN_GPU

81 CRT_GREEN_GPU

C7507

Dock Dock

+3.3V_RUN
OSC7501

55 GREEN_CRT

C7506

TLV320AIC3004IRHBR-GP

GREEN_DOCK

74 GREEN_DOCK

C7505

Dock Dock

DOUT
LEFT_LO
RIGHT_LO

CRT_RED_GPU

81 CRT_RED_GPU

C7504

Dock

SCD1U10V2KX-4GP

RED_CRT

55 RED_CRT

DRVDD
DRVDD

+3.3V_DELAY

B2
B1
B0

RED_DOCK

74 RED_DOCK

SC4D7U6D3V3KX-GP
2
1

2
1
9

AVDD

18
24

+1.8V_RUN

1 Dock
2
BLM18EG601SN1D-GP

C7512
CRT_HSYNC_GPU

25

VL

55

R2
R1
R0

CRT_SW ITCH_HSYNC

L7501

Close to Pin.25

U7502
+3.3V_RUN_I2S_VDD

17
18
3

DOCK_AUD_RST#

81,83

11
6

CRT_SW ITCH_HSYNC

21
22
1

H1
H0

CRT_BLUE_GPU

81 CRT_BLUE_GPU

SEL
EN

G2
G1
G0

74 BLUE_DOCK
55 BLUE_CRT

MAX4885EETG-GP

24
23

15
16
4

SCD1U10V2KX-4GP

DY

V1
V0

CRT_VSYNC_GPU

55

+3.3V_RUN

5V_CRT_RUN

SC1U10V2KX-1GP

C7522 C7510

CRT_SW ITCH_VSYNC

CRT_VSYNC_GPU

GND
GND

+3.3V_DELAY
38 CRT_SW ITCH

CRT_SW ITCH_VSYNC

12
7

2
DY 33R2J-2-GP

C7509
DockSCD1U10V2KX-4GP

U7501

SDA2
SDA1
SDA0

19
20
2
SCL2
SCL1
SCL0
25
10

1
R7506

24,30 PCH_AZ_CODEC_RST#

CLK_DDC2_CRT
CLK_DDC2_DOCK

55 CLK_DDC2_CRT
74 CLK_DDC2_DOCK

13
14
5

C7503

DY Dock

R7503
100KR2J-1-GP

Dock

Close to Pin.18
+3.3V_RUN_I2S_VDD

C7502

GPU_CLK_DDC

81 GPU_CLK_DDC

Close to Pin.24

L7502
1 Dock
2
BLM18EG601SN1D-GP

+3.3V_RUN

GPU_DAT_DDC
DAT_DDC2_CRT
DAT_DDC2_DOCK

81 GPU_DAT_DDC
55 DAT_DDC2_CRT
74 DAT_DDC2_DOCK

+3.3V_RUN

SCD1U10V2KX-4GP
2
1

SSID = DOCK AUDIO

SCD1U10V2KX-4GP
2
1

SSID = DOCK CRT SWITCH

SCD1U10V2KX-4GP
2
1

SCD1U10V2KX-4GP
2
1

SCD1U10V2KX-4GP
2
1

Document Number

Docking IC / SW

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

75

of

89

SSID = User.Interface

C7604
SCD1U10V2KX-4GP

+3.3V_RUN_W W AN

C7605
SCD1U10V2KX-4GP

C7603
SCD1U10V2KX-4GP

+3.3V_SUS

+3.3V_LAN

C7602
SCD1U10V2KX-4GP

C7601
SCD1U10V2KX-4GP

+1.5V_RUN_CPU

+5V_ALW

Place near BTB1

IO Board Connector
BTB1

66 BREATH_PW RLED_B
25 USB_MCARD2_DET#
21 PCIE_MCARD2_DET#

38 MDC_RST_DIS#
38 W W AN_RADIO_DIS#
38,63 USB_SIDE_EN#
21 USB_OC#2_3

21 USBP1321 USBP13+
23 CLK_PCIE_MINI2#
23 CLK_PCIE_MINI2
23 PCIE_PRX_W W ANTX_N1
23 PCIE_PRX_W W ANTX_P1
B

23 PCIE_PTX_W W ANRX_N1_C
23 PCIE_PTX_W W ANRX_P1_C
24 PCH_AZ_MDC_BITCLK
24 PCH_MDC_SDOUT
24 PCH_AZ_MDC_RST#
24 PCH_MDC_SDIN1
24 PCH_AZ_MDC_SYNC

84
85
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2

86
NP2
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

1
82
81

80
NP1
83

+3.3V_SUS
PW R_BTN_BD_DET# 38

POW ER_SW #_MB 37


+3.3V_RUN_W W AN
+5V_ALW

+1.5V_RUN_CPU
NB_LOM_SPD10LED_GRN#_R
NB_LOM_ACTLED_YEL#_R

35

+3.3V_LAN

35

NB_LOM_SPD100LED_ORG#_R
LED_W W AN_OUT# 66
PLTRST4# 21,35,64
MINI2CLK_REQ# 23

35

NB_LOM_TRD0+ 35
NB_LOM_TRD0- 35
NB_LOM_TRD1+ 35
NB_LOM_TRD1- 35
NB_LOM_TRD2+ 35
NB_LOM_TRD2- 35

NB_LOM_TRD3+ 35
NB_LOM_TRD3- 35
USBP3- 21
USBP3+ 21
USBP2- 21
USBP2+ 21

TYCO-CONN80E-GP

20.F1612.080

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Document Number

IO Board CONN

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

76

of

89

SSID = User.interface
D

LED BD Connector
LEDB1
13
AFTP7702
66 BAT1_LED_AMBER_B
66 BAT2_LED_BLUE_B

BT_LED_B

66 BT_LED_B

LED_WLAN_OUT_B

66 LED_WLAN_OUT_B

BAT1_LED_AMBER_B
BAT2_LED_BLUE_B

HDD_LED_B

66 HDD_LED_B

LED_BD_DET#

25 LED_BD_DET#

1
2
3
4
5
6
7
8
9
10
11
12

*Pin12 for Daughter Board DET


*Daughter Board Pin12 connect to Pin1
C

14

Main:20.K0227.012

MLX-CON12-11GP

2nd:20.K0230.012

20.K0227.012

AFTP7701
AFTP7703

1
1

BAT1_LED_AMBER_B
BAT2_LED_BLUE_B

AFTP7704
AFTP7705

1
1

BT_LED_B
LED_WLAN_OUT_B

AFTP7706
AFTP7707

1
1

HDD_LED_B
LED_BD_DET#

LED Location from left to right


HDD

BATTERY

WLAN

BLUE TOOTH

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

LED Board Connector

Size
A4

Document Number

Date: Thursday, March 18, 2010


5

Rev

-1

Fonseca 14.1" DIS


2

Sheet

77

of
1

89

SSID = User.Interface
D

AFTP7802
AFTP7803
AFTP7804
AFTP7805

1
1
1
1

+3.3V_RUN
Biometric_USBPBiometric_USBP+
BIO_DET#

+3.3V_RUN

21 USBP1021 USBP10+

R7801
0R0603-PAD-2-GP
1
2
1
2
0R0603-PAD-2-GP
R7802

-1.10/0310

C7801
SCD1U10V2KX-4GP

FP1

1
Biometric_USBPBiometric_USBP+
AFTP7801
25 BIO_DET#

2
3
4
5
6
8

Main:20.K0227.006

MLX-CON6-11-GP

20.K0227.006

2nd:20.K0230.006

Biometric Connector
B

<Core Design>

Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

Finger Printer Board CONN

Size
A4

Document Number

Date: Thursday, March 18, 2010


5

Sheet

78

of
1

Rev

-1

Fonseca 14.1" DIS

89

Hole

34.4F822.002

SPR5

SPR6

34.45T31.001

34.45T31.001

14

14

DY

10

13

TSAHC14PW -GP

SPRING-24-GP-U

SPRING-24-GP-U

SPRING-24-GP-U

SPRING-24-GP-U

34.45T31.001

12

11

U5501C
SSAHCT125PW R-GP

7
2

SCD1U50V3KX-GP

EC7908
U5501D
SSAHCT125PW R-GP

EC7910

DY

EC7911

EC7909

DY

TSAHC14PW -GP

+PW R_SRC

SCD1U50V3KX-GP

1
2

+PW R_SRC

SCD1U50V3KX-GP

SCD1U10V2KX-4GP

H27
HOLE

+COIN_CELL

SCD1U50V3KX-GP

ZZ.00PAD.I71 ZZ.00PAD.I71 ZZ.00PAD.I71 ZZ.00PAD.I71 ZZ.00PAD.I71 ZZ.00PAD.I71

DY
2

SCD1U50V3KX-GP

9
EC7907

14

+PW R_SRC

H17
HOLE
EC7906

12

+5V_CRT_RUN

10

14

+PW R_SRC

DY

34.45T31.001

EMI CAPS

HOLE355X355R126-GP

34.4F822.002

U7402F

SPR7

+5V_CRT_RUN

H16

H15
HOLE355X355R126-GP

H14
HOLE355X355R126-GP

H13
HOLE355X355R126-GP

HOLE355X355R126-GP

HOLE355X355R126-GP

H12

SPRING-51-GP

34.4F822.002

ZZ.00PAD.M01

HT65B85X925R29-S-GP

H10

SPRING-51-GP

34.4Y702.001

SPRING-51-GP

ZZ.00PAD.J11

+DC_IN
H11

SPR4

SPR3

13

SPR2

11

HOLET256B315R111-GP

ZZ.00PAD.J01

+3.3V_RUN

1
1

U7402E
SPR1

H9

HOLE256R126-GP

ZZ.00PAD.I51

+3.3V_RUN

SPRING

HOLE296R166-GP

ZZ.00PAD.J11
H8

ZZ.00PAD.I51

BOSS1
STF217R128H83-GP

H4

HOLE296R166-GP

ZZ.00PAD.J11
H7

HTE10BE10R32-D-55-GP

HTE10BE10R32-D-55-GP

H6

H3

HOLE296R166-GP

HOLE296R166-GP

H2

ZZ.00PAD.J11

Unused

SSID = Mechanical
H1

-1.10/0317

1
ZZ.00PAD.I61

RF

EC7916

SC33P50V2JN-3GP
2
1

EC7924

DY

EC7925

DY

<Core Design>

+1.5V_SUS

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

EC7921

DY
Title
Size
Date:

+1.5V_RUN

EC7922

A3
5

EC7927

DY

+1.5V_RUN

SC33P50V2JN-3GP
2
1

SC33P50V2JN-3GP
2
1

SCD1U50V3KX-GP
2
1

EC7923

EC7920

+1.5V_RUN

+1.05V_VTT_PW R_SRC

DY

SCD1U50V3KX-GP

DY
2

EC7919

+PW R_SRC_GFX_CORE

SCD1U50V3KX-GP
2
1

EC7915

+1.5V_SUS

SCD1U50V3KX-GP

DY

EC7914

DY

+5V_ALW

DY

+1.5V_SUS

SC33P50V2JN-3GP
2
1

DY

SC33P50V2JN-3GP
2
1

SC33P50V2JN-3GP
2
1

EC7903

DY

+5V_ALW

EC7913

SC33P50V2JN-3GP
2
1

SC33P50V2JN-3GP
2
1

EC7912

+5V_ALW

EC7918

+PW R_SRC

+1.5V_RUN

EC7917

EC7902

DY

+5V_ALW

DY

SCD1U50V3KX-GP

SCD1U50V3KX-GP

ZZ.00PAD.M61

+PW R_SRC
ZZ.00PAD.M51

SC33P50V2JN-3GP

EC7901

DY

SCD1U50V3KX-GP

EC7905

+1.5V_RUN

SC33P50V2JN-3GP

H26
HTE54B5R28-D-42-GP

1
2

H22
HT65X75B62X56R28-2P-S-GP

+1.5V_RUN

DY

ZZ.00PAD.I81

+5V_ALW

SC33P50V2JN-3GP

ZZ.00PAD.I81

EC7904

DY
2

SC33P50V2JN-3GP

1
ZZ.00PAD.J71

+1.5V_RUN

+VCC_GFX_CORE

H25
HOLE197R91-GP

H24
HOLE197R91-GP

SC33P50V2JN-3GP

ZZ.00PAD.I61

H23
HOLE197R99-1-GP

ZZ.00PAD.S31

ZZ.00PAD.S31

H21

HOLE300X166R111-GP

H20

HOLE300X166R111-GP

H19
HOLE78X42R54X34-S-GP

H18
HOLE78X42R54X34-S-GP

Unused Parts / EMI RF Cap.

Document Number

Sheet
1

79

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

of

89

1 OF 7

U8001A

PEG_CTX_GRX_P[0..15]
PEG_CTX_GRX_N[0..15]

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

AH30 PEG_CRX_GTX_R_P0
AG31 PEG_CRX_GTX_R_N0

C8002 1
1
C8003

2 SCD1U16V2KX-3GP PEG_CRX_GTX_P0
PEG_CRX_GTX_N0
2
SCD1U16V2KX-3GP

PEG_CTX_GRX_P1
PEG_CTX_GRX_N1

AE29
AD28

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

AG29 PEG_CRX_GTX_R_P1
AF28 PEG_CRX_GTX_R_N1

C8005 1
1
C8004

2 SCD1U16V2KX-3GP PEG_CRX_GTX_P1
PEG_CRX_GTX_N1
2
SCD1U16V2KX-3GP

PEG_CTX_GRX_P2
PEG_CTX_GRX_N2

AD30
AC31

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

AF27 PEG_CRX_GTX_R_P2
AF26 PEG_CRX_GTX_R_N2

C8006 1
1
C8007

2 SCD1U16V2KX-3GP PEG_CRX_GTX_P2
PEG_CRX_GTX_N2
2
SCD1U16V2KX-3GP

PEG_CTX_GRX_P3
PEG_CTX_GRX_N3

AC29
AB28

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

AD27 PEG_CRX_GTX_R_P3
AD26 PEG_CRX_GTX_R_N3

C8009 1
1
C8008

2 SCD1U16V2KX-3GP PEG_CRX_GTX_P3
PEG_CRX_GTX_N3
2
SCD1U16V2KX-3GP

PEG_CTX_GRX_P4
PEG_CTX_GRX_N4

AB30
AA31

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

AC25 PEG_CRX_GTX_R_P4
AB25 PEG_CRX_GTX_R_N4

C8010 1
1
C8011

2 SCD1U16V2KX-3GP PEG_CRX_GTX_P4
PEG_CRX_GTX_N4
2
SCD1U16V2KX-3GP

PEG_CTX_GRX_P5
PEG_CTX_GRX_N5

AA29
Y28

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

Y23
Y24

PEG_CRX_GTX_R_P5
PEG_CRX_GTX_R_N5

C8001 1
1
C8012

2 SCD1U16V2KX-3GP PEG_CRX_GTX_P5
PEG_CRX_GTX_N5
2
SCD1U16V2KX-3GP

PEG_CTX_GRX_P6
PEG_CTX_GRX_N6

Y30
W 31

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

AB27
AB26

PEG_CRX_GTX_R_P6
PEG_CRX_GTX_R_N6

C8013 1
1
C8014

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P6
PEG_CRX_GTX_N6

PEG_CTX_GRX_P7
PEG_CTX_GRX_N7

W 29
V28

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

Y27
Y26

PEG_CRX_GTX_R_P7
PEG_CRX_GTX_R_N7

C8015 1
1
C8016

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P7
PEG_CRX_GTX_N7

PEG_CTX_GRX_P8
PEG_CTX_GRX_N8

V30
U31

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

W 24
W 23

PEG_CRX_GTX_R_P8
PEG_CRX_GTX_R_N8

C8017 1
1
C8018

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P8
PEG_CRX_GTX_N8

PEG_CTX_GRX_P9
PEG_CTX_GRX_N9

U29
T28

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

V27
U26

PEG_CRX_GTX_R_P9
PEG_CRX_GTX_R_N9

C8019 1
1
C8023

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P9
PEG_CRX_GTX_N9

PEG_CTX_GRX_P10
PEG_CTX_GRX_N10

T30
R31

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

U24
U23

PEG_CRX_GTX_R_P10
PEG_CRX_GTX_R_N10

C8020 1
1
C8021

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P10
PEG_CRX_GTX_N10

PEG_CTX_GRX_P11
PEG_CTX_GRX_N11

R29
P28

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

T26
T27

PEG_CRX_GTX_R_P11
PEG_CRX_GTX_R_N11

C8022 1
1
C8024

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P11
PEG_CRX_GTX_N11

PEG_CTX_GRX_P12
PEG_CTX_GRX_N12

P30
N31

PCIE_RX12P
PCIE_RX12N

PCI EXPRESS INTERFACE

AF30
AE31

PCIE_TX12P
PCIE_TX12N

T24
T23

PEG_CRX_GTX_R_P12
PEG_CRX_GTX_R_N12

C8025 1
1
C8026

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P12
PEG_CRX_GTX_N12

C8027 1
1
C8028

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P13
PEG_CRX_GTX_N13

PEG_CTX_GRX_P13
PEG_CTX_GRX_N13

N29
M28

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

P27
P26

PEG_CRX_GTX_R_P13
PEG_CRX_GTX_R_N13

PEG_CTX_GRX_P14
PEG_CTX_GRX_N14

M30
L31

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

P24
P23

PEG_CRX_GTX_R_P14
PEG_CRX_GTX_R_N14

C8029 1
1
C8030

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P14
PEG_CRX_GTX_N14

PEG_CTX_GRX_P15
PEG_CTX_GRX_N15

L29
K30

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

M27
N26

PEG_CRX_GTX_R_P15
PEG_CRX_GTX_R_N15

C8032 1
1
C8031

2 SCD1U16V2KX-3GP
2
SCD1U16V2KX-3GP

PEG_CRX_GTX_P15
PEG_CRX_GTX_N15

PEG_CRX_GTX_P[0..15]
PEG_CRX_GTX_N[0..15]

PEG_CTX_GRX_N[0..15]

PEG_CRX_GTX_P[0..15]

PEG_CRX_GTX_N[0..15]

6 OF 7

U8001F

LVDS CONTROL

VARY_BL
DIGON

AB11
AB12

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AH20
AJ19

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AL21
AK20

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH22
AJ21

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AL23
AK22

TXOUT_U3P
TXOUT_U3N

AK24
AJ23

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AL15
AK14

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AH16
AJ15

LBKLT_CTL_GPU 54
LCDVDD_EN_GPU 38,54

4
3

PEG_CTX_GRX_P0
PEG_CTX_GRX_N0

PEG_CTX_GRX_P[0..15]

RN8001
SRN10KJ-5-GP

1
2

SSID = VIDEO

LVTMDP

CLOCK

CLK_PCIE_GPU
CLK_PCIE_GPU#

23 CLK_PCIE_GPU
23 CLK_PCIE_GPU#

AK30
AK32

PCIE_REFCLKP
PCIE_REFCLKN

L9
N9
N10

NC#L9
NC#N9
NC_PW RGOOD

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
CALIBRATION

1
R8006
9,21,58 PLTRST1#

PARK 2

10KR2J-3-GP

1 R8001 2 PLTRST_DELAY# AL27


0R0402-PAD-2-GP

PCIE_CALRP

Y22

PCIE_CALRP

R8004 1

2 1K27R2F-L-GP

PCIE_CALRN

AA22

PCIE_CALRN

R8005 1

2 2KR2F-3-GP

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
+1.1V_GFX_PCIE

TXOUT_L3P
TXOUT_L3N

PERSTB

CAPs close to eDP Panel Connector

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AL17 eDP_CTX_LRX_GPU_P1 1 DY2C8033 eDP_CTX_LRX_P1
AK16 eDP_CTX_LRX_GPU_N1 1 DY2C8034 eDP_CTX_LRX_N1

eDP_CTX_LRX_P1 54
eDP_CTX_LRX_N1 54

AH18 eDP_CTX_LRX_GPU_P0 1
AJ17 eDP_CTX_LRX_GPU_N0 1

eDP_CTX_LRX_P0 54
eDP_CTX_LRX_N0 54

2C8035 eDP_CTX_LRX_P0
2C8036 eDP_CTX_LRX_N0

SCD1U10V2KX-4GP
SCD1U10V2KX-4GP

AL19
AK18

Cap. place near LCD connector

M92-S2-GP

M92-S2-GP

For Park-S3: the PWRGOOD pin


must need to pull down to GND
For M9X-S2/S3: This PWRGOOD pin
is not connected

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

GPU-PCIE/LVDS(1/4)

Size
Document Number
Custom
Date:
5

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

80

of

89

PARK

SC1U10V3KX-3GP
C8105
2
1

SCD01U16V2KX-3GP
C8103
2
1

83 DVPDATA0

M92/ PARK switch

83 DVPDATA2

DPC_VDD18_1

C8112
SCD1U16V2KX-3GP

C8111
SC1U6D3V2KX-GP
2
1

PARK

PARK

1
2

L8105

C8110
SC10U6D3V5MX-3GP

PARK

PARK

DPC_VSSR_5

DPC_VSSR_1

+1.1V_GFX_PCIE

PARK

DPC_VSSR_2

DPC_VDD18_2

R8117
0R2J-2-GP

DPC_VDD18_1
DPC_PVDD

DPC_VDD10_1
DPC_VDD10_1

2
1

PARK 2 DPC_VDD10_2
83 DVPDATA19
AFTP8101
83 DVPDATA21

R8119
0R2J-2-GP

DVPDATA_20

DPC_VDD18_2

R8120
4K7R2F-GP

DY

DY
2

+3.3V_DELAY

PARK

PARK

C8115
SCD1U16V2KX-3GP

PARK

BLM15BD121SS1D-GP

C8114
SC1U6D3V2KX-GP
2
1

DPC_VDD10_2

DY

L8104
BLM15BD121SS1D-GP

C8113
SC10U6D3V5MX-3GP

SC10U6D3V5KX-1GP
C8102
2
1

SC10U6D3V5KX-1GP
C8108
2
1

SCD1U16V2KX-3GP
C8109
2
1

BLM15BD121SS1D-GP

+1.8V_DELAY

SC10U6D3V5KX-1GP
C8104
2
1

+DPLL_PVDD

L8103

BLM15BD121SS1D-GP

SCD01U16V2KX-3GP
C8107
2
1

+1.8V_DELAY

2 OF 7

U8001B

SCD1U16V2KX-3GP
C8106
2
1

SSID = VIDEO
+1.8V_DELAY

+DPLL_VDDC

L8102

TXCAP_DPA3P
TXCAM_DPA3N
MUTI GFX
DPA

TX0P_DPA2P
TX0M_DPA2N
TX1P_DPA1P
TX1M_DPA1N

AA1
Y4
AC7
Y2
U5
U1
Y7
V2
Y8
V4
AB7
W1
AB8
W3
AB9
W5
AC6
W6
AD7
AA3
AC8
AA5
AE8
AA6
AE9
AB4
AD9
AB2
AC10
AC5

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N

DPB

TX3P_DPB2P
TX3M_DPB2N
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N

AF2 DPB_LANE_3P_GPU
AF4 DPB_LANE_3N_GPU
AG3 DPB_LANE_2P_GPU
AG5 DPB_LANE_2N_GPU
AH3 DPB_LANE_1P_GPU
AH1 DPB_LANE_1N_GPU
AK3 DPB_LANE_0P_GPU
AK1 DPB_LANE_0N_GPU
AK5 DPC_LANE_3P_GPU
AM3 DPC_LANE_3N_GPU
AK6 DPC_LANE_2P_GPU
AM5 DPC_LANE_2N_GPU
AJ7 DPC_LANE_1P_GPU
AH6 DPC_LANE_1N_GPU
AK8 DPC_LANE_0P_GPU
AL7 DPC_LANE_0N_GPU

DPB_LANE_3P_GPU
DPB_LANE_3N_GPU

74
74

DPB_LANE_2P_GPU
DPB_LANE_2N_GPU

74
74

DPB_LANE_1P_GPU
DPB_LANE_1N_GPU

74
74

DPB_LANE_0P_GPU
DPB_LANE_0N_GPU

74
74

DPC_LANE_3P_GPU
DPC_LANE_3N_GPU

74
74

DPC_LANE_2P_GPU
DPC_LANE_2N_GPU

74
74

DPC_LANE_1P_GPU
DPC_LANE_1N_GPU

74
74

DPC_LANE_0P_GPU
DPC_LANE_0N_GPU

74
74

M92/ PARK switch

RN8101

1
2
3
4

PARK

8 DPC_VSSR_1
7 DPC_VSSR_2
6 DPC_VSSR_5
5

SRN0J-7-GP

R8121
4K7R2F-GP

+DAC1_AVDD

+1.8V_DELAY

I2C

83 JTAG_TESTEN

DY
HPD4
+3.3V_DELAY

MMBT3904-7-F-GP
Q8104

B2
B2B

JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
TESTEN

C
Y
COMP

GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4

AC16

H2SYNC
V2SYNC

40mA

HPD1

1mA

R2SET

DDC/AUX
PLL/CLOCK

C8132
SCD1U16V2KX-3GP

AF14
AE14

+DPLL_VDDC

DPLL_PVDD
DPLL_PVSS

120mA

DPLL_VDDC 300mA

R8141
XTALIN_R

124R2F-U-GP

7 CLK_GPU27M_NSS

AM28
AK28

TP8110

XTALIN
XTALOUT

NC#AB22
NC#AC22
39 GPU_THERM_DP
39 GPU_THERM_DN

GPU_THERM_DP
GPU_THERM_DN

T4
T2

DPLUS
DMINUS

+DAC1_VDD1DI

+1.8V_DELAY

AM12
AK12

L8109

TP8111

SCD1U16V2KX-3GP

C8142
1
2

R5
AD17
AC17

PARK

DPC_PVDD

L8108
BLM15BD121SS1D-GP

AK10
AL9

PARK

AH12
AM10
AJ9
AL13
AJ13

DAC2_HSYNC
DAC2_VSYNC

PARK

40mA

20mA

DDC6CLK
DDC6DATA
NC_DDCAUX7P
NC_DDCAUX7N

PARK

83
83

1
2

+3.3V_DELAY

65mA

AD19
AC19

+DAC2_VDD2DI

AE20

+DAC2_A2VDD

AE17

+DAC2_A2VDDQ

2
0R0402-PAD-2-GP

+DAC2_A2VDD

1
R8135

2
0R0402-PAD-2-GP

AE19
AG13

GPU_R2SET

1
R8139

2
715R2F-GP

+DAC2_A2VDDQ

AE6
AE5
AD2
AD4

DPB_DOCK_AUX
DPB_DOCK_AUX#

DPB_DOCK_AUX 74
DPB_DOCK_AUX# 74

DPC_DOCK_AUX
DPC_DOCK_AUX#

DPC_DOCK_AUX 74
DPC_DOCK_AUX# 74

AC11
AC13
AD13
AD11
AB22
AC22

CAPs close to eDP Panel Connector

+1.8V_DELAY
L8101 1
2
BLM15BD121SS1D-GP

+3.3V_DELAY

eDP_AUX_GPU
eDP_AUX#_GPU

1
2 C8140
eDP_AUX 54
C8139
1
2
eDP_AUX# 54
SCD1U10V2KX-4GP
GPU_CLK_DDC
AC1 M92CRT_DDCCLK
1
2
M92CRT_DDCDATA
GPU_DAT_DDC
AC3
1
2
R8145
0R0402-PAD-2-GP
R8146
0R0402-PAD-2-GP
AD20
AC20
AE16
AD16

M92CRT_DDCDATA
M92-S2-GP

RN8103

3
4

GPU_CLK_DDC

2
1

+3.3V_DELAY
SRN2K2J-1-GP
<Core Design>
U8101

1
2

75 GPU_CLK_DDC

GPU_DAT_DDC

DY

GPU_DAT_DDC

Wistron Corporation

75

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

5
M92CRT_DDCCLK

4
DMN66D0LDW-7-GP

C8119
SC4D7U6D3V5KX-3GP

1
2
1
2
1
R8130

5V @ CRT side

Title

GPU-TV/CRT/DP PORT (2/4)


Size
C
Date:

C8118
SC1U6D3V2KX-GP

1
1

M92/ PARK switch


+1.8V_DELAY

SCD1U10V2KX-4GP

DDCAUX5P
DDCAUX5N
TS_FDO
TSVDD
TSVSS

L8107 1
2
BLM15BD121SS1D-GP

+DAC2_VDD2DI

AL11
AJ11

R8151
10KR2J-3-GP

SC1U10V3KX-3GP
C8141
2
1

GPU_CLK_REQ#

1 R8147

FAN_PWM
+TSVDD

BLM15BD121SS1D-GP

C8122
SC1U6D3V2KX-GP

AE23
AD23

2
499R2F-2-GP

+1.8V_DELAY

C8121
SCD1U16V2KX-3GP

1
R8128
+DAC1_AVDD

2
1

(Placed between this pin and AVSSQ)

CRT_RSET

AG24
AE22

+DAC1_VDD1DI

75,83
75,83

AD22

75

CRT_HSYNC_GPU
CRT_VSYNC_GPU

L8106 1
2
BLM15BD121SS1D-GP

THERMAL

DDC2CLK
DDC2DATA
AUX2P
AUX2N

R8142
150R2F-1-GP

+1.8V_DELAY

DDC1CLK
DDC1DATA
AUX1P
AUX1N

+DPLL_PVDD

AD14

DY

A2VDD
A2VDDQ
A2VSSQ

VREFG VOLTAGE DIVIDER IS


(VREFG = VDDR4,5(1.8V) / 3 = .6V)

R8140
249R2F-GP

CRT_BLUE_GPU

1mA

1 R8143 2
0R0402-PAD-2-GP

10KR2J-3-GP

VDD2DI
VSS2DI

VREFG

DY

+3.3V_DELAY

2 150R2F-1-GP

AH26
AJ27

DAC2

65mA
GPU_VREFG

R8137
499R2F-2-GP

R8138
10KR2J-3-GP
2
1

G2
G2B

2 150R2F-1-GP

DY

VDD1DI
VSS1DI

R8127

75

C8134
SC1U6D3V2KX-GP

AC14

45mA

R8125

75

CRT_GREEN_GPU

DY

200KR2J-L1-GP

R8150
200KR2J-L1-GPDY

AB13
W8
W9
W7
AD10

AVDD
AVSSQ

R2
R2B

+1.8V_DELAY

74 DPB_DOCK_HPD

GENERICB

HPD1

R8136

1
1

L6
L5
L3
L1
K4
AF24

RSET

70mA

CRT_BLUE_GPU

CRT_RED_GPU

2 150R2F-1-GP

1 R8144 2
0R0402-PAD-2-GP

TP8108
TP8109

JTAG_TRSTB
1
1
1
1

TP8105
TP8106
TP8107
TP8101

HSYNC
VSYNC

AH24
AG25

R8124

R8133
10KR2J-3-GP
2
1

R8149
200KR2J-L1-GPDY

R8132
1KR2J-1-GP
2
1

2 RN8102 3
1
4
0R4P2R-PAD

MMBT3904-7-F-GP
Q8103

DY

R8129 1
2
10KR2J-3-GP
GPU_CLK_REQ#
GPU_GPIO_29
GPU_GPIO_30

83 GPIO_VGA_22

RN

200KR2J-L1-GP

GPU_THERM#

B
BB

DAC1

CRT_GREEN_GPU

C8136
SCD1U16V2KX-3GP

86 PWRCNTL_1

R8131

1
1

TP8103
TP8104

+3.3V_DELAY

DY

HPD2

86 PWRCNTL_0
7 CLK_GPU27M_SS

1 R8152 2
0R0402-PAD-2-GP

PANEL_BKEN_GPU

83 GPIO_VGA_11
83 GPIO_VGA_12
83 GPIO_VGA_13

DY

54 eDP_LCD_HPD

83 GPIO_VGA_05
1
83 GPIO_VGA_08
83 GPIO_VGA_09

R8101
10KR2J-3-GP
2
1

R8148
200KR2J-L1-GPDY

TP8102

38,54 PANEL_BKEN_GPU

200KR2J-L1-GP

MMBT3904-7-F-GP
Q8102

CRT_RED_GPU

AL25
AJ25

C8120
SCD01U16V2KX-3GP

DY

AM26
AK26

C8127
SCD1U16V2KX-3GP

G
GB

C8124
SC1U6D3V2KX-GP
2
1

DY

R8134
1KR2J-1-GP
2
1

R8126

74 DPC_DOCK_HPD

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
GPIO_29_DRM_0
GPIO_30_DRM_1

R
RB

GENERAL PURPOSE I/O


U6
U10
T10
U8
U7
T9
T8
T7
P10
P4
P2
N6
N5
N3
Y9
N1
M4
R6
W10
M2
P8
P7
N8
N7
T11
R11

83 GPIO_VGA_00
83 GPIO_VGA_01
83 GPIO_VGA_02

+3.3V_DELAY

0R2J-2-GP

C8117
SCD1U16V2KX-3GP

SCL
SDA

R1
R3

2
2

C8123
SC10U6D3V5MX-3GP

DY
DY

C8116
SCD01U16V2KX-3GP

0R2J-2-GP
R8122 1
R8123 1

37,54 LCD_SMBCLK
37,54 LCD_SMBDAT

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

81

of

89

H8

AG19
AF20

AG10
AG11

+DPB_PVDD

NC_DPF_PVDD
NC_DPF_PVSS

DPB_PVDD
DPB_PVSS

Dock
M92-S2-GP

+DPA_PVDD

C8323
SC1U6D3V2KX-GP

AG8
AG7

20mA

SPV10

1
2

C8221
SC10U6D3V5KX-1GP

1
2

1
2

C8240
SC10U6D3V5KX-1GP

1
2

C8239
SC1U6D3V2KX-GP

1
2

C8238
SC1U10V2KX-1GP

C8237
SC1U10V2KX-1GP

1
2

C8236
SC1U10V2KX-1GP

1
2

C8232
SC1U6D3V2KX-GP

1
2

C8260
SC1U6D3V2KX-GP

C8259
SC1U6D3V2KX-GP

C8258
SC1U6D3V2KX-GP

C8268
SC1U6D3V2KX-GP

C8267
SC1U6D3V2KX-GP
2
1

C8257
SC1U6D3V2KX-GP

1
2

C8249
SC1U6D3V2KX-GP

C8256
SC1U6D3V2KX-GP
2
1

1
2

C8248
SC1U6D3V2KX-GP

C8265
SCD1U16V2KX-3GP
2
1

C8264
SCD1U16V2KX-3GP
2
1

C8263
SC1U6D3V2KX-GP

C8262
SC1U6D3V2KX-GP
2
1

1
2

C8288
SC1U6D3V2KX-GP

1
2

35mA

SPVSS

BBP#1
BBP#2

144mA

+1.8V_DELAY

L8209
1

PARK

M92/ PARK switch

2
+VCC_GFX_CORE

BLM15BD121SS1D-GP

+SPV10
L8210
1

M92

BLM15BD121SS1D-GP
L8214

+1.1V_GFX_PCIE

300mA

+1.1V_GFX_PCIE
L8218

D-Change

1
2
BLM15BD121SS1D-GP

PARK-S3:110mA@1.0V
M92-S2:200mA@1.1V

PARK

BLM15BD121SS1D-GP

+1.8V_DELAY
L8213
1

PARK

BLM15BD121SS1D-GP

L8212

+1.1V_GFX_PCIE

D-Change

1
2
BLM15BD121SS1D-GP

PARK-S3:110mA@1.0V
M92-S2:200mA@1.1V

L8208

+1.8V_DELAY

D-Change

1
2
BLM15BD121SS1D-GP

<Core Design>
L8207

+1.8V_DELAY

Dock

Dock

Wistron Corporation

1
2
BLM15BD121SS1D-GP

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:

C8230
SC1U6D3V2KX-GP

1
2

C8229
SC1U6D3V2KX-GP

C8228
SC1U6D3V2KX-GP

1
2

C8227
SC1U6D3V2KX-GP

1
2

C8226
SC1U6D3V2KX-GP

C8220
SCD1U16V2KX-3GP

1
1

C8233
SCD1U10V2KX-4GP

2
1

1
2

NC_SPV18

D-Change

DPA_PVDD
DPA_PVSS

DP PLL POWER

Dock

C8329
SC1U6D3V2KX-GP

DPE_PVDD
DPE_PVSS

Dock
2

AG18
AF19

Dock

C8322
SCD1U16V2KX-3GP

+DPE_PVDD

20mA

20mA

AE10

DPAB_CALR

C8328
SCD1U16V2KX-3GP

DPEF_CALR

AF17

SCD1U16V2KX-3GP
C8321
2
1

300mA

SC1U6D3V2KX-GP
C8201
2
1

1
2
BLM15BD121SS1D-GP

SC4D7U6D3V5KX-3GP
C8320
2
1

L8215

C8297
SC4D7U6D3V5KX-3GP

2
2

Dock

R8210
150R2F-1-GP
DPAB_CALR_GND

C8307
SC4D7U6D3V5KX-3GP

C8306
SC1U6D3V2KX-GP

2
1

C8312
SC1U6D3V2KX-GP

Dock

C8313
SC4D7U6D3V5KX-3GP

C8296
SC1U6D3V2KX-GP

1
2
1
2

C8305
SCD1U16V2KX-3GP

PARK

PARK

C8319
SC4D7U6D3V5KX-3GP

Dock

AF10
AG9
AH8
AM6
AM8

DPEF_CALR_GND

PARK

C8324
SC4D7U6D3V5KX-3GP

DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR
DPB_VSSR

+DPB_VDD10

Dock

C8330
SC4D7U6D3V5KX-3GP

R8209
150R2F-1-GP
+1.8V_DELAY

DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR
DPF_VSSR

AF8
AF9

Dock

AF23
AG23
AM20
AM22
AM24

DPB_VDD10
DPB_VDD10

PARK

C8318
SC1U6D3V2KX-GP

1 R8214 2
0R0603-PAD-2-GP

+DPB_VDD18

PARK-S3:110mA@1.0V
M92-S2:170mA@1.1V

AE13
AF13

PARK

Dock

AE1
AE3
AG1
AG6
AH5

DPF_VDD10
DPF_VDD10

+1.1V_GFX_PCIE

C8295
SCD1U16V2KX-3GP

1
+DPA_VDD10

NC_DPB_VDD18
NC_DPB_VDD18

200mA

AF22
AG22

200mA

+DPF_VDD10

DPF_VDD18
DPF_VDD18

170mA

AF16
AG17

DY

BACK BIAS
M11
M12

DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR
DPA_VSSR

AF6
AF7

PARK

200mA

DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR
DPE_VSSR

DPA_VDD10
DPA_VDD10

+DPA_VDD18

0R0603-PAD-2-GP
+DPF_VDD18

C8282
SCD1U16V2KX-3GP

SCD1U16V2KX-3GP
C8287
2
1

200mA

DPE_VDD10
DPE_VDD10

AE11
AF11

C8317
SCD1U16V2KX-3GP

NC_DPA_VDD18
NC_DPA_VDD18

C8311
SCD1U16V2KX-3GP

AG14
AH14
AM14
AM16
AM18

C8283
SC1U10V2KX-1GP
2
1

SCD1U16V2KX-3GP
C8294
2
1

SC1U6D3V2KX-GP
C8293
2
1

SC4D7U6D3V5KX-3GP
C8292
2
1

SC10U6D3V5KX-1GP
C8285
2
1
AG20
AG21

DP A/B POWER

DPE_VDD18
DPE_VDD18

1 R8215

+DPE_VDD10

AG15
AG16

DY

M92-S2-GP

7 of 7

DP E/F POWER
+DPE_VDD18

DY

C8274
SCD1U10V2KX-4GP

NC_MPV18

M13
M15
M16
M17
M18
M20
M21
N20

68mA

+VCC_GFX_CORE

170mA

1
2
BLM15BD121SS1D-GP

DY

U8001G

SCD1U16V2KX-3GP
C8304
2
1

+1.1V_GFX_PCIE
L8211

SC1U6D3V2KX-GP
C8303
2
1

PARK-S3:110mA@1.0V
M92-S2:170mA@1.1V

SC4D7U6D3V5KX-3GP
C8302
2
1

300mA

SC1U6D3V2KX-GP
C8286
2
1

1
2
BLM15BD121SS1D-GP

300mA

L8201

C8281
SC10U6D3V5MX-3GP
2
1

+PCIE_PVDD
L8206

+1.8V_DELAY

J7

+VCC_GFX_CORE

C8280
SC10U6D3V5KX-1GP

PCIE_PVDD

+MPV18

H7

1
2
BLM15BD121SS1D-GP

2
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI
VDDCI

PLL

+SPV10

C8261
SC1U6D3V2KX-GP

60mA

ISOLATED
CORE I/O

VSSRHA

L16
+PCIE_PVDD
AM30

+VCC_GFX_CORE

M92

VDDRHA
C8279
SCD1U10V2KX-4GP

300mA

L8205
BLM15BD121SS1D-GP

C8273
SC1U6D3V2KX-GP

M92

L17

MEM CLK
1

+VDDRHA

VDDR4
VDDR4
VDDR4
VDDR4

C8278
SCD1U10V2KX-4GP

AA11
AA12
Y11
Y12

+VCC_GFX_CORE

2
2 0R2J-2-GP
0R2J-2-GP

AA15
N15
N17
R13
R16
R18
R21
T12
T15
T17
T20
U13
U16
U18
U21
V15
V17
V20
V21
Y13
Y16
Y18
Y21

DY

+1.1V_GFX_PCIE

M92
M92

VDDR5
VDDR5
VDDR5
VDDR5

L23
L24
L25
L26
M22
N22
N23
N24
R22
T22
U22
V22

C8277
SCD1U10V2KX-4GP

1
1

U11
U12
V11
V12

VDDR3
VDDR3
VDDR3
VDDR3

+SPV18

+1.8V_DELAY

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

AB23
AC23
AD24
AE24
AE25
AE26
AF25
AG26

+1.8V_DELAY
1 M92 2
R8202 1 PARK 2 0R2J-2-GP
R8203
0R2J-2-GP
1 M92 2
R8204
0R2J-2-GP

170mA

AA17
AA18
AB17
AB18

L8

PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC
PCIE_VDDC

CORE

+1.5V_RUN

C8272
SCD1U16V2KX-3GP

1
2

C8270
SCD1U16V2KX-3GP

DY
2

C8269
SC1U6D3V2KX-GP

Need find
470ohm bead

VDD_CT
VDD_CT
VDD_CT
VDD_CT

136mA

AA20
AA21
AB20
AB21

PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR
PCIE_VDDR

C8276
SCD1U10V2KX-4GP

1
2
2

C8245
SCD1U16V2KX-3GP

C8244
SCD1U16V2KX-3GP

C8243
SC1U6D3V2KX-GP

1
1

C8255
SCD1U16V2KX-3GP

1
2

DY

C8254
SCD1U16V2KX-3GP

C8253
SC1U6D3V2KX-GP

DY

1
C8251
SC1U10V2KX-1GP

C8252
SC1U6D3V2KX-GP

C8250

PARK SCD1U16V2KX-3GP PARK


2

09/0623

2A

LEVEL
TRANSLATION

M92/ PARK switch


+MPV18

PARK

2.2A

170mA

L8204
BLM15BD121SS1D-GP

VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1
VDDR1

500mA

C8212
SC1U6D3V2KX-GP
1

C8219
SC1U6D3V2KX-GP

H13
H16
H19
J10
J23
J24
J9
K10
K23
K24
K9
L11
L12
L13
L20
L21
L22

C8231
SC1U6D3V2KX-GP

C8211
SC1U6D3V2KX-GP

PCIE

+3.3V_DELAY

R8201
R8205
A32
AM1
AM32

MEM I/O

I/O

+1.8V_DELAY

VSS_MECH
VSS_MECH
VSS_MECH

C8218
SC1U6D3V2KX-GP

C8217
SCD1U16V2KX-3GP
1

C8225
SC1U6D3V2KX-GP

C8210
SC1U6D3V2KX-GP
1

C8216
SC1U6D3V2KX-GP
1

C8224
SCD1U16V2KX-3GP

C8209
SC1U6D3V2KX-GP

1
2

C8208
SC1U6D3V2KX-GP

C8223
SC1U6D3V2KX-GP

2
1

PARK

PARK

C8247
SC1U10V2KX-1GP

+SPV18

2
C8246
SCD1U16V2KX-3GP

4 OF 7

U8001D

+VDD_CT
C8242
SC1U6D3V2KX-GP

PARK

DY

300mA

C8241
SC10U6D3V5KX-1GP

DY

+1.8V_DELAY

L8202
BLM15BD121SS1D-GP

M92/ PARK switch

L8203
BLM15BD121SS1D-GP

C8215
SCD1U16V2KX-3GP

2
2

C8222
SC1U6D3V2KX-GP

1
2

C8207
SCD1U10V2KX-4GP
2

C8214
SC1U6D3V2KX-GP

C8213
SC1U6D3V2KX-GP

C8206
SC1U6D3V2KX-GP
1

SC10U6D3V5KX-1GP
C8205
2
1

SC22U6D3V5MX-2GP
C8204
2
1

SC10U6D3V5KX-1GP
C8203

DY

2
+1.8V_DELAY

GND

DY

M92-S2-GP

+1.5V_RUN

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

A3
A30
AA13
AA16
AB10
AB15
AB6
AC9
AD6
AD8
AE7
AG12
AH10
AH28
B10
B12
B14
B16
B18
B20
B22
B24
B26
B6
B8
C1
C32
E28
F10
F12
F14
F16
F18
F2
F20
F22
F24
F26
F6
F8
G10
G27
G31
G8
H14
H17
H2
H20
H6
J27
J31
K11
K2
K22
K6

POWER

M6
N11
N12
N13
N16
N18
N21
P6
P9
R12
R15
R17
R20
T13
T16
T18
T21
T6
U15
U17
U20
U3
U9
V13
V16
V18
V6
Y10
Y15
Y17
Y20
Y6

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS
PCIE_VSS

SC10U6D3V5KX-1GP
C8202
2
1

+1.5V_RUN
AA27
AB24
AB32
AC24
AC26
AC27
AD25
AD32
AE27
AF32
AG27
AH32
K28
K32
L27
M32
N25
N27
P25
P32
R27
T25
T32
U25
U27
V32
W25
W26
W27
Y25
Y32

5 OF 7

U8001E

C8271
SCD1U16V2KX-3GP

SSID = VIDEO

GPU-POWER/GND(3/4)

Document Number

Sheet
1

82

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

of

89

SSID = VIDEO

ATI RESERVED CONFIGURATION STRAPS

( 0.5 * VDDR1 ) ( for SSTL-1.8/SSTL-2/DDR2 )


( 0.7 * VDDR1 ) ( for GDDR3/GDDR4 )

R8301
100R2F-L1-GP-U

R8302
100R2F-L1-GP-U

R8303
100R2F-L1-GP-U

+1.5V_RUN

C8331
SCD1U16V2KX-3GP

+1.5V_RUN

R8304
243R2F-2-GP 1

+1.5V_RUN

K26
J26

VGA_CALRN0 J25
VGA_CALRN1 K7
VGA_CALRP1
J8
VGA_CALRP0 K25

PARK2R8307 243R2F-2-GP

L10

+1.5V_RUN
R8310
2KR2J-1-GP

K8
L7

M92

DQA_0
DQA_1
DQA_2
DQA_3
DQA_4
DQA_5
DQA_6
DQA_7
DQA_8
DQA_9
DQA_10
DQA_11
DQA_12
DQA_13
DQA_14
DQA_15
DQA_16
DQA_17
DQA_18
DQA_19
DQA_20
DQA_21
DQA_22
DQA_23
DQA_24
DQA_25
DQA_26
DQA_27
DQA_28
DQA_29
DQA_30
DQA_31
DQA_32
DQA_33
DQA_34
DQA_35
DQA_36
DQA_37
DQA_38
DQA_39
DQA_40
DQA_41
DQA_42
DQA_43
DQA_44
DQA_45
DQA_46
DQA_47
DQA_48
DQA_49
DQA_50
DQA_51
DQA_52
DQA_53
DQA_54
DQA_55
DQA_56
DQA_57
DQA_58
DQA_59
DQA_60
DQA_61
DQA_62
DQA_63

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13/BA2
MAA_14/BA0
MAA_15/BA1
DQMA_0
DQMA_1
DQMA_2
DQMA_3
DQMA_4
DQMA_5
DQMA_6
DQMA_7
RDQSA_0
RDQSA_1
RDQSA_2
RDQSA_3
RDQSA_4
RDQSA_5
RDQSA_6
RDQSA_7
WDQSA_0
WDQSA_1
WDQSA_2
WDQSA_3
WDQSA_4
WDQSA_5
WDQSA_6
WDQSA_7
ODTA0
ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

NC_MEM_CALRN0
NC_MEM_CALRN1

WEA0B
WEA1B

MEM_CALRP1
NC_MEM_CALRP0

K17
J20
H23
G23
G24
H24
J19
K19
J14
K14
J11
J13
H11
G11
J16
L15

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
BA2
BA0
BA1

E32
E30
A21
C21
E13
D12
E3
F4

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

H28
C27
A23
E19
E15
D10
D6
G5

RDQSA0
RDQSA1
RDQSA2
RDQSA3
RDQSA4
RDQSA5
RDQSA6
RDQSA7

H27
A27
C23
C19
C15
E9
C5
H4

WDQSA0
WDQSA1
WDQSA2
WDQSA3
WDQSA4
WDQSA5
WDQSA6
WDQSA7

L18
K16

ODTA0
ODTA1

H26
H25

CLKA0
CLKA0#

G9
H9

CLKA1
CLKA1#

G22
G17

RASA0#
RASA1#

G19
G16

CASA0#
CASA1#

H22
J22

CSA0_0#

G13
K13

CSA1_0#

K20
J17

CKEA0
CKEA1

G25
H10

WEA0#
WEA1#

AB16
G14
G20

RSVD#1
RSVD#2
RSVD#3

DRAM_RST

MAA13_R 1
R8308

MAA[0..12]

84,85

RDQSA0 and WDQSA0 = differential pair


RDQSA1 and WDQSA1 = differential pair
ETC

V
DQMA#[0..3]

84

DQMA#[4..7]

85

RDQSA[0..3]

84

RDQSA[4..7]

85

STRAPS

Chingis
(formerly PMC)

PIN

MAA13
PARK20R2J-2-GP

CLKA0
CLKA0#

84
84

CLKA1
CLKA1#

85
85

RASA0#
RASA1#

84
85

CASA0#
CASA1#

84
85

CSA0_0#

84

CSA1_0#

85

CKEA0
CKEA1

84
85

WEA0#
WEA1#

84
85

M25P05A
M25P10A
M25P20
M25P40
M25P80

0100
0101
0101
0101
0101

Pm25LV512A
Pm25LV010A

0100
0101

DESCRIPTION
Tansmitter Power Savings Enable

V 0= 50% Tx output swing

GPIO1

V 0= Tx de-emphasis disabled

1= Full Tx output swing

84

Transmitter De-emphasis Enable

TX_DEEMPH_EN
WDQSA[4..7]
ODTA0
84
ODTA1
85

ST
Microelectronics

(Internal PD)
WDQSA[0..3]

Part Number GPIO[13,12,11]

GPIO0

1= Tx de-emphasis enabled

(Internal PD)

85

BIF_GEN2_EN_A

GPIO2

BIF_CLK_PM_EN

GPIO8

V 0 = Advertises the PCI-E device


as 2.5GT/s
1 = Advertises the PCI-E device
as 5GT/s

V 0= Disable CLKREQ#power management capability


1= Enable CLKREQ# power management capability
C

ROMIDCFG[3:0]
(Internal PD)

GPIO[13,12,11]

if BIOS_ROM_EN=1,then Config[3:0]
defines the ROM type
if BIOS_ROM_EN=0,then Config[3:0]
defines the primary memory apeture size
Enable external BIOS ROM device

BIOS_ROM_EN

GPIO_22_ROMCSB V 0= Disable external BIOS ROM device


1= Enable external BIOS ROM device

(Internal PD)
AUD[1]
AUD[0]

VGA_HSYNC
VGA_VSYNC

MAA13 84,85

(Internal PD)

CLKTESTA
CLKTESTB

C8332
SCD1U10V2KX-4GP

VGA_CLKTSTA
VGA_CLKTSTB

PARK PARK

R8333
51D1R2F-GP

route 50ohms
single-ended/100ohms diff
and keep short

81 GPIO_VGA_02
81 GPIO_VGA_05

Use this option ONLY


for Park-S3

81 GPIO_VGA_08
81 GPIO_VGA_09
81 GPIO_VGA_11

PARK PARK
2

3
4

RN8302
M92SRN4K7J-8-GP

2
1

2
SC68P50V2JN-1GP

For PARK-S3, R7620 change


to 150 ohms (1%)

C8334
SCD1U10V2KX-4GP

81 GPIO_VGA_01

M92
PARK

R8332
51D1R2F-GP

C8338

SC2200P50V2KX-2GP C8337
2
1

x000
x001
x010
x
x
x
x
x

AUD[1:0]
00:No audio function
01:Audio for DisplayPort and HDMI
( if adapter is detected)
10:Audio for DisplayPort only
11:Audio for both DisplayPort and HDMI

M92-S2-GP

1
10KR2J-3-GP
R2325
2

R8335
680R2F-GP

128MB
256MB
64MB
32MB
512MB
1GB
2GB
4GB

TX_PWRS_ENB

81 GPIO_VGA_00

PARK2

If BIOS_ROM_EN (GPIO22) = 1

Size of the primary


GPIO[13,12,11] Manufacturer
memory apertures

84,85
84,85
84,85

R8314 1

DY

2 10KR2J-3-GP

R8315 1

DY

2 10KR2J-3-GP

R8316 1

DY

2 10KR2J-3-GP

R8317 1

84,85 MEM_RST
1

GPIO3 , H2SYNC , V2SYNC


PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET

+3.3V_DELAY

R8334
0R0402-PAD-2-GP
1
2

PARK

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESE

If BIOS_ROM_EN (GPIO22) = 0
BA2
BA0
BA1

C8336
SCD1U16V2KX-3GP

2
1
2

MVREFD
MVREFS
2
PARK
R8305 1
2
243R2F-2-GP PARK

81 JTAG_TESTEN

R8309
100R2F-L1-GP-U

K27
J29
H30
H32
G29
F28
F32
F30
C30
F27
A28
C28
E27
G26
D26
F25
A25
C25
E25
D24
E23
F23
D22
F21
E21
D20
F19
A19
D18
F17
A17
C17
E17
D16
F15
A15
D14
F13
A13
C13
E11
A11
C11
F11
A9
C9
F9
D8
E7
A7
C7
F7
A5
E5
C3
E1
G7
G6
G1
G3
J6
J1
J3
J5

MEMORY INTERFACE

84,85 MDA[0..63]
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

3 OF 7

U8001C

81 GPIO_VGA_12

For M9X-S2/S3,J8 Pin Connect to VSS


through 240 Ohms(0.5%) resistor.
For Park-S3,J8 Pin Connect to VSS
through 150 Ohms(1%) resistor for DPC_CALR

Use this option ONLY


for M9x-S2/S3vFamily

81 GPIO_VGA_13
81 GPIO_VGA_22
81 DAC2_VSYNC

DY

2 10KR2J-3-GP

R8318

DY

2 10KR2J-3-GP

R8319

DY

2 10KR2J-3-GP

R8320

R8321

DY

2 10KR2J-3-GP

R8322

DY

2 10KR2J-3-GP

GPIO_VGA_05
(Internal PD)

GPIO_5_AC_BATT is an optional input which


allows the system to request a fast power
reductionby setting GPIO_5_AC_BATT to
low (0 V).The resulting state transition may
disturb the display momentarily.Power
reductions that are less time critical should
V use the standard software methods only in
order to prevent display disturbances.

2 10KR2J-3-GP

R8323

DY

2 10KR2J-3-GP

R8324

DY

2 10KR2J-3-GP

R8325

DY

2 10KR2J-3-GP

STRAPS
MEM_TYPE

PIN

DESCRIPTION
MEMORY TYPE,SIZE INFO AND MANUFACTURER
Hynix
Samsung
0010 - gDDR3 128Mx16 Hynix
0011 - gDDR3 128Mx16 Samsung

V 0000 - gDDR3 64Mx16


V 0001 - gDDR3 64Mx16

DVPDATA(19,21,2,0)

(Internal PD)

R8306
1

M92

VGA_CALRP1

81 DAC2_HSYNC

240R2F-1-GP
1
R8326

+1.8V_DELAY

PARK2

150R2F-1-GP
81 DVPDATA0

1
R8328

81 DVPDATA2

1
R8329

81 DVPDATA21

1
R8330

DY

81 DVPDATA19

1
R8331

DY

VRAM

2
10KR2J-3-GP

VRAM2

10KR2J-3-GP
10KR2J-3-GP
10KR2J-3-GP

+3.3V_DELAY
A

RN8301
75,81 CRT_VSYNC_GPU
75,81 CRT_HSYNC_GPU

1
2
SRN10KJ-5-GP

4
3
<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A2
Date:
5

GPU-MEMORY/STRAPS(4/4)

Document Number

Sheet
1

83

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

of

89

SSID = VIDEO
Place blow decouping caps close VDD pin.

Place blow decouping caps close VDD pin.

+1.5V_RUN

+1.5V_RUN

+1.5V_RUN

83,85 MAA[0..12]
83,85 MAA13
83,85
83,85
83,85

BA0
BA1
BA2

83
83

CLKA0
CLKA0#

83

CKEA0

83
83

DQMA#0
DQMA#2
83
83
83

WEA0#
CASA0#
RASA0#

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
BA0
BA1
BA2

M2
N8
M3

CLKA0
CLKA0#

J7
K7

CKEA0

K9

DQMA#0
DQMA#2

D3
E7

WEA0#
CASA0#
RASA0#

L3
K3
J3

RDQSA0
WDQSA0

DQSL
DQSL#

F3
G3

RDQSA2
WDQSA2

ODT

K1

ODTA0

L2
T2

CSA0_0#
MEM_RST

A0
A1
A2
CS#
A3
RESET#
A4
VRAM
A5
A6
NC#T7
A7
NC#L9
A8
NC#L1
A9
NC#J9
A10/AP
NC#J1
A11
A12/BC#
A13
VSS
A15
VSS
VSS
VSS
BA0
VSS
BA1
VSS
BA2
VSS
VSS
VSS
CK
VSS
CK#
VSS
VSS
CKE
VSSQ
VSSQ
DMU
VSSQ
DML
VSSQ
VSSQ
VSSQ
W E#
VSSQ
CAS#
VSSQ
RAS#
VSSQ

C7
B7

DQSU
DQSU#

VREFDQ_0_2
83 WDQSA[0..3]

RDQSA0
WDQSA0

Place C8424 C8426


close to H1 M8

83
83

RDQSA2
WDQSA2

83
83

ODTA0

83

VREFCA_0_2
ZQ_1_3

CSA0_0#
MEM_RST 83,85

83

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

83,85 MAA[0..12]
83,85 MAA13
83,85
83,85
83,85

G1
F9
E8
E2
D8
D1
B9
B1
G9

C8424
SCD1U10V2KX-4GP

D7
C3
C8
C2
A7
A2
B8
A3

83 RDQSA[0..3]

R8410
243R2F-2-GP

1
2

R8407
243R2F-2-GP

1
2

R8408
4K99R2F-L-GP

ZQ_0_2

VREFDQ
VREFCA
ZQ

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDA7
MDA3
MDA5
MDA2
MDA0
MDA4
MDA1
MDA6

83,85 MDA[0..63]

H1
M8
L8

VREFCA_0_2

C8425
SCD1U10V2KX-4GP

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MDA16
MDA20
MDA17
MDA21
MDA22
MDA23
MDA18
MDA19

1
2

VREF=0.75V

A8
A1
C1
C9
D2
E9
F1
H9
H2

C8422
SC10U6D3V5MX-3GP
2
1

C8421
SC10U6D3V5KX-1GP
2
1

C8420
SC10U6D3V5KX-1GP
2
1

C8419
SC1U6D3V2KX-GP
2
1

C8418
SC1U6D3V2KX-GP
2
1

U8402

E3
F7
F2
F8
H3
H8
G2
H7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

SCD1U10V2KX-4GP

Place C8423 C8425


close to H1 M8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

1
2

R8405
4K99R2F-L-GP

+1.5V_RUN

C8423
SCD1U10V2KX-4GP

K8
K2
N1
R9
B2
D9
G7
R1
N9

MDA[0..63]

2
C8426

R8403
4K99R2F-L-GP

2
1
C

R8401
4K99R2F-L-GP

VREFDQ_0_2

DY

+1.5V_RUN
U8401

VREF=0.75V

DY

C8417
SC1U6D3V2KX-GP
2
1

C8416
SC1U6D3V2KX-GP
2
1

C8415
SC1U6D3V2KX-GP
2
1

C8414
SC1U6D3V2KX-GP
2
1

C8413
SC1U6D3V2KX-GP
2
1

C8412
SC1U6D3V2KX-GP
2
1

C8411
SC10U6D3V5KX-1GP
2
1

C8410
SC10U6D3V5KX-1GP
2
1

C8409
SC10U6D3V5KX-1GP
2
1

C8408
SC1U6D3V2KX-GP
2
1

C8407
SC1U6D3V2KX-GP
2
1

100R

C8406
SC1U6D3V2KX-GP
2
1

100R

C8405
SC1U6D3V2KX-GP
2
1

MVREF TO GND

40.2R

C8404
SC1U6D3V2KX-GP
2
1

100R

C8403
SC1U6D3V2KX-GP
2
1

MVREF TO 1.8V

C8402
SC1U6D3V2KX-GP
2
1

+1.5V_RUN

DDR2/3 GDDR3
C8401
SCD1U10V2KX-4GP
2
1

DIVIDER RESISTORS

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

CLKA0
CLKA0#

83

CKEA0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8

VREFDQ
VREFCA
ZQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
BA0
BA1
BA2

M2
N8
M3

CLKA0
CLKA0#

J7
K7

BA0
BA1
BA2

83
83

K8
K2
N1
R9
B2
D9
G7
R1
N9

CKEA0

K9

DQMA#1
DQMA#3

D3
E7

WEA0#
CASA0#
RASA0#

L3
K3
J3

83 DQMA#[0..3]
83
83
83
83
83

DQMA#1
DQMA#3
WEA0#
CASA0#
RASA0#

H5TQ1G63BFR-12C-GP

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA26
MDA25
MDA28
MDA24
MDA29
MDA30
MDA27
MDA31

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA8
MDA9
MDA11
MDA14
MDA10
MDA15
MDA12
MDA13

DQSU
DQSU#

C7
B7

RDQSA1
WDQSA1

DQSL
DQSL#

F3
G3

RDQSA3
WDQSA3

ODT

K1

ODTA0

L2
T2

CSA0_0#
MEM_RST

A0
A1
A2
CS#
A3
RESET#
A4
VRAM
A5
A6
NC#T7
A7
NC#L9
A8
NC#L1
A9
NC#J9
A10/AP
NC#J1
A11
A12/BC#
A13
VSS
A15
VSS
VSS
VSS
BA0
VSS
BA1
VSS
BA2
VSS
VSS
VSS
CK
VSS
CK#
VSS
VSS
CKE
VSSQ
VSSQ
DMU
VSSQ
DML
VSSQ
VSSQ
VSSQ
W E#
VSSQ
CAS#
VSSQ
RAS#
VSSQ

RDQSA1
WDQSA1

83
83

RDQSA3
WDQSA3

83
83

ODTA0

83

CSA0_0#
MEM_RST 83,85

83

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

G1
F9
E8
E2
D8
D1
B9
B1
G9

H5TQ1G63BFR-12C-GP

R8411
CLKA0
A

CLKA0_GND

56R2J-4-GP

Wistron Corporation

R8412
CLKA0#

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.

C8427
SCD01U16V2KX-3GP
Title
Size

VRAM (1/2)

Document Number

Custom
Date:
5

<Core Design>

56R2J-4-GP

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

84

of

89

SSID = VIDEO
Place blow decouping caps close VDD pin.

Place blow decouping caps close VDD pin.

+1.5V_RUN

83,84 MDA[0..63]

VREF=0.75V

C8525
SCD1U10V2KX-4GP

83,84 MAA[0..12]
83,84 MAA13

R8508
243R2F-2-GP

ZQ_4_6

1
2

R8507
4K99R2F-L-GP

VREFCA_4_6

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7

83,84
83,84
83,84
83
83

CLKA1
CLKA1#

83
83
83

BA0
BA1
BA2

CKEA1
DQMA#6
DQMA#4

83
83
83

WEA1#
CASA1#
RASA1#

BA0
BA1
BA2

M2
N8
M3

CLKA1
CLKA1#

J7
K7

CKEA1

K9

DQMA#6
DQMA#4

D3
E7

WEA1#
CASA1#
RASA1#

L3
K3
J3

MDA51
MDA53
MDA48
MDA55
MDA49
MDA54
MDA50
MDA52

DQSU
DQSU#

C7
B7

RDQSA6
WDQSA6

DQSL
DQSL#

ODT
A0
A1
A2
CS#
A3
RESET#
A4
A5
A6
NC#T7
A7
NC#L9
A8
NC#L1
A9
NC#J9
A10/AP
NC#J1
VRAM
A11
A12/BC#
A13
VSS
A15
VSS
VSS
VSS
BA0
VSS
BA1
VSS
BA2
VSS
VSS
VSS
CK
VSS
CK#
VSS
VSS
CKE
VSSQ
VSSQ
DMU
VSSQ
DML
VSSQ
VSSQ
VSSQ
W E#
VSSQ
CAS#
VSSQ
RAS#
VSSQ

F3
G3

RDQSA4
WDQSA4

K1

ODTA1

L2
T2

CSA1_0#
MEM_RST

83 WDQSA[4..7]

RDQSA6
WDQSA6
RDQSA4
WDQSA4
ODTA1

Place C8528 C8529


close to H1 M8

83
83

VREFCA_4_6

83
83

ZQ_5_7

83

CSA1_0#
MEM_RST 83,84

83

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

83,84 MAA[0..12]
83,84 MAA13
83,84
83,84
83,84
83
83
83 DQMA#[4..7]

G1
F9
E8
E2
D8
D1
B9
B1
G9

C8522
SC10U6D3V5KX-1GP
2
1

C8521
SC10U6D3V5KX-1GP
2
1

C8520
SC10U6D3V5KX-1GP
2
1

C8519
SC1U6D3V2KX-GP
2
1

C8518
SC1U6D3V2KX-GP
2
1

C8517
SC1U6D3V2KX-GP
2
1

C8516
SC1U6D3V2KX-GP
2
1

C8515
SC1U6D3V2KX-GP
2
1

C8514
SC1U6D3V2KX-GP
2
1

VREFDQ_4_6

VREFDQ
VREFCA
ZQ

D7
C3
C8
C2
A7
A2
B8
A3

83 RDQSA[4..7]

H1
M8
L8

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

U8502

C8528
SCD1U10V2KX-4GP

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

MDA37
MDA36
MDA39
MDA34
MDA32
MDA33
MDA38
MDA35

Place C8523 C8525


close to H1 M8

A8
A1
C1
C9
D2
E9
F1
H9
H2

E3
F7
F2
F8
H3
H8
G2
H7

83
83
83

BA0
BA1
BA2
CLKA1
CLKA1#
CKEA1

DQMA#7
DQMA#5
83
83
83

WEA1#
CASA1#
RASA1#

R8510
243R2F-2-GP

1
C8523
SCD1U10V2KX-4GP

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1
2

+1.5V_RUN
R8505
4K99R2F-L-GP

R8502
4K99R2F-L-GP

VREFDQ_4_6

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VREF=0.75V

K8
K2
N1
R9
B2
D9
G7
R1
N9

+1.5V_RUN

MDA[0..63]

2
C8529

1
2

R8501
4K99R2F-L-GP

U8501

SCD1U10V2KX-4GP

+1.5V_RUN

C8513
SC1U6D3V2KX-GP
2
1

C8512
SC1U6D3V2KX-GP
2
1

C8511
SC10U6D3V5KX-1GP
2
1

DY

C8510
SC10U6D3V5KX-1GP
2
1

C8509
SC10U6D3V5KX-1GP
2
1

C8508
SC1U6D3V2KX-GP
2
1

C8507
SC1U6D3V2KX-GP
2
1

C8506
SC1U6D3V2KX-GP
2
1

C8505
SC1U6D3V2KX-GP
2
1

C8504
SC1U6D3V2KX-GP
2
1

+1.5V_RUN

C8503
SC1U6D3V2KX-GP
2
1

C8502
SC1U6D3V2KX-GP
2
1

C8501
SC1U6D3V2KX-GP
2
1

+1.5V_RUN

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

K8
K2
N1
R9
B2
D9
G7
R1
N9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A8
A1
C1
C9
D2
E9
F1
H9
H2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

H1
M8
L8

VREFDQ
VREFCA
ZQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
M7
BA0
BA1
BA2

M2
N8
M3

CLKA1
CLKA1#

J7
K7

CKEA1

K9

DQMA#7
DQMA#5

D3
E7

WEA1#
CASA1#
RASA1#

L3
K3
J3

H5TQ1G63BFR-12C-GP

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA44
MDA45
MDA47
MDA40
MDA46
MDA43
MDA41
MDA42

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA62
MDA63
MDA61
MDA60
MDA58
MDA56
MDA59
MDA57

DQSU
DQSU#

C7
B7

RDQSA7
WDQSA7

DQSL
DQSL#

F3
G3

RDQSA5
WDQSA5

K1

ODTA1

L2
T2

CSA1_0#
MEM_RST

ODT
A0
A1
A2
CS#
A3
RESET#
A4
A5
A6
NC#T7
A7
NC#L9
A8
NC#L1
A9
NC#J9
A10/AP
NC#J1
VRAM
A11
A12/BC#
A13
VSS
A15
VSS
VSS
VSS
BA0
VSS
BA1
VSS
BA2
VSS
VSS
VSS
CK
VSS
CK#
VSS
VSS
CKE
VSSQ
VSSQ
DMU
VSSQ
DML
VSSQ
VSSQ
VSSQ
W E#
VSSQ
CAS#
VSSQ
RAS#
VSSQ

RDQSA7
WDQSA7

83
83

RDQSA5
WDQSA5

83
83

ODTA1

83

CSA1_0#
MEM_RST 83,84

83

T7
L9
L1
J9
J1
J8
M1
M9
J2
P9
G8
B3
T1
A9
T9
E1
P1

G1
F9
E8
E2
D8
D1
B9
B1
G9

H5TQ1G63BFR-12C-GP

R8511
CLKA1
A

CLKA1_GND

56R2J-4-GP

R8512

Wistron Corporation

C8527
SCD01U16V2KX-3GP

56R2J-4-GP

CLKA1#

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,


Taipei Hsien 221, Taiwan, R.O.C.
Title

VRAM (2/2)

Size
Document Number
Custom
Date:
5

<Core Design>

Rev

-1

Fonseca 14.1" DIS

Thursday, March 18, 2010

Sheet
1

85

of

89

1
2

Design Current = 7.5A


11.8<OCP<13.9A

TPS51511RHLRG4-GP

4
3
2
1

NC#2

V5IN

+VCC_GFX_CORE
+VCC_GFX_COREP

PTC8601
ST330U2D5VDM-13GP

1
2

PTC8603
ST220U2D5VBM-2GP
2
1

PC8609
SCD1U10V2KX-4GP

1
GAP-CLOSE-PWR-3-GP

2
1
2

GAP-CLOSE-PW R
C

+GFX_CORE_VOUT

DY

1
2

PR8609
10KR2F-2-GP

GAP-CLOSE-PW R

PQ8601
2N7002A-7-GP

PW RCNTL_1_R

DY

PG8614
2

GAP-CLOSE-PW R
PG8615
1
2

PR8623
5K1R2F-2-GP

PG8612
2

GAP-CLOSE-PW R
PG8613
1
2

+GFX_CORE_VFB

PR8616
49K9R2F-L-GP

GAP-CLOSE-PW R
PG8616
1
2

1
PR8617
10KR2F-2-GP

GAP-CLOSE-PW R
PG8610
2
1

DY

DY

PR8624

+3.3V_RUN

DY

PG8606
1

GAP-CLOSE-PW R
PG8608
2
1

GAP-CLOSE-PW R

DY

DY

DY

DY

SCD047U16V2KX-1-GP
PC8601
2
1

1
2

PD8602

B0530W S-7-F-GP

10K7R2F-GP

Power team check

+3.3V_DELAY

PC8612
SC330P50V3KX-GP
PC8617

+3.3V_DELAY

81 PW RCNTL_1

Voltage
0.9V
0.95V

DY

PR8613
39K2R2F-L-GP

DY

PG8611

SC1KP50V2KX-1GP
2
1

GFX_CORE_EN

DY

VID0
GPIO15
1
0

PR8604
2D2R5F-2-GP

Vout=0.75V*(R1+R2)/R2

VID1
GPIO20
x
x

DY

+GFX_CORE_DRVL

PR8625
10KR2F-2-GP

5
6
7
8
SCD1U25V3KX-GP

4
3
2
1

PGND

GND
GND

1
1

0R3J-0-U-GP

PU8603

PC8613

1 PR8615 2 GFX_MEM_VTT_ON_C
0R0402-PAD-2-GP
PC8615
SCD1U10V2KX-4GP

38 GFX_MEM_VTT_ON

PR8605
PC8610
1+GFX_CORE_LL1
1
2

GFX_CORE_PW RGD

+GFX_CORE_DRVL
+GFX_CORE_LL
+GFX_CORE_DRVH
+GFX_CORE_VBST 2

IND-2D2UH-111-GP

PWRCNTL_1#

DY

17
18
19
20

PR8622
100KR2J-1-GP

38 GFX_CORE_ON
38,42,51,72 RUN_ON

1 PR8611 2
0R0402-PAD-2-GP
1
2
PR8612
0R2J-2-GP

DRVL
LL
DRVH
VBST

PC8614
SCD01U50V2KX-1GP

PR8610
100KR2J-1-GP

11
12

+3.3V_SUS

ENLDO
ENSW

GFX_MEM_VTT_ON_C
GFX_CORE_EN

16

1 PR8608 2
0R0603-PAD-2-GP

+5V_ALW

COMP
PGOOD
CS

PC8611

SC4D7U10V3KX-GP

PR8607
6K2R2F-GP

8
13
15

PL8601
+GFX_CORE_LL

S
S
S
G

VOUT = 0.5 *(1+Rtop/Rbot)

PR8606
30KR2F-GP

ODOFF
OD

21
5

+5V_ALW
38 GFX_CORE_PW RGD

6
7

9
10

+GFX_CORE_VFB1
2
R8603
130KR2F-GP

PR8602
15KR2F-GP

GAP-CLOSE-PW R

+GFX_ODOFF

PG8609
2

VOSW
VSWFB

D
D
D
D

GAP-CLOSE-PW R

SC22U6D3V5MX-2GP

PC8608

VLDOIN
VLDO
VLDOFB

+GFX_CORE_VOUT
+GFX_CORE_VFB

SIR460DP-T1-GE3-GP

1
3
4

SC1000P100V3KX-GP

SC22U6D3V5MX-2GP

PG8607
2

PWRCNTL_0=GPIO15
PWRCNTL_1=GPIO20

PC8604
SC2200P50V2KX-2GP

1
2

14

1
2

PU8602
SI7686DP-T1-GP

GAP-CLOSE-PW R
PU8601

+GFX_CORE_VLDOFB
PC8607

GAP-CLOSE-PW R
PG8619
1
2

+GFX_CORE_DRVH

GAP-CLOSE-PW R

+1D1V_RUN_P
PG8604
1
2

PC8606
SCD1U10V2KX-4GP

+1.1V_GFX_PCIE

PC8618
SC1U6D3V2KX-GP

GAP-CLOSE-PW R
PG8601
2
1

S
S
S
G

+1.1V_RUN
Design current = 1.7A
peak current = 2.5A

GAP-CLOSE-PW R

-1.10/0302

+PW R_SRC_GFX_CORE

D
D
D
D

PC8605
SC1U10V3KX-3GP

GAP-CLOSE-PW R
PG8603
1
2
GAP-CLOSE-PW R
PG8605
1
2

PG8617
1

GAP-CLOSE-PW R
PG8618
2
1

2
+5V_ALW

+1.5V_LDOIN_GFX
PG8602
1
2

+PW R_SRC_GFX_CORE

+1.5V_SUS

+PW R_SRC

PC8603
SCD1U50V3KX-GP

SSID = PWR.Plane.Regulator_GFX

PC8602
SC10U25V6KX-1GP

5
6
7
8

+GFX_ODOFF
PD8601

PW RCNTL_0_R
0R2J-2-GP

D
PQ8602
2N7002A-7-GP

DY
1

DY

DY
S

DY

PR8619
5K1R2F-2-GP

SCD047U16V2KX-1-GP

1
PR8621

81 PW RCNTL_0

DY

PC8616
1

DY

B0530W S-7-F-GP

PR8618
100KR2J-1-GP

PR8620
10KR2F-2-GP

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

1 PR8614 2
0R0402-PAD-2-GP

Size

A3
Date:
5

Fonseca

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

86

of

89

(Blank)

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Fonseca 14.1" DIS

Size
Document Number
Custom
Date:
5

Rev

-1

DC to DC 1.5V/1.1V

Thursday, March 18, 2010

Sheet
1

87

of

89

VERSION

DATE

NO

PAGE

02/24

54

03/01

37,54

Modified List

03/03

-1

03/05

03/10

OWNER

Delete FUSE5401, C5407, C5408. Add C5410, C5411, C5412, U5402, R5427, R5426,
Q5405.

EE

Rename net "EC_GPIO060" into "EN_INVPWR". Delete TP3702. Add R3741, 63.10434.1DL.

To solve panel white screen issue on pulling off ADP and apply
it on again within 2 seconds.

EE

64

Add C6410, pop R6419.

Solve +3.3V_ALW drop issue.

EE

65

Add C6501, pop R6502.

Solve +3.3V_ALW drop issue.

EE

86

Add PC8618.

Solve +1.5V_SUS drop issue.

EE

42

Change C4208 to 470pF.

Solve +5V_ALW drop issue.

EE

32

R3214 change to short pad.

EE

65

Add R6503, Q6501.

71

Delete L7101, L7102.

10

37

R3703 change to 33k ohm.

Change board ID.

EE

11

72

Add extra power pins to U7202.

Add Ricoh as express card power switch second source.

EE

12

47

PTC4702 pop. PTC4703 dummy.

Add Ricoh as express card power switch second source.

EE

13

54

Change Q5405 to 84.2N702.E31.

EE

14

65

Name net "WWAN_DIS".

EE

15

58

XDP1, XDP2, R5803, R5804, R5806, C5803, C5802, R5808, R5807, TP5808, TP5810,
TP5815, TP5802, TP5803, TP5804, TP5805, TP5806, TP5807, TP5809, TP5811, TP5812,
TP5801, TP5813, TP5814 change symbols.

16

24

Delete AFTP2401, AFTP2402.

17

7,23,
25

18

03/08

Issue Description

03/02

+3.3V_RUN_WWAN discharge circuit.

EE
EE

Change the symbols so that when SMT, solder paste will not be
applied onto the locations.

EE

EE

Delete RN701, RN703, RN704, RN705, R708, RN2311, RN2302, RN2306, RN2307, RN2308,
RN2301, RN2505.

EE

40

C4002 pop.

EE

19

55

Add AFTP5502, AFTP5503, AFTP5504.

Factory request.

EE

20

67

C6705, C6704 set as SC.

Smart Card use only.

EE

21

70

R7001 dummy.

22

78

Delete EL7801.

23

67

Change Smart Card socket into 21.H0136.011, Smart Card connector into
62.10024.C11.

EE

24

68

Change SW1 into 62.40018.601.

EE

25

79

Change H18 and H19 into ZZ.00PAD.S31.

EE

EE
Common mode choke longer needed.

EE

03/17

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Size
A3
Date:
5

Change List - 1

Document Number

Rev

-1

Fonseca 14.1" DIS


Thursday, March 18, 2010

Sheet
1

88

of

89

VERSION

DATE

03/18
D

03/19
03/22

NO

PAGE

Modified List

Issue Description

OWNER

26

Dummy R903, R913, Q901, C901.

CPU_CATERR# continously pull high.

EE

27

67

Add C6706, 78.27134.1FL.

Eliminate ripple.

EE

28

64

Remove EL6401.

29

67

Change R6705 into 63.10334.1DL, C6704 into 78.22034.1FL, C6705 into 78.39124.2FL,
R6701 change to 63.R0034.1DL.

Smart card VCC ripple eliminate.

EE

30

46

Change PR4647 into 64.32425.6DL.

Raise +5V_ALW voltage level.

EE

EE

-1

<Core Design>

Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title

Change List - 2

Size
A3

Document Number

Date:

Monday, March 22, 2010

Rev

-1

Fonseca 14.1" DIS


Sheet
1

89

of

89

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