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Practical Work 2
No
Name
Practical
Work Report
(Cognitive)
Practical Skill
Marks
(Psychomotor)
Total
Marks
1.
/ 30
/ 70
/ 100
2.
/ 30
/ 70
/ 100
CLASS
LECTURER NAME
DATE SUBMITTED
(Note: Submit this page along with the practical skill rubric after each Practical Work is completed)
/4
2.
Result
/ 10
3.
Discussion
/ 12
4.
Conclusion
/4
TOTAL :
/ 30
PRACTICAL WORK 2
2.1 TITLE: Layout Design and Simulation of MOS Transistor
2.2 LEARNING OUTCOMES
At the end of this practical work session, the student should be able to:
1. design NMOS and PMOS transistor layout according to the Design Rules.
2. simulate NMOS and PMOS transistor characteristics.
3. simulate NMOS and PMOS dynamic behaviour.
2.3 EQUIPMENT/TOOLS
PC Set & Microwind 2.6a software.
2.4 PROCEDURE
Part 1 : Designing NMOS transistor layout according to the design rule.
Open the Microwind Editor window.
Select the Foundry file from File menu. Select cmos012.rul file.
Draw the NMOS layout as shown in figure 2.1. (Use NMOS size : W=6, L=2)
Make sure to conform to the design rules (refer to Appendix A).
Polysilicon
Metal1
Metal1
N+ Diffusion
Page | 2
VDD Property
VSS Property
Clock Property
Node Visible
Pulse Property
Apply a clock to the gate. Click on the Clock icon and then, click on the polysilicon gate. The
clock menu appears again. Change the name into gate and click on OK to apply a clock
with 8 ns period.
To watch the output, click on the Visible icon and then, click on the right diffusion. The
window as shown in figure 2.5 appears. Change the name into source. Click OK. The
Visible property is then sent to the node. The wave form of this node will appear at the next
simulation
Page | 3
Page | 4
N Well
Metal1
P+ Diffusion
Contact P+ Diff/Metal1
Repeat all the steps in Part 1 until Part 3 for the PMOS transistor layout.
Page | 5
2.5 RESULT
In your report, include the results of the following:
1. NMOS
a. Layout without DRC error
b. Transistor cross section
c. Id - Vd characteristic curves
d. Input / Output timing diagram (dynamic behaviour)
(2 marks)
(1 mark)
(1 mark)
(1 mark)
2. PMOS
c. Layout without DRC error
d. Transistor cross section
c. Id - Vd characteristic curves
d. Input / Output timing diagram (dynamic behaviour)
(2 marks)
(1 mark)
(1 mark)
(1 mark)
2.6 DISCUSSION
1.
2.
Explain why PMOS transistor size is double the size of NMOS transistor.
(2 marks)
Make a compariosn between the Id - Vd characteristic curves between NMOS and PMOS
transistors.
(4 marks)
3.
4.
(2 marks)
(4 marks)
2.7 CONCLUSION
Give TWO(2) conclusions for this practical work.
(4 marks)
Page | 6
Appendix A
Design Rules
1.
2.
3.
Page | 7
4.
5.
Appendix A
Contact width : 2
Between two contacts : 5
Extra diffusion over contact: 2
Extra poly over contact: 2
Extra metal over contact: 2
Distance between contact and poly gate: 3
r601
r602
r603
r604
r605
Via width : 2
Between two Via: 5
Between Via and contact: 0
Extra metal over via: 2
Extra metal2 over via: 2
Page | 8
Class :
Student ID# :
Date :
ASPECTS
A.
Technology feature
B.
Design rule
C.
Transistor size
D.
Metal layers
E.
F.
No DRC error
display
Layout Design
input / output /
floorplan
EXCELLENT
4-5
Use correct technology feature
for ALL parts of the layout.
Follow lambda design rule for
minimum width and spacing for
ALL polygons.
Use correct PMOS and NMOS
transistor size.
Use correct number of metal
layers and width.
Able to produce No DRC error
display for ALL layouts.
SCORE DESCRIPTION
MODERATE
2-3
Use correct technology feature
for parts of the layout.
POOR
1
SCALE
x1
x1
Layout simulation
H.
TOTAL
SCORE
x2
x2
x2
x2
x2
x2
/ 70
..
Supervisor Name & Signature