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IntegratedClockGatingCell
PostedonFebruary18,2014bySiniMukundaninPhysicalDesign//10Comments
Clockgatingisacommontechniqueforreducingclockpowerbyshuttingofftheclocktomodulesbya
clockenablesignal.ClockgatingfunctionallyrequiresonlyanANDorORgate.Consideryouwere
usinganANDgatewithclock.ThehighENedgemaycomeanytimeandmaynotcoincidewithaclock
edge.InthatcasetheoutputoftheANDgatewillbea1forlesstimethantheclocksdutycycle.Youin
turnendupwithaglitchinyourclocksignal.
Toavoidthis,aspecialkindofclockgatingcellsareused,thatsynchronizestheENwithaclockedge.
ThesearecallintegratedclockgatingcellsorICG.
TherearetwocommonlyusedICGcelltypes.
UsingANDgatewithhighEN
ThefollowingdesignusesanegativeedgetriggeredlatchtosynchronizetheENsignaltothe
CLK.TheGCLKisavailableonlywhenthelatcho/pishigh.GCLKisheldlowwhenENislow.

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UsingORgatewithhighEN
Thefollowingdesignusesapositiveedgetriggeredlatch.GCLKisheldhighwhenENislow.Note
thatthelatcho/pisinvertedattheORinput.Hence,theclockispassedthroughwhenthisi/pgets
alow.

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SiniMukundan
StaffEngineeratTexasInstruments

Siniisanexpertonphysicaldesignflowandrelatedmethodologies.Outsidework,sheisanavid
readerandgenerallylovesbeinglazy.

cts
icg
10CommentsonIntegratedClockGatingCell
1.

pramod//December22,2014at1:39pm//Reply
Howtimingchecksaredoneonregtoclgpaths?Whytherearetwosetuptime(clkgatingand
nochange)andtwoholdtimesarecomingforthispath?Canyoupleasetellme?

2.

Anil//January14,2015at10:06am//Reply
HiSini,

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DoesLatcho/pwaveformdelayedby1clockcyclecomparetoenablethoughitislevelsensitive
latch?Ifsowhatisthereason?
Regards,
Anil
Sini//January14,2015at12:31pm//Reply
Itwontbeheldanotheronecycle,butifthechangeoccurredwhentheclockwasnotactive,
itwillbeheld.Ithinkthetimingdiagramsareabitoff.AssumetheENgoinglowafterthe
negativeedgeoftheclkinthelasttimingdiagramabove.
3.

Seth//March30,2015at6:36am//Reply
Thetimingwaveformsarewrong.Youdontshowthetransparentphaseofthelatchoutput.

4.

ethan//May18,2015at12:17pm//Reply
Hi,sini,
IgotsomequestionsaboutICG,
Inposedgesynchronousdesign,weoftenuseANDgatewithhighEN.
Buttheclockisheldlowwhenenableislow.PosedgeFFsconstituteoftwolatchs,clk=0makes
thefirstlatchtoggleallthetime.
Howcanthispowersaved?
Regards,
ethan

5.

Sangeetha//September1,2015at8:56am//Reply
IsORgatebasedclockgatingusedonlywhendrivinganegativeedgetriggeredflipflopand
ANDgatebasedclockgatingonlyusedforpositiveedgetriggeredflipflops?

6.

SarathChandra//December13,2015at7:20pm//Reply
Hisini,
Howcomeedgetriggerwordisusedinlatches?Forlatchesitshouldbeleveltriggered.
Hopemyquestionisavalidone.
SiniMukundan//December13,2015at7:47pm//Reply
Incommonusageyes.Butflipflopisalsoanedgesensitivelatch.Thisisthenomenclature
usuallyusedforICGcells,asoneisanenablesignal.

7.

Himavanth//January19,2016at5:52pm//Reply

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whatisstaticanddynamicclockgating
8.

nirmal//March31,2016at12:52pm//Reply
HiSini
InANDbasedclockgating,thereisapossibilityofclockpulsecutoffbeforeclockperiod.Butin
latchbasedclockgating,thereisapossibilityoflosingaclockpulseentirelyiflatchsetuptiming
isviolated(meaninglathenablecomesjustafterclockedge).Amiright?

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