Sardar Vallabhbhai Patel Institute of Technology- Vasad.

Practical Lesson Plan

Name: Prof. Satish L Chauhan.
Subject: Digital Electronics.
Lab. Sessions/Week: 1
Practical
Practical Name
No.
1
2
3
4
5
6

Designation: Asst. Professor

Class: S.Y. Electrical I II
Lab. Slot No. : 3
Batch A

Dept.: Electrical Engg.

Batch: A/B/C/D
Week: 13
Batch D
Batch B Batch C

To study and verify truth table of various logic gate.

To study implementation of various logic gates using NAND
Gate.
To study implementation of various logic gates using only NOR
gate.
To study and verify function of Half Adder and Full Adder
circuits.
To study and verify function of Half sub tractor and Full sub
tractor Circuit.
To study and verify the function of binary to gray code
conversion.

To verify the function of 2-4 line decoder.

To study about 4:1 MUX

To study about 1:4 DE-MUX

10

To verify the function of latch and flip-flop.

11

To study the shift register.

12

OEP

Sign of Faculty member

Dept. HOD.

Principal