Debugging Clock Trees will now

be easier

CADENCE CDNLive! 2007 EMEA Conference in Munich

NEC Electronics
European Technology Center

Martin Spohr - martin.spohr@eu.necel.com

Frank Guffler - frank.guffler@eu.necel.com
Ver. 1.0 04/12

Overview
NEC Electronics Timing Implementation
Clock Tree Synthesis - what is the challenge ?
The idea - how to debug a complex clock tree ?
The solution - Clock Tree Analyst

NEC Electronics in Europe

European Technology Centre

Founded:

1995

Location:

Dsseldorf, Germany

Employees:

120

Main Focus:

Development of advanced ASIC & ASSPs for

the European market

Processes:

0.35m - 55nm =>

Service

Includes all Steps locally from Specification

to Tester Qualification

Full service around ASIC Design Service

ETC Design Services
Design Consultancy
Comprehensive Project Management for
Implementation
DFT Service
RTL Handover & Timing Closure
Physical Implementation & Mask
Verification
Multi-Mio Gates, 0.35 m to 55 nm Node

40+ tape-outs/year make it the experts ...

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CTS what is the challenge ?

Unknown designs with complex clock structures
Big number of clock trees need to be balanced
Each clock tree contains :
thousands of leaf pins
cut points
through pins
macro delay specifications for hierarchical designs
reconvergent clocks
What is the expectation ?
Good balanced clock tree
OCV aware latency and skew

What to do when the result is not as

expected ?
5

What do we get ?
PLL line

The pin name of the number in figure is shown

on the next page.
D D D

1
8

1
6

OSC

ACLK

PLL2 CLKO266M
1
7

OSC33M
Through Pin
Exclude Pin
Preserve Pin

LFT_UART_SCLK
Div4 1

PCLK

D
D

clk divider

Div8

1
2

apb_pclk

ahb_pclk

udl_pclk

LFT_PCI_CLK

delay gate

gated cell

apb_uart_sclk

PCI_CLK
clkmask
8

JTAG1

ahb_aclk
usb_aclk
sata_aclk
pci_aclk
dcu_aclk
ata_aclk
exunit_aclk
sgx_aclk_sys_clk
sgx_aclk_mem_clk

JTAG3

JTAG0

mbus_sclk (133MHz)
mbus_mclk

1
5

hierarchy

CTS root Pin

adjust CTS
delay
clk adjuster

D
D
D
D
D
D
D
D
D

Div2 0

1
4

usb_pci_clk

pci_pci_clk

apb_i2c_clk

D
5

I2C_CLK
clkmask
Div641
3

LFT_I2C_CLK

D
6

Complicated clock specification

6

What do we get ?
Sometimes even
less

Clk in

How to implement and check the clock tree ?

7

Current situation
Current First Encounter Clock tree browser
Is structure oriented not timing!
Can not display reconvergence
Display not suitable for large clock trees
Displays too many details

The Idea
Users are looking for a tool to better understand the
quality and structure of a clock tree
The tool should help debugging clock trees
Versus CTS constraints
Versus Physical implementation
Versus timing problems
Problems to be investigated
Skew
Latency
Balancing with other clocks
DRVs

We need a Graphical Clock tree

analysis tool
9

Solution
NEC and Cadence have a very close cooperation

So it was obvious to ask Cadence what they think

about a graphical clock tree analyzer

OK, lets do it

Phase 1 : Collecting ideas and specify the new tool

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Requirements 1

Global picture
Whole clock tree on a single page.

Representation
Timing oriented
Symbolic representation
Gating structure
Reconvergence

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Requirements 2
Display on a as-needed basis
Capability to expand/collapse a particular branch
To detail a branch through an instance
To a leaf
Expand/collapse by level of
gating
Buffer
Divergence point
Crossprobing
With layout
Design browser
Schematic

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Initial phase
Clock Tree Analyst window was available
2 month after specification review
Implemented function :
Clock tree extracted from cts spec file (.ctstch)
Whole clock tree on a single page
Based on CTS tracing/timing
Choice of preRoute, clkRouteOnly, postRoute
Unit delays when clock tree not built
Gates and leaves will be displayed
Reconvergence
Expand/Collapse on branches

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Clock tree analysis

Latency

Skew
Cross reference

Structure, Gating

Cadence feature CK Analyst helps to understand unexpected

effects in clock tree
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CK Analyst examples
Reasons for unexpected long latency/skew
in Clock Tree :

Reconvergence
Fixed cells
CLK Gating
CLK Grouping

15

Reconvergent clocks

Reconvergence

clk1
clk2
Structure, Gating

Check for doted line Best Solution: Insert cut point to CLK Spec file
Alternative : use reconvergence switch in FE (increase run time)
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Fixed cells in clock Tree

Cross reference

Fixed cells in clocktree could lead to big latency

Fixed cells will be displayed in a different color. Additionally check
CLK path using cross reference feature
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CLK Gating / Through cells

OCV aware clock gating

Common path

Through cell

Check for long common path to reduce OCV influence

Check timing placement for through cells

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Clock Grouping
cascade buffer

List of clock root points

clock gating

Check latency of different CLK groups

19

Backtracing

Easy debugging with backtracing

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Clock Tree Analyst

Will make clock tree debugging easier
Will be available in FE 7.1
For more information, please ask
you Cadence representative.
Special thanks to Thierry Sarrazin

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Any Questions ?