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SECTION B (3*10=30)
16. a. Draw & explain the architecture of 8085 microprocessor.
ARCHITECTURE OF 8085
All of the three flip flop set and reset according to the stored result in the accumulator.
1.Sign- If D7 of the result is 1 then sign flag is set otherwise reset. As we know that a number
on the D7 always desides the sign of the number.
if D7 is 1: the number is negative.
if D7 is 0: the number is positive.
2.Zeros(Z)-If the result stored in an accumulator is zero then this flip flop is set otherwise it is
reset.
3.Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output then it is set otherwise it
is reset.
4.Parity(P)-If the no of 1's is even in the output stored in the accumulator then it is set
otherwise it is reset for the odd.
5.Carry(C)-If the result stored in an accumulator generates a carry in its final output then it is
set otherwise it is reset.
Serial Input Output Control-There are two pins in this unit. This unit is used for serial data
communication.
Interrupt Unit-There are 6 interrupt pins in this unit. Generally an external hardware is
connected to these pins. These pins provide interrupt signal sent by external hardware to
microprocessor and microprocessor sends acknowledgement for receiving the interrupt signal.
Generally INTA is used for acknowledgement.
b. Draw the Pin Diagram of 8085 and explain the function of various signals.
PIN DIAGRAM
8085 is a general purpose microprocessor having 40 pins and works on single power supply.
To study the pin diagram we group
the signals into 5 categories:
1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports
1. Power supply and Clock frequency signals:
Vcc:
+ 5 volt power supply
Vss:
Ground
X1, X2 :
Crystal or R/C network or LC network connections to set the frequency of internal clock
generator. The frequency is internally divided by two. Since the basic operating timing
frequency is 3 MHz, a 6 MHz crystal is connected externally. CLK (output)-Clock
Output is used as the system clock for peripheral and devices interfaced with the
microprocessor.
2. Address Bus:
A8 - A15:
(output; 3-state) It carries the most significant 8 bits of the memory address or the 8 bits
of the I/O address
3. Data bus:
AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the lower
order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.
READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
The processor sets the READY signal after completing the present job to access the
data.
The microprocessor enters into WAIT state while the READY pin is disabled.
8. Single Bit Serial I/O ports:
SID (input)
- Serial input data line
SOD (output)
- Serial output data line
These signals are used for serial communication.
17. a. Explain the instruction format & instruction sets with suitable example.
Instruction Format
An instruction is a command to the microprocessor to perform a given task on a
specified data. Each instruction has two parts: one is task to be performed, called the operation
code (opcode), and the second is the data to be operated on, called the operand. The operand
(or data) can be specified in various ways. It may include 8-bit (or 16-bit ) data, an internal
register, a memory location, or 8-bit (or 16-bit) address. In some instructions, the operand is
implicit.
Instruction word size
The 8085 instruction set is classified into the following three groups according to word
size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.
One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are
internal register and are coded into the instruction.
For example:
These instructions are 1-byte instructions performing three different tasks. In the first
instruction, both operand registers are specified. In the second instruction, the operand B is
specified and the accumulator is assumed. Similarly, in the third instruction, the accumulator is
assumed to be the implicit operand. These instructions are stored in 8- bit binary format in
memory; each requires one memory location.
MOV rd, rs
rd <-- rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the
destination of the data, sss is the code of the source register.
Example: MOV A,B
Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction design of such
processors).
Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second byte
specifies the operand. Source operand is a data byte immediately following the opcode. For
example:
MNEMONICS
HEX CODE
MVI A,32
32,3H
Assume that the data byte is 32H. The assembly language instruction is written as
The instruction would require two memory locations to store in memory.
MVI r,data
r <-- data
Example: MVI A, 30H coded as 3EH 30H as two contiguous bytes. This is an example of
immediate addressing.
OUT port
Where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but points
directly to where it is located this is called direct addressing.
Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two
bytes specify the 16-bit address. Note that the second byte is the low-order address and the third
byte is the high-order address. Opcode + data byte + data byte
Example:
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.
LDA addr
A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H
21H. This is also an example of direct addressing.
b. With neat sketch explain the architecture of 8255.
INTEL introduced this programmable peripheral interface (PPI) chip 8255A for interfacing
peripheral devices to the 8085 system. This versatile chip 8255A is used as a general purpose
peripheral device for parallel data transfer between microprocessor and a peripheral device by
interfacing the device to the system data bus. The PPI has three programmable I/O ports viz.,
Port A, Port B and Port C each of 8 bit width. Port C can be treated as two ports Port C upper
(PC7-4) and Port lower (PC3 0) and these two can be independently programmed as INPUT or
OUTPUT ports also.
Salient Features
i.
It is a general purpose programmable I/O device which is compatible with all INTEL
processors and also most other processors.
ii. It provides 24 I/O pins which may be individually programmed in two groups.
iii. This chip is also completely TTL compatible.
iv. It is available in 40 pin DIP and 44 pin plastic leaded chip carrier (PLCC) packages.
v. It has three 8 bit ports. Port A, Port B and Port C. Port C is treated as two 4 bit ports
also.
vi. This 8255 is mainly programmed in two modes (a) the I/O mode and (b) The bit set/reset
mode (BSR) mode. The I/O mode is further divided into three modes: Mode 0, Mode 1,
and Mode 2.
vii. An 8 bit control resister is used to configure the modes of 8255.
There is also another 8 bit port called control port, which decides the configuration of
8255 ports. This port is written by the microprocessor only.
Pin Description
The 8255A is a 40 pin DIP chip which works at single + 5V DC. The pin diagram of
8255A chip is shown in Fig. The pin details of the chip are given below.
PA3
40
PA4
PA2
39
PA5
PA1
38
PA6
PA0
37
PA7
RD
36
WR
CS
35
Reset
GND
34
D0
A1
33
D1
A0
32
D2
31
D3
PC7
10
PC6
11
30
D4
PC5
12
29
D5
PC4
13
28
D6
PC0
14
27
D7
PC1
15
26
Vcc
PC2
16
25
PB7
PC3
17
24
PB6
PB0
18
23
PB5
PB1
19
22
PB4
PB2
20
21
PB3
8255A