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Y
Y
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Y
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Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC and PCC
TL/F/10193 1
TL/F/10193 2
TL/F/10193
RRD-B30M105/Printed in U. S. A.
9403A
April 1989
Logic Symbol
TL/F/10193 3
Description
U.L.
HIGH/LOW
Input IIH/IIL
Output IOH/IOL
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
285/26.7
285/26.7
20/13.3
20/13.3
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
5.7 mA/16 mA
5.7 mA/16 mA
b 400 mA/8 mA
b 400 mA/8 mA
Block Diagram
TL/F/10193 4
Functional Description
the F3 flip-flop and resetting the other flip-flops. The Q output of the last flip-flop (FC) is brought out as the Input Register Full output (IRF). After initialization this output is HIGH.
TL/F/10193 5
TL/F/101936
TL/F/10193 7
EXPANSION
Vertical ExpansionThe 9403A may be vertically expanded to store more words without external parts. The interconnection is necessary to form a 46-word by 4-bit FIFO are
shown in Figure 4 . Using the same technique, and FIFO of
TL/F/10193 8
Horizontal ExpansionThe 9403A can also be horizontally expanded to store long words (in multiples of four bits)
without external logic. The interconnections necessary to
form a 16-word by 12-bit FIFO are shown in Figure 5 . Using
the same technique, any FIFO of 16 words by 4n bits can be
constructed, where n is the number of devices. The IRF
output of the right most device (most significant device) is
connected to the TTS inputs of all devices. Similarly, the
ORE output of the most significant device is connected to
the TOS inputs of all devices. As in the vertical expansion
scheme, horizontal expansion does not sacrifice any of the
9403As flexibility for serial/parallel input and output.
Horizontal and Vertical ExpansionThe 9403A can be
expanded in both the horizontal and vertical directions without any external parts and without sacrificing any of its FIFOs flexibility for serial/parallel input and output. The interconnections necessary to form a 31-word by 16-bit FIFO are
shown in Figure 6 . Using the same technique, any FIFO of
(15m a 1)-words by (4n)-bits can be constructed, where m is
the number of devices in a column and n is the number of
devices in a row. Figures 7 and 8 show the timing diagrams
for serial data entry and extraction for the 31-word by 16-bit
FIFO shown in Figure 6 . The final position of data after serial insertion of 496 bits into the FIFO array of Figure 6 is
shown in Figure 9 .
Interlocking CircuitryMost conventional FIFO designs
provide status signals analogous to IRF and ORE. However,
when these devices are operated in arrays, variations in unit
to unit operating speed require external gating to assure all
devices have completed an operation. The 9403A incorporates simple but effective master/slave interlocking circuitry to eliminate the need for external gating.
In the 9403A array of Figure 6 devices 1 and 5 are defined
as row masters and the other devices are slaves to the
TL/F/10193 9
TL/F/10193 10
TL/F/10193 11
TL/F/10193 12
TL/F/10193 13
TL/F/10193 14
10
Recommended Operating
Conditions
b 65 C to a 150 C
b 55 C to a 125 C
b 55 C to a 125 C
0 C to a 70 C
Supply Voltage
Military
Commercial
b 55 C to a 175 C
a 4.5V to a 5.5V
a 4.5V to a 5.5V
b 0.5V to a 7.0V
b 0.5V to a 7.0V
Input Voltage (Note 2)
b 30 mA to a 5.0 mA
Input Current (Note 2)
Voltage Applied to Output
in HIGH State (with VCC e 0V)
b 0.5V to VCC
Standard Output
b 0.5V to a 5.5V
TRI-STATE Output
Current Applied to Output
in LOW State (Max)
twice the rated IOL (mA)
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
VIH
VIL
VCD
VOH
Output HIGH
Voltage
Output LOW
Voltage
VOL
Min
Typ
Max
2.0
Units
VCC
V
0.8
b 1.5
Conditions
Recognized as a HIGH Signal
Recognized as a LOW Signal
Min
IIN e b18 mA
Min
IOH
IOH
IOH
IOH
e
e
e
e
0.4
0.4
0.5
0.5
Min
IOL
IOL
IOL
IOL
e
e
e
e
4 mA (IRF, ORE)
8 mA (Qn, Qs)
8 mA (IRF, ORE)
16 mA (Qn, Qs)
2.4
2.4
2.4
2.4
IIH
40
mA
Max
VIN e 2.7V
IBVI
100
mA
Max
VIN e 7.0V
IIL
b 0.45
mA
Max
VIN e 0.4V
IOZH
100
mA
Max
VOUT e 2.4V
IOZL
b 100
mA
Max
VOUT e 0.5V
b 130
mA
Max
VOUT e 0V
b 30
IOS
ICEX
250
mA
Max
VOUT e VCC
ICCL
170
mA
Max
VO e LOW
11
AC Electrical Characteristics
Symbol
tPHL
tPLH
Parameter
Comm
Mil
Comm
TA e a 25 C
VCC e a 5.0V
CL e 50 pF
Min
Max
Min
Max
Min
Max
Propagation Delay,
Negative-Going
CPSI to IRF Output
1.5
20.0
1.5
29.0
1.5
21.0
Propagation Delay,
Negative-Going
TTS to IRF
1.5
36.0
1.5
46.0
1.5
38.0
Units
Fig.
No.
ns
9403A-a , b
tPLH
tPHL
Propagation Delay,
Negative-Going
CPSO to QS Output
1.5
1.5
28.0
28.0
1.5
1.5
33.0
33.0
1.5
1.5
29.0
29.0
ns
9403A-c, d
tPLH
tPHL
Propagation Delay,
Positive-Going
TOP to Outputs Q0 Q3
1.5
1.5
46.0
46.0
1.5
1.5
53.0
53.0
1.5
1.5
48.0
48.0
nsd
9403A-e
tPHL
Propagation Delay,
Negative-Going
CPSO to ORE
1.5
35.0
1.5
41.0
1.5
37.0
ns
9403A-c, d
Propagation Delay,
Negative-Going
TOP to ORE
1.5
37.0
1.5
45.0
1.5
39.0
ns
9403A-e
Propagation Delay,
Positive-Going
TOP to ORE
1.5
47.0
1.5
53.0
1.5
49.0
Propagation Delay,
Negative-Going
TOS to Positive Going ORE
1.5
42.5
1.5
50.0
1.5
45.0
ns
9403A-c, d
Propagation Delay,
Positive-Going
PL to Negative-Going IRF
1.5
28.0
1.5
36.0
1.5
29.0
ns
9403A-g, h
Propagation Delay,
Negative-Going
PL to Positive-Going IRF
1.5
tPHL
tPLH
tPLH
tPHL
tPLH
24.0
1.5
12
29.0
1.5
25.0
AC Electrical Characteristics
Symbol
Parameter
74F
54F
74F
TA e a 25 C
VCC e a 5.0V
CL e 50 pF
Units
Min
Max
Min
Max
Min
Max
Propagation Delay,
Positive-Going
OES to ORE
1.5
39.5
1.5
38.0
1.5
41.0
ns
Propagation Delay,
Positive-Going
IES to Positive-Going IRF
1.5
20.0
1.5
25.0
1.5
21.0
ns
tPLH
Propagation Delay,
MR to IRF
1.5
20.0
1.5
20.0
1.5
20.0
ns
tPHL
Propagation Delay,
MR to ORE
1.5
33.0
1.5
43.0
1.5
35.0
ns
tPZH
tPZL
Propagation Delay,
OE to Q0, Q1, Q2, Q3
1.5
1.5
14.0
14.0
1.0
1.0
25.0
25.0
1.5
1.5
14.0
14.0
tPHZ
tPLZ
Propagation Delay,
OE to Q0, Q1, Q2, Q3
1.5
1.5
14.0
14.0
1.0
1.0
25.0
25.0
1.5
1.5
14.0
14.0
tPZH
tPZL
Propagation Delay,
Negative-Going
OES to QS
1.5
1.5
16.5
17.0
1.0
1.0
30.0
30.0
1.5
1.5
17.0
17.0
tPHZ
tPLZ
Propagation Delay,
Negative-Going
OES to QS
1.5
1.5
14.0
14.0
1.0
1.0
30.0
30.0
1.5
1.5
14.0
14.0
tPZH
tPZL
Turn On Time
TOS to Qs
1.5
1.5
60.0
60.0
1.5
1.5
60.0
60.0
1.5
1.5
60.0
60.0
ns
tDFT
500
ns
tAP
tAS
tDBU
Bubble-Up Time
tPLH
tPLH
Fig.
No.
9403A-h
ns
ns
500
500
b 19.0
6.5
b 20.0
10.0
b 20.0
7.0
b 9.5
14.5
b 20.0
25.0
b 10.0
15.0
ns
470
500
13
500
ns
9403A-f
AC Operating Requirements
Symbol
Parameter
74F
54F
74F
TA e a 25 C
VCC e a 5.0V
Min
Min
Max
Max
Min
Units
Fig.
No.
ns
9403A-a, b
Max
ts(H)
ts(L)
15.5
15.5
30.0
30.0
16.0
16.0
th(H)
th(L)
2.0
2.0
8.0
8.0
2.0
2.0
ts(L)
18.0
50.0
18.0
ns
9403A-b
ts(L)
65.0
110.0
70.0
ns
9403A-b
ts(H)
ts(L)
0
0
1.0
1.0
0
0
th(H)
th(L)
0
0
6.0
6.0
0
0
tw(H)
tw(L)
30
20
52.0
25.0
32
20
ns
tw(H)
16.5
20.0
17.0
ns
9403A-g, h
tw(L)
16.0
20.0
17.0
ns
9403A-a, b,
c, d
tw(L)
15.0
20.0
15.0
ns
9403A-f
tw(H)
tw(L)
15.0
15.0
22.0
20.0
17.0
15.0
ns
9403A-e
tw(H)
tw(L)
17.0
17.0
20.0
20.0
17.0
18.0
ns
9403A-c, d
trec
Recovery Time
MR to Any Input
16.5
25.0
19.0
ns
9403A-f
14
ns
9403A-a, b
Timing Waveforms
TL/F/10193 15
TL/F/10193 16
TL/F/10193 17
Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW
15
TL/F/10193 18
TL/F/10193 19
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
TL/F/10193 20
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
16
TL/F/10193 21
FIGURE 9403A-g. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
TL/F/10193 22
Conditions: stack not full, device initialized (Note 1) with IES HIGH
17
Order Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/10193 23
18
19
9403A
Lit. 103753
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.