Wassenaar, R.F., et al.

"Operational Transconductance Amplifiers"

The VLSI Handbook.
Ed. Wai-Kai Chen
Boca Raton: CRC Press LLC, 2000

2000 by CRC PRESS LLC

22
Operational
Transconductance
Amplifiers
R.F. Wassenaar
University of Twente

Mohammed Ismail
The Ohio State University

Chi-Hung Lin
The Ohio State University

22.1
22.2
22.3
22.4

Introduction
Noise Behavior of the OTA
An OTA with an Improved Output Swing
OTAs with High Drive Capability
OTAs with 1:B Current Mirrors OTA with Improved Output
Stage Adaptively Biased OTAs Class AB OTAs

22.5 Common-Mode Feedback

22.6 Filter Applications with Low-Voltage OTAs

22.1 Introduction
In many analog or mixed analog/digital VLSI applications, an operational amplifier may not be
appropriate to use for an active element. For example, when designing integrated high-frequency
active filter circuitry, a much simpler building block, called an operational transconductance amplifier
(OTA), is often used.1 This type of amplifier is characterized as a voltage-driven current source and
in its simplest form is a combination of a differential input pair with a current mirror as shown in
Fig. 22.1. It is a simple circuit with a relatively small chip area. Further, it has a high bandwidth and
also a good common-mode rejection ratio up to very high frequencies. The small signal transconductance, gm = Iout/Vin, can be controlled by the tail current. This chapter discusses CMOS OTA
design for modern VLSI applications. We begin the chapter with a brief study of noise in OTAs,
followed by OTA design techniques.

22.2 Noise Behavior of the OTA

The noise behavior of the OTA is discussed here. Attention will be paid to thermal and flicker noise
and to the fact that, for minimal noise, some voltage gain, from the input of the differential pair to
the input of the current mirror, is required. Then, only the noise of the input pair becomes dominant
and the other noise sources can be neglected to first order. The noise behavior of a single MOS
transistor is modeled by a single noise voltage source. This noise voltage source is placed in series
with the input (gate) of a noiseless transistor. Fig. 22.2(a) shows the simple OTA, including the
noise sources, while Fig. 22.2(b) shows the same circuit with all the noise referred to the input of
the stage.

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FIGURE 22.1 (a) A NMOS differential pair with a PMOS current mirror forming an OTA; (b) the symbol for a
single-ended OTA; and (c) the symbol for a fully differential OTA.

FIGURE 22.2 (a) The OTA with its noise voltage sources, and (b) the same circuit with the noise voltage sources
referred to one of the input nodes.

All the noise sources indicated in Fig. 22.2(a) are converted to equivalent input noise voltags, which
are then added to form a single noise source at the input (Fig. 22.2(b)). As a result, we obtain (assuming
gm1 = gm2 and gm3 = gm4) the following mean-square input referred noise voltage

g m3 2
2
2
2
- ( V p3 2 + V p4 2 )
V eq = V n1 + V n2 + ----- g m1

2000 by CRC Press LLC

(22.1)

The thermal noise contribution of one transistor, over a band f, is written as:

2
1
2
V th = --- 4kT ----- f
3
gm

(22.2)

where k is the Boltzman constant and T is the absolute temperature.

The equivalent noise voltage V theq 2 becomes:

g m3 2 1
2
1
1
1
2
V theq = --- 4kT ------- + ------- + ------------ + ------- f
g m1 g m2 g m1 g m3 g m4
3

(22.3)

and because gm1 = gm2 and gm3 = gm4, V theq becomes:

g m3 2 1
16
1
2
- ------- f
V theq = ------ kT ------- + ----- g m1 g m1 g m3
3

(22.4)

g m3
16 kT
2
V theq = ------ ------- 1 + ------ f
3 g m1
g m1

(22.5)

or

Expressing gm in physical parameters results in:

p ( W L ) 3
16kT
2
- f
V theq = --------------------------------------------- 1 + -----------------------
n ( W L ) 1
3 n C ox ( W L ) 1 I 0

(22.6)

In this equation, I0 represents the tail current of the differential pair. Note that the term between brackets
represents the relative noise contribution of the current mirror. This term can be neglected if M3 and M4
are chosen relatively long and narrow in comparison to M1 and M2.
It should be mentioned that the thermal noise of an N-MOS transistor and a P-MOS transistor with
equal transconductance is the same. In most standard IC processes, a three to ten times lower 1/f noise
is observed for P-MOS transistors in comparison to N-MOS transistors of the same size. However, in
modern processes, the 1/f noise contribution of N- and P-MOS transistors tends to be equal.
For the 1/f noise, it is usually assumed for standard IC processes that:

K
2
V 1 f = ------------------f
WLC ox f

(22.7)

where K is the flicker noise coefficient in the range of 1024 J for N-MOS transistors and in the range
of 3 1025 to 1025 J for P-MOS transistors. The equivalent 1/f input noise source of the OTA in Fig.
22.2(b) yields:
2
2K n f
K p p L 1
2
1 + -------------------V eq ( 1 f ) = ----------------------2
W 1 L 1 C ox f
K n n L 3

(22.8)

Here, the noise contributions of the current mirror (M3, M4) will be negligible if L3 is chosen much larger
than L1.

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The offset voltage of a differential pair is lowest when the transistors are in the weak-inversion mode;
but on the contrary, the mismatch in the current transfer of a current mirror is lowest when the transistors
are deep in strong inversion. Hence, the conditions that have to be fulfilled for both minimal equivalent
input noise and minimal offset are easy to combine.

22.3 An OTA with an Improved Output Swing

A CMOS OTA with an output swing much higher than that in Fig. 22.1(a) is shown in Fig. 22.3. This
configuration needs two extra current mirrors and consumes more current, but the output voltage
window is, in the case when common-mode input voltage is zero, about doubled. The rules discussed
earlier for sizing the input transistors and current-mirror transistors to reduce noise and offset still apply.
However, there is still a tradeoff. On the one hand, a high voltage gain from the input nodes to the
current mirror is good for reducing noise and mismatch effects; on the other hand, too much gain also
reduces the upper limit of the common-mode input voltage range and the phase margin needed to ensure
stability (this will be discussed later).2 A voltage gain on the order of 3 to 10 is advised. The frequency
behavior of the OTA in Fig. 22.3 is rather complex since there are two different signal paths in parallel,
as shown in Fig. 22.4. In this scheme, rp represents the parallel value of the output resistance of the stage
(ro6||ro8) and the load resistance (RL); therefore,

r p = r o6 || r o8 || R L

FIGURE 22.3 An OTA with an improved output window.

FIGURE 22.4 The signal paths of the OTA in Fig. 22.3.

2000 by CRC Press LLC

(22.9)

FIGURE 22.5 (a) The Bode plot belonging to signal path 1 in the OTA in Fig. 22.3 and 22.4, (b) signal path 2, and
(c) to the combined signal path.

The capacitor Cp represents the sum of the parasitic output capacitance and the load capacitance Cp
= Co + CL. Using the half-circuit principle for the differential pair, a fast signal path can be seen from
M2 via current mirror M7, M8 to the output. This signal path contributes an extra high-frequency pole.
The other signal path leads from transistor M1 via both current mirrors M3, M4 and M5, M6 to the output.
In this path, two extra poles are added. The transfer of both signal paths and their combination are
shown in the plots in Fig. 22.5, assuming equal pole positions of all three current mirrors. Note that the
first (dominant) pole (1) is determined by rp and Cp.

1
1 = ---------rp Cp

(22.10)

The second pole (2) is determined by the transconductance of M3 and the sum of the gate-source
capacitance of M3 and M4. If M3 and M4 are equal, the second pole is located at:

g m3
2 = ----------2C gs3

(22.11)

The unity-gain corner frequency T of the loaded OTA is at:

g m1
T = -----Cp

(22.12)

g m3 C p

- -----------------2 = -----g m1 2C gs3

T

(22.13)

Therefore, the ratio 2/T is:

When the OTA is used for high-frequency filter design, an integrator behavior is required, that is, a
constant 90 phase at least at frequencies around T. Therefore, a high value of the ratio 2/T is needed
in order to have as little influence as possible from the second pole. It is obvious from Eq. 22.12 that the

2000 by CRC Press LLC

low-frequency voltabe gain from the input nodes of the circuit to the input of the current mirrors (=
gm1/gm3) must not be chosen too high. As mentioned, this is in contrast to the requirements for minimum
noise and offset.
Sometimes, OTAs are used as unity gain voltage buffers; for example, in switched capacitor filters. In
this case, the emphasis is put more on obtaining high open-loop voltage gain, improved output window,
and good capability to drive capacitive loads efficiently (or small resistors); its integrator behavior is of
less importance.
To increase the unloaded voltage gain, cascode transistors can be added in the output stage. This greatly
increases the output impedance of the OTA and hardly decreases the phase margin. The penalty that has
to be paid is an additional pole in the signal path and some reduction of the maximum possible output
swing. This reduction can be very small if the cascode transistors are biased on the weak-inversion mode.
The open-loop voltage gain can be in the order of 40 to 60 dB. A possible realization of such a configuration is shown in Fig. 22.6.3

FIGURE 22.6 An OTA with improved output impedance.

22.4 OTAs with High Drive Capability

For driving capacitive loads (or small resistors), a large available output current is necessary. In the
OTAs shown so far, the amount of output current available is equal to twice the quiescent current
(i.e., the tail current I0). In some situations, this current can be too small. There are several ways to
increase the available current in an efficient way. To achieve this, four design principles will be
discussed here:
1. Increasing the quiescent current by using current mirrors with a current transfer ratio greater
than 1
2. Using a two-transistor level structure to drive the output transistors
3. Adaptive biasing techniques
4. Class AB techniques

OTAs with 1:B Current Mirrors

One way to increase available output current is to increase the transfer ratio of the current mirrors CM1
and CM2 by a factor B, as indicated in Fig. 22.7.4 The amount of available output current and also the
overall transconductance increase by the same factor. Unfortunately, the 3 dB frequency of the CM1CM2 current mirrors will be reduced by a factor (B + 1)/2 due to the larger gate-source capacitance of
the mirror output transistors. Moreover, T will increase, 2 will decrease, and the ratio 2/T will be

2000 by CRC Press LLC

FIGURE 22.7 An OTA with improved load current using 1:B current mirrors.

strongly deteriorated. The amount of available output current though is B times the tail current. It is
also possible to increase the current transfer ratio of current mirror CM3 instead of CM1. A better
current efficiency then results, but at the expense of more asymmetry in the two signal paths. Although
the amount of the maximum available output current is B times the tail current in both situations, the
ratio between the maximum available current and quiescent current of the output stage remains equal
to two, just as in the OTAs discussed previously.

OTA with Improved Output Stage

Another way of increasing the maximal available output current is illustrated in Fig. 22.8.6 It improves
upon the factor-two relationship between quiescent and maximal available current. Assuming equal K
factors for all transistors shown in the circuit leads to the conclusion that the effective gate-source voltage
of transistor M11 (= VGS11 VT11) equals that of transistor M1 (=VGS1 VT1), since they carry the same
current, assuming that transistors M1, M4, and M6 are in saturation. Because the current drawn through
transistor M9 is equal to the current in transistor M2, their effective source-gate voltages must also be
equal assuming equal K factor for M2 and M9. Since the sum of the effective gate-source voltages transistors
M11 and M12, and also of M9 and M10, is fixed and equal to VB, a situation exists which is equivalent to
the two transistor level structure described in Ref. 5.

FIGURE 22.8 An OTA with an improved ratio between the maximum available current and the quiescent current
of the output stage.

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The ratio between the maximum available output current and the quiescent current of the output
2
stage can be chosen by the designer. It is equal to: ( V B ( V B V GS0 ) ) , where VGS0 is the quiescent gatesource voltage of transistor M11.
If the OTA is used in an over-drive situation |Vin| > ( 2I 0 ) K , then either M6 or M5 will be cut off,
while the other transistor carries its maximum current. As a result, one of the output transistors (M10 or
M12) carries its maximum current, while the other transistor is in a low-current stand-by situation. The
maximum current that one of the output transistors carries is therefore proportional to VB2. With the
high ohmic resistor R (indicated in Fig. 22.8 with dotted lines), this maximum current corresponds to
either (VP VSS VTN)2 or (VDD VQ VTP)2, because in that situation no current flows through the
resistor. Hence, with the extra resistor, it becomes possible to increase the maximum current in overdrive situations and therefore reduce the slewing time. Because resistor R is chosen to be high, it does
not disturb the behavior of the circuit discussed previously. In practice, resistor R is replaced by transistor
MR working in the triode region, as shown in Fig. 22.9(a). Figure 22.9(b) shows the circuit which was
used in Ref. 5 for biasing the gates of transistors M0, M9, and M11. It is much like the so-called replica
biasing. The current in the circuit is strongly determined by the voltage across R (and its value) and is
therefore very sensitive to variations in the supply voltage.

FIGURE 22.9 (a) The complete OTA, (b) and its bias stage.

Adaptively Biased OTAs

Another combination of high available output current with low standby current can be realized by making
the tail current of the differential input pair signal dependent. Figure 22.10 shows the basic idea of such
an OTA with adaptive biasing.7 The tail current I0 of the differential pair is the sum of a fixed value IR
and an additional current equal to the absolute value of the difference between the drain currents
multiplied by the current feedback factor B (I0 = IR + B|I1 I2|). Therefore, with zero differential input
voltage, only a low bias current IR flows through the input pair. A differential input voltage, Vind, will
cause a difference in the drain currents which will increase the tail current. This, in turn, again gives rise
to a greater difference in the drain current, and so on. This is the kind of positive feedback that can bring
the differential input pair from the weak-inversion mode into the strong-inversion mode, depending on
the input voltage and the chosen current feedback factor B.
Normally, when Vind = Vin+ Vin is small, the input transistors are in weak inversion. The differential
output current (I1 I2) of a differential pair operating in weak inversion equals the tail current times
tanh( ( qV ind ) ( 2AkT ) ). This leads to the following equation:

qV ind
( I 1 I 2 ) = I R + B I 1 I 2 tanh ------------ 2AkT

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(22.14)

FIGURE 22.10

An OTA with an input dependent tail current.

or

qV ind
tanh ------------ 2AkT
( I 1 I 2 ) = ----------------------------------------------I R
qV ind
1 B tanh ------------ 2AkT

(22.15)

and because Iout = (I1 I2):

I out

qV ind
tanh ------------ 2AkT
= ----------------------------------------------I R
qV ind
1 B tanh ------------ 2AkT

(22.16)

However, in the case of large currents, this expression will no longer be valid since M1 M2 will
leave the weak-inversion domain and enter the strong-inversion region. If that is the case, the output
current becomes:

I out

k
--- V ind
2
=
k
--2- V ind

4I R
K
2
2
2
------- ( 1 B )V ind + B ---V ind
2
K
4I
K
2
2
2
------R- ( 1 B )V ind B ---V ind
2
K

for V ind > 0

for V ind < 0

(22.17)

In order to keep some control over the output current, a negative overall feedback must be applied, which
is usually the case. For example, when an OTA is used as a unity-gain buffer with a load of CL (see Fig. 22.11)
and assuming a positive input step is applied, then the output current increases dramatically due to the
positive feedback action described previously and, as a result, the output voltage will increase. This will lead
to a decrease of the differential input voltage Vind (Vind = Vs Vout). The result will be a very fast settling of
the output voltage, and that is what we wanted to have. In order to realize current |I1 I2|, two currentsubtracter circuits can be combined (see Fig. 22.12). If the current I2 is larger than current I1, the output of
current-subtracter circuit 1 (Iout1) will carry a current; otherwise, the output current will be zero. The opposite
situation is found for the output current of subtracter circuit 2 because of the interchange of their input

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FIGURE 22.11

An OTA used as a unity gain buffer.

currents (Iout2 = B(I1 I2)). Consequently, either Iout1 or Iout2 will draw a current B|I1 I2| and the other current
will be zero. It is for this reason that the upper current mirrors (in Fig. 22.13) have two extra outputs to
support the currents for the circuit in Fig. 22.12. A practical realization of the adaptive biasing OTA is shown
in Fig. 22.13. In order to avoid unwanted, relatively high stand-by currents due to transistors mismatches,
the transfer ratio of the current mirrors (M12, M13) and (M19, M18) can be chosen somewhat larger than 1.
This ensures an inactive region of the input voltage range whereby the feedback loop is deactivated.

FIGURE 22.12
in Fig. 22.10.

A combination of two current subtracters for realizing the adaptive biasing current for the circuit

FIGURE 22.13

A practical realization of OTA with an adaptive biasing of its tail current.

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FIGURE 22.14

An OTA using a minimum selector for adapting the tail current.

Another example of an adaptive tail current circuit is shown in Fig. 22.14.8 It has a normal OTA
structure except that the input pair is realized in twofold, and the tail current transistor is used in a
feedback loop. This feedback loop includes the inner differential pair and tail current transistor M0 as
well as a minimum current selector, the current source IU, transistor MR, and a current sink IL. The
minimum current selector9 delivers an output current equal to the lowest value of its input currents (Iout
= Min(I1, I2)). The feedback loop ensures that the output current of the minimum current selector is
equal to the difference in currents between the upper and lower current sources. Assume that the upper
current carries a current 2IB and the lower current source carries IB, then the feedback loop will bias the
tail current in such a way that either I1 or I2 becomes equal to IB; for positive values of Vind, that will be
I2. It should be realized that at Vind = 0, all four input transistors are biased at the same gate-source
voltage (VGS0), corresponding to a drain current IB. In the case of positive input voltages, the gate-source
voltage of M2/M2 will not change.
Therefore, all the input voltage will be added to the bias voltage of M1/M1, that is,

V GS1 = V GS0 + V ind

(22.18)

Figure 22.15 shows the ID vs. VGS characteristic for both transistors M1/M1 and M2/M2. Accordingly, the
relationship between (I1 I2) vs. Vind (for Vind > 0) follows the right side of the ID VGS curve of M1,

FIGURE 22.15

The ID vs. VGS characteristic for transistors M1/M1 and M2/M(2, showing their standby point VGS0, IB.

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FIGURE 22.16

I1 I2 vs. Vind.

starting from the stand-by point (VGS0, IB) as indicated by the solid curve in Fig. 22.15. A similar view
can be taken for negative values of the input voltage Vind, resulting in an equal (I1 I2) vs. Vin curve
rotated 180. The result is shown in Fig. 22.16.
Note that this input stage has a relationship between (I1 I2) and Vind that is different from that of a
simple differential input stage. By increasing Vind, the slope increases and, to a first-order approximation,
there will not be a limit for the maximum value of (I1 I2).
Note that there is an additional MOS transistor MR in the circuit in Fig. 22.14 to fix the output voltage
of the minimum current selector circuit. The lower current source IL is necessary to be able to discharge
the gate-source capacitor C of M0 (indicated in Fig. 22.14 with dotted lines). The OTA in Fig. 22.14 is
simpler than that in Fig. 22.13. However, its bandwidth is lower due to the high impedance of node P
in the feedback loop.

Class AB OTAs
Another possibility to design an OTA with a good current efficiency is to use an input stage exhibiting
a class AB characteristics.11 The input stage in Fig. 22.17 contains two CMOS pairs12 connected as Class
AB input transistors. They are driven by four source-followers. By applying a differential input voltage,

FIGURE 22.17

An OTA having a class AB input stage.

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the current through one of the input pairs will increase while the current through the other will decrease.
The maximum current that can flow through the CMOS pair is, to first order, unlimited. In practice, it
is limited by the supply voltage, the Keq factor, the mobility reduction factor, and the series resistance.
The currents are delivered to the output with the help of two current mirrors. In the OTA shown in Fig.
22.17, only one of the two outputs of each CMOS pair is used. The other output currents flow directly
to the supply rails. Instead of wasting the other output currents, they can be used to supply an extra
output. So with the addition of two current mirrors, an OTA with complementary outputs as shown in
Fig. 22.18 can be achieved.10 An improvement of the output impedance and low-frequency voltage gain
can be obtained by cascoding the output transistors of the current mirrors (Fig. 22.19). Usually, this
reduces the output window. The function of transistors M41-M44 is to control the dc output voltages.
They form a part of a common-mode feedback system, which will be discussed next.

FIGURE 22.18

An OTA having a class AB input stage and two complementary outputs.

FIGURE 22.19

An improved fully differential OTA. (From Ref. 10. With permission.)

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The relationship between the differential input voltage Vin and one of the output currents Iout is shown
in Fig. 22.20. There is a linear relationship between Vind and Iout for small to moderate values of Vind. In
the case of larger values of Vind, one of the CMOS pairs becomes cut off, resulting in a quasi-quadratic
relationship. At a further increase of Vind, the output current will be somewhat saturated due to mobility
reduction and to the fact that one of the transistors of the CMOS pair leaves saturation mode. The latter
effect is, of course, also strongly dependent on the common input voltage.

FIGURE 22.20

The Vin Iout characteristic of the OTA in Fig. 5.19.

22.5 Common-Mode Feedback

A fully differential OTA circuit, as in Fig. 22.19, has many advantages compared with its single-ended
counterpart. It is a basic building block in filter design. A fully differential approach, in general, leads to
a more efficient current use, doubling of the maximum output-voltage swing, and an improvement of
the power-supply rejection ratio (PSRR). It also leads to a significant reduction of the total harmonic
distortion, since all even harmonics are canceled out due to the symmetrical structure. Even when there
is a small imperfection in the symmetry, the reduction in distortion will be significant.
However, this type of symmetrical circuit needs an extra feedback loop. The feedback around a
single-ended OTA usually only provides a differential-mode feedback and is ineffective for commonmode signals.
So, in the case of the fully differential OTA, a common-mode feedback (CMFB) circuit is needed to
control the common output voltage. Without a CMFB, the common-mode output voltage of the OTA
is not defined and it may drift out of its high-gain region. The general structure of a simple OTA circuit
with a differential output and a CMFB circuit is shown in Fig. 22.21. The need for a CMFB circuit is a
drawback since it counters many of the advantages of the fully differential approach. The CMFB circuit
requires chip area and power, introduces noise, and limits the output-voltage swing.
Figure 22.22(b) shows a simple implementation of a CMFB circuit. A differential pair (M1, M2) is used
to sense the common-mode output voltage. So, the voltage at the common source of this differential pair
(Vs) is used. Its voltage provides, with a level shift of one VGS, the common-mode output voltage of the
OTA. The voltage at this node is the first order insensitive to the differential input voltage. The relationship
between the differential input voltage Vin of the differential pair, superimposed on a common-mode input
voltage VCM, and its common-source voltage Vs is shown in Fig. 22.22(a). The common-mode output

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FIGURE 22.21

The general structure of a simple OTA circuit having a differential output and the required CMFB.

voltage of the OTA is determined by the VGS of M1/M2 and M9/M10 and can be controlled by the voltage
source V0. There might be an offset in the dc value of the two output voltages due to a mismatch in
transistors M9 and M10.
If the amplitude of the differential output voltage increases, the common-mode voltage will not remain
constant, but will be slightly modulated by the differential output voltage, with a modulation frequency
that is twice the differential input signal frequency. This modulation is caused by the non-flat characteristic of the Vs vs. Vin characteristic of the differential pair (M1, M2) (see Fig. 22.22(a)).

FIGURE 22.22 (a) The relationship between the differential input voltage, superimposed on a common-mode
voltage VCM of a differential pair (M1, M2) and its common-source voltage Vs; (b), a fully differential OTA with the
differential pair (M1, M2) for providing a common-mode feedback.

Another commonly used CMFB circuit is shown in the fully-differential folded cascode OTA in Fig.
22.23.13 In this circuit, a similar high-output resistance and high unloaded voltage gain can be achieved
as in the normal cascode circuits. An advantage of the folded cascode technique, however, is a higher

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FIGURE 22.23

A fully differential folded cascode OTA with another commonly used CMFB circuit.

accuracy in the signal-current transfer because current mirrors are avoided. In Fig. 22.23, all transistors
are in saturation, with the exception of M1, M11, and M12, which are in the triode region. The CMFB is
provided with the help of M11 and M12. These two transistors sense the output voltages VP and VQ. Since
they operate in the triode region, their sum-current is insensitive to the differential output voltage (VP
VQ) and depends only on the common output voltage ((VP+VQ)/2). Because the current that flows
through M17 and M18 forces the value of the above-mentioned sum-current, they also determine, together
with Vbias4, the common-mode output voltage. By choose Vbias1 in such a way that IM19 is twice IM17, and
making the width of transistor M1 twice that of M11 (= M12), the nominal common-mode output voltage
will be equal to the gate voltage of M1.

22.6 Filter Applications with Low-Voltage OTAs

Usually, gm-C filters are considered suitable candidates for high-speed and low-power applications.
Compared with the SC op-amp and RC op-amp techniques, the applicability of the gm-C filter is
limited by the low dynamic range and medium, even poor, linearity. The strategy of both simplifying
the architecture and designing an ultra-low-voltage OTA16 are used to meet low-power and dynamic
range requirements. The filter topology is derived from a passive ladder form of 5th-order elliptic
filtering. Using element replacement and sharing multiple inputs for gyrators, a fully differential 5thorder elliptic filter is shown in Fig. 22.24.14 This multi-input sharing in the filter design reduces the
numbers of OTAs from 11 to 6. Especially for wide bandwidth design, the method saves almost half
of the die area and power dissipation. This design uses balanced signals to reduce even harmonics
and to relax parasitic matching requirements. The capacitors realizing the filter poles are connected
between the outputs of the transconductors and signal ground. This helps the stability of the commonmode feedback circuit because of the loading to both common-mode and fully-differential signal
paths> The inherent 6 dB loss at low frequency is compensated for by the first transconductor with
2gm gain. Fig. 22.25 shows the frequency response and the passband of the filter. The filter has 3dB
frequency tuning ranges of 1.2 MHz to 2.9 MHz and 60 dB stop band rejection. Obviously, the
tuning range is limited by the low-power supply rail. This presents a problem for automatic tuning
design at very low supply voltages. A possible application for this filter is for channel selection in
wideband handy phones.15

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FIGURE 22.24

A gm-C elliptic filter with low-voltage OTAs.

FIGURE 22.25

Frequency response and passband of the filter.

2000 by CRC Press LLC

References
1. M. Ismail and T. Fiez, Analog VLSI Signal and Information Processing, McGraw-Hill, 1994.
2. E. A. Vittoz, The design of high-performance analog circuits on digital CMOS chips, IEEE J. SolidState Circuits, vol. SC-20, pp. 657-665, June 1985.
3. F. Krummenacher, High voltage gain CMOS OTA for micro-power SC filters, Electronics Letters,
vol. 17, pp. 160-162, 1981.
4. M. S. J. Steyaert, W. Bijker, P. Vorenkamp, and J. Sevenhans, ECL-CMOS and CMOS-ECL Interface
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