THE WIRE

In the first lessons we have studied the main devices of the CMOS process, i.e., the MOS transistor as main
element and the diode as parasitic element. In truth, in digital integrated circuits, there is another parasitic
element: the wire. This element is acquiring more and more importance as the device dimensions shrink
and the operating frequency is increased. Until now, we have already considered the wire as a short circuit,
a simple line carrying the signals with no apparent effect on circuit performance. Actually, the wire is a
mixture of resistances, inductances and capacitances. Be aware that these elements are not located in a
specific point, but they are rather distributed over the length of the wire.
The effects of these parasitics on digital circuits are:
1. an increase in propagation delay or, equivalently, a drop in dynamic performance;
2. an increase of the energy dissipation (due to the capacitance associated to the wire);
3. an introduction of extra noise sources, which affects the reliability of the circuit, due for example to
the capacitive coupling between adjacent wires.
In this lesson we will focus on the effect of a wire in terms of propagation delay.
Let us make an example to understand how complex is the modeling of the interconnection sketching a
simple wire, for example in metal 1, supposing that this interconnect is built near another wire in metal 1.
No other interconnections are present. Obviously, we need to consider the substrate that acts as a ground
plane. Its a very simplistic case. The most complete model of this wire has to take into account the
inductance, the resistance and the capacitance that are distributed over the length of the line, as well as
the coupling capacitances. The resulting model is very complex!

Now the question is: is it worthwhile to consider all these parasitics to assess the contribution of a wire?
Obviously the answer is negative, especially for a first order and hand-made analysis.
In order to simplify the problem of modeling a wire, we must consider three important rules:
1) Inductance can be neglected if the wire resistance is large or if the rise/fall time of the input
signal is large.
We will come back to this point later, when we briefly analyze the transmission line model. In
general, in an integrated circuit the inductance of the line can be neglected. It becomes an issue
only at board level where the wire resistance is small and the time-of-flight of the electromagnetic
wave is no longer negligible or for advanced technologies where low-resistivity material, such
copper, is used for the interconnections.
2) When the wire is short and when the equivalent resistance of the driver is large, the wire
resistance can be serenely neglected.
In this case, the wire is a capacitance. The wire can be modeled with a capacitance to ground or
with capacitances to the neighboring wires. The latter can give rise to coupling effect worsening the
reliability of the circuit.
3) When the separation between nearby wires is large or when the wires run for a short distance,
the inter-wires capacitance can be neglected.
The designer must own the ability to discriminate between dominant and secondary effects and to choose
between different models. Now, lets discuss more in detail how to evaluate the capacitance, the resistance

and the inductance of a wire. After this discussion, different models suited to catch the contribution to the
delay of a wire will be presented.

CAPACITANCE
Let us consider a rectangular wire placed above the substrate.

If the width W of the wire is substantially larger than its thickness H, it may be assumed that the electricalfield lines are orthogonal to the capacitor plates, and that its capacitance can be modeled by the parallelplate capacitance, also called area capacitance. The capacitance is
WL
,
C pp = di
tdi
where di stands for the dielectric permittivity given by the product of r0. di is the relative permittivity,
while 0 is the permittivity of the vacuum equal to 8.854 x 10-12 F/m. The typical dielectric material is the
SiO2 having a relative permittivity of 3.9, 1/3 of the silicon permittivity (11.7). Silicon Nitride is not used as
insulating material due to a larger relative permittivity (7.5). Its only used as sacrificial layer in the CMOS
process steps. In the future, to reduce the capacitance of the wires, aerogel can be adopted since it
features a lower permittivity (see the next table).

The important message from the previous equation is that the capacitance is proportional to the
overlapping area.
Unfortunately, a wire rarely presents a width much larger than its thickness. A small width is desirable to
shrink the layout and to lessen the overhead, thus to keep the resistance low the height cannot be too
much low. In our reference technology, a metal 2 for example has a minimum width of 0.4m and a height
of 1m. Thus, the aspect ratio, i.e. the ratio between the width and the thickness of the wire, can be lower
than 1. Under these circumstances, the parallel plate approximation is no longer valid. In fact, the
contribution of the side-walls to the substrate cannot be longer ignored. The contribution due to the
sidewall is also called fringing capacitance. In fact, fringe means edge.
The problem can be simplify considering that a wire with a height H and a width W can be decomposed as
the sum of a cylinder having a diameter of H and a rectangular wire with a width equal to w=W-H/2.

Thus, considering a wire of length L, the overall capacitance results

Ctot
w
2
.
di + di
L
tdi
2tdi
ln 1 +
H

The point is that the fringing capacitance is a mild function, being the logarithm a mild function of its
argument, of the ratio between the dielectric thickness and the height of the wire. The fringing capacitance
is usually the most dominant contribution, also by a factor of 5-10, for W/tdi ratio lower than 1,
approximately.
Lets try to plot the two contributions, the parallel-plate and the fringing capacitance, as function of the
W/tdi ratio, normalized to the wire length L and considering the silicon dioxide as dielectric. The former
contribution increases linearly with the aforementioned ratio, the latter instead is almost independent. The
following graph reports the area capacitance and the overall capacitance for two values of the H/ tdi ratio,
0.5 and 1. The difference is light. Its worth pointing out that the overall capacitance is approximately
constant for W/tdi ratio lower than 1. Observe that your reference book is just a bit messy since it indicates
the dielectric thickness first with tdi and then with H.

H/tdi=1
H/tdi=0.5
Cpar-plate

W
H
tdi

W/tdi
The previous graph refers to the so called microstripline, which is a wire surrounded by dielectric above a
ground plane. The situation is more complicated if you consider that todays processes offer many layers of
interconnect. In this scenario, the assumption that a wire is completely isolated from its surrounding
structures and is only coupled to ground becomes unrealistic.
The situation can be like the one depicted in the following figure.

fringing

parallel

Considering the top-left wire, its capacitive components are not towards the grounded substrate, rather
than to the nearby wires. Both parallel-plate and fringing contributions are present. Clearly, this situation is
very tangled and difficult to analyze. The overall parasitic capacitance affecting the considered wire can be
evaluated by means of a parasitic extractor in the layout environment. However, its clear that this situation
is not the best in term of capacitance. The best scenario is when the wire is not close to other wires and
well distant from the substrate, i.e., with a small W/tdi ratio.
Now, if I want to estimate by hand the parasitic capacitance of a wire, like the one just considered, what
can I do? Typically, for a given technology process, a table is given reporting the parallel-plate and the
fringing capacitance contributions for a wire in a certain layer with respect to another wire in another layer.
This table reports the contributions for the 0.25m process technology. The parallel-plate capacitance is
reported in the white lines expressed in aF/m2 of overlapping area, while the shaded lines report the
fringing capacitance contribution in aF/m of perimeter.
The rows represent the considered wire (poly, met1, etc), while the column represents the underlying
layer. The term field refers to the oxide that covers the substrate, while active refers to a n+/p+ region.

Clearly, the contributions increase moving rightwards in a row since the dielectrics thickness becomes
thinner.
A similar table is given for evaluating the capacitance towards a nearby wire implemented with the same
layer, supposed that the two wires are at the minimum distance allowed by the technology process. In this
case the capacitance is per unit length of lateral overlapping in aF/m.

The inter-wire capacitance increases moving from pol to metal5, even if the minimum distance between
adjacent wires increases due to a larger height of the wires implemented in the upper levels.

The metal5 wires display the highest inter-wire capacitance due to the largest height. Its clear that this
metal has to be used to distribute around the chip the global signals, like the clock and the power supplies.
Lets make an example to show how to compute the capacitance of a wire. Consider a wire in aluminum of
10cm length and 1m width routed in the metal1 layer of our 0.25-m CMOS process. This wire is no
surrounded by other wires. The capacitance to ground can be computed considering the first table as

aF 5
aF 5
Ctot 30
m
m
m

10

+
40

2
10

= 3pF + 8 pF = 11pF .

m2 L
m L
W
The factor of 2 in the above expression takes into consideration the two sides of the wire in order to
correctly evaluate the perimeter of the wire.
Now, let us suppose that a second wire in metal1 is built alongside the first one, at the minimum distance.
We can estimate the inter-wire capacitance from the second table as

aF 5
Cint 95
10 m = 9.5pF .
m L
Clearly, adding this wire alongside the first one reduces the contribution due to the fringing capacitance,
since some of the field lines do not close to ground but to the adjacent wire. This example shows how much
the evaluation of the wire capacitance can be troublesome.

RESISTANCE
The resistance of a wire can be calculated by means of the well-known expression:
L
R=
WH
where is the resistivity of the material in m.
The most commonly-used material is the aluminum which a resistivity of 2.7x10-8m. We know that its
commonly-used due to its low cost and for its compatibility with the CMOS process.
The tungsten, which is sometimes adopted for the first level of metalization layer since it does not feature
problems of electro-migration, has a larger resistivity. Its a factor of 2 larger than the aluminum resistivity.
The copper, which is material adopted for the upper level metals in advanced technologies, is less resistive,
but it is not commonly implemented since the copper deposition is not trivial.

Looking to the expression of the resistance, since H is a constant for a given technology, the resistance can
be expressed as
L
L
R = = R .
W
H W
The ratio H is known as sheet resistance and its expressed in per square. In fact, considering a wire
with W=L, i.e., a square, the resistance of the wire is R . To assess the resistance of a certain wire, its
sufficient to multiply the sheet resistance by the ratio L/W, which represents the number of squares.
In the following table, you can observe the sheet resistance of the various interconnect layers in a modern
ICs.

The n- or p-well has a sheet resistance of approximately 1k per square. The n+ or p+ diffusion has a sheet
resistance which is a factor 10 lower, approximately 100 per square. If we silicide the diffusion, i.e. a layer
of a compound material is added on the surface of the diffusion, the resistance per square is reduced by a
factor larger than 10. The silicide is a compound material formed by silicon and a conductive material, like
Tungsten Disilicide (WSi2) or Titanium Disilicide (TiSi2). For example, Tungsten Disilicide has a resistivity of
1.3x10-6cm, which is 8 times lower that the polysilicon resistivity. This material is often used to reduce
the resistance of the transistor gates. Clearly, the aluminum has the lower sheet resistance. Approximately
0.1 per square. The value depends on the height of the wire. Also the contacts and the vias show a
resistance which is in the order of 10 for the contacts and 1-5 for the vias. Note that all these values are
evaluated in DC. At very high frequency, the resistance tends to increase due to the skin effect. In practice,
the current tends to flow in the peripheral part of the wire. Considering a wire with a width W and a height
H, the current flows almost entirely in a peripheral section characterized by a depth:

=
f
This formula suggests that the skin-effect increases as the frequency increases. At 1GHz the skin-depth for
the aluminum is 2.6um. Obviously, if the conductor has width and height lower than the skin-depth, this
effect does not take part. Thus, this effect is a concern only for wide wires.

INDUCTANCE
In digital integrated circuits, the inductive effects play a role with the advent of low-resistivity materials and
for the cutting-edge technologies when the circuits are driven with very-high frequency clocks. In this case,
in fact, the rise/fall times are lower than the time-of-flight of the signal along the global interconnections
and the inductive effect is no longer ignorable. Actually, inductive effects are a concern when we have to
design printed circuit boards or also when you have to model the long bonding wires.
First of all, which are the effects that the inductance of a wire can lead?
1) ringing and overshooting;
2) switching noise due to the Ldi/dt voltage drop;
3) magnetic coupling among wires.
However, these effects can be ignored in an integrated circuit unless you deal with very high-frequency
signals with very sharp rising and falling edges.
Now the question is: how can we assess the inductance of a wire?
The inductance per unit length of a conductor having a width W placed over a ground plane at a distance tdi
can be estimated as:
8t
inductance
W
=l= 0 ln di +
,
L
2 W 4tdi
assuming W<tdi and a negligible thickness of the wire. 0 is the vacuum permeability equal to 4107H/m.
First, observe that the inductance of the wire is a mild function of the geometrical dimensions, being a
logarithm. For W=tdi, the formula yields an inductance of about 0.4pH/m. Second, this expression is too
cumbersome to be adopted.
Fortunately, the inductance can be evaluated in a simpler way considering that the capacitance per unit
width, c, and the inductance per unit length, l, are related to the speed of an electromagnetic wave, being

v=

1
lc

c0

r r

where c0 is the light speed in free air (3x108 m/s or equivalently 30cm/ns), while r and r are the relative
permittivity and permeability, respectively, of the surrounding dielectric. Thus, being r=3.9 and r=1 for
the silicon dioxide, the speed of an electromagnetic wave is about half the light speed.
Lets make an example considering a wire in the first layer of aluminum in our reference process
surrounded by the dielectric and above the substrate which acts as ground plane. The capacitance per unit
length can be estimated as
c = (W 30 + 2 40 ) aF m .
We can derive the inductance per unit lenght from the previous formula ( v = c0

l=

r r ) as

r r

.
c c02
Thus, for W=1m the capacitance per unit length is 110aF/m, while the inductance per unit length is
0.39pH/m, close to the value estimated before for by means of the inductance formula. Now, assuming a
resistance of 0.075/um, we can evaluate at which frequency the inductive impedance is equal to the
resistance of the wire. It comes out
r
2 fl = r f =
30GHz .
2 l
These numbers indicate that the inductance becomes an issue in integrated circuits for frequencies that are
well above 10 GHz.

ELECTRICAL MODELS
Until now, we have studied how to compute the capacitance, the resistance and the inductance of a wire.
Now, we are interested in evaluating the effect of this parasitics on the propagation delay.
First of all, we can distinguish between lumped and distributed models. Lets start with the lumped models.

LUMPED C MODEL
As long as the resistance of the wire is low, much lower than the driving resistance, the wire can be
modeled as a lumped capacitance.

WIRE
OUT

IN
Cw

IN

Req
Cint

OUT
Cw

In this case, the wire introduces a capacitance in parallel to the output capacitance of the driving inverter,
which eventually adds to the input capacitance of the load.
For the considered case, the propagation delay can be estimated as
= ln ( 2 ) Re q ( C int + C w ) .
Note that if the wire ends with a capacitive load we have to add the load to the overall capacitance.
This is the simplest model. Note that in this case the wire is considered equipotential: each point along the
line has the same voltage at a given instant.

LUMPED RC MODEL
If the resistance of the wire is no longer negligible, the first approach is to lump the resistance of the line
into a single resistance and the same for the capacitance. This model is known as lumped RC model. We will
find that this model is pessimistic and overestimates the propagation delay. The distributed model is more
accurate. The question is: while we need to study the lumped RC model?

1) the distributed RC model is complicated and there is no closed form solution;

2) we want to obtain a first estimate in a short time, rather than a more correct solution, which can be
easily obtained by means of a simulator;
3) finally, as we will see in the following, adopting the lumped RC model, we are able to approximate
the distributed model of the wire.
Lets come back to the previous problem with an inverter driving a wire and a capacitive load. In order to
assess the propagation delay we can model our inverter as a voltage generator (turned on at the time t=0)
in series to the equivalent resistance, the lumped RC model of the wire and the load. It result in a 2-pole
network, as depicted on the right.

Req

Req
IN

OUT

VDD

Rw
OUT

Cint

Rw

Cw

Cint

Cw

CL

CL

How can we assess the propagation delay? To this aim, a famous theorem may come in handy: the so called
Elmore theorem.

ELMORE THEOREM
This theorem allows to assess the delay of a network by evaluating the first-order time constant of the
network (which is equivalent to the first moment of the impulse response). The theorem can be applied if
three conditions are verified:
1. the network has a single input node;
2. all the capacitors are between a node and ground;
3. the network does not contain any resistive loops (which makes it a tree).
These conditions are verified in our previous example.
Now, let us consider a node i where we want to evaluate the delay of the input signal. The time constant
associated to this node can be assessed as
N

Di = Ck Rik .
k =1

For every capacitance Ck of the network, we have to evaluate the so called shared-path resistance, Rik. This
resistance represents the resistance shared between the path from the source s to the node i and the
path from the source to the capacitance Ck. This approximation has proven to be quite reasonable and
acceptable.
Lets make an example. Consider the following network which is compliant to the aforementioned
requirements (only one source, all capacitors to ground, and no loops) and lets try to assess the delay from
the source s to the output node i.

In this case, it is:

Di = C1 (R1 ) + C2 (R1 ) + C 3 ( R1 + R3 ) + C 4 (R1 + R3 ) + C i (R1 + R3 + Ri )

Obviously, the propagation delay can be evaluated as ln ( 2 ) Di .

Note that applying the Elmore theorem to this network having different branches its equivalent to shift the
capacitors C2 and C4 onto the path from the source to the output node, neglecting the resistances R2 and R4.
Then, the dominant time constant of the new network has to be evaluated.
For the same network, we can evaluate the time constant related to the node 2, which results:
D2 = ( C1 + C 3 + C 4 + C i )(R1 ) + C2 ( R1 + R2 )
For the abovementioned problem of an inverter that drives a wire (having a resistance RW and a
capacitance CW) and a load CL, the time constant is
Dout = C int (Re q ) + ( Cw + C L ) (Re q + Rw ) .
Another example where the Elmore theorem finds application is the non-branched RC chain, also known as
ladder network.

Let us suppose that all the resistances have the same value R as well as the capacitances whose value is C.
Thus, we have N identical RC cells in cascade.
The time constant referred to the output node is:
N ( N + 1)
Dout = CR + 2CR + 3CR + ...... + NCR =
CR
2
This model can be used as a good approximation of a resistive-capacitive wire, without adopting a
distributed RC model. The wire with a total length of L is partitioned into N identical segments, each with a
length of L/N. The resistance and capacitance of each segment are hence equal to R/N and C/N,
respectively. Introducing the specific resistance r and the specific capacitance c we have rL/N and cL/N.
Rearranging the previous expression we get:
N ( N + 1) cL rL
Dout =
2
NN
For very large values of N, this model asymptotically approaches the distributed RC line yielding:
rcL2 RC
Dout
=
2
2
Two important conclusions can be drawn:
1) the delay of a line increases with the square of the length, because both R and C are proportional
to the length L;
2) the lumped RC model overestimates the delay since we get a time constant RC, while with this
more accurate model that resembles a distributed line we get RC/2.
Finally, note that this theorem will be very helpful when we analyze the delay of complex gate having
transistors in series. Since a transistor can be thought as a combination of a resistance and a capacitance to
ground, we can model a complex gate as cascaded RC cells and apply the Elmore delay formula.

DISTRIBUTED RC MODEL
So far, we have learned that the lumped RC model leads to a wrong estimation of the delay thorough a
wire. More precisely, it leads to an overestimation. By using a distributed-like model we get a more correct
result. The real distributed model considers the line as infinite RC cells each having an infinitesimal length
L, with L that tends to 0. This is the schematic representation of the distributed rc line and its
equivalent symbol:

The voltage at the node i of this network can be determined by solving the following differential equation
V (V V ) (Vi Vi 1 )
cL i = i +1 i
,
t
r L
with L that tends to 0.
It yields the famous diffusion equation:
V 2V
rc
=
t x2
where V is the voltage at a particular point of the line and x is the distance between that point and the
source.
This equation is difficult to be solved and no closed form solution exists for this problem. The voltage at the
end of the line can be approximated as:

RC
2 x t2
erf(
x
):
e dt
t<<RC
=
Vout ( t ) = 2erf

0
4t

t
t

2.5359
9.4641
RC
RC
t>>RC
+ 0.366e
Vout ( t ) = 1 1.366e
where R and C are the overall resistance and capacitance of the line, respectively.
Now, if we plot the solution of this differential equation for different point of the line we get the following
graph. Note how the voltage diffuses from the onset to the end of the line and note how the delay
increases moving rightwards.

Moreover, we can compare the results obtained by solving the diffusion equation with the results of the
lumped RC model:

Now, look at the propagation delay evaluated with the distributed model. This delay is 0.38RC, which is
roughly half the delay estimated by the lumped model.

And what did we get when we considered the wire as formed by N cells having the same resistance and the
same capacitance and applying the Elmore delay formula? Approximately the same result, that is,
ln(2)RC/2=0.345RC. Thus, from now on, we can consider that a line with a resistance R and a capacitance C
gives a delay equal to ln(2)RC/2, instead of ln(2)RC, in order to take into consideration the distributed effect
of capacitance and resistance.
Now, lets consider again the wire with a length L, specific capacitance c and specific resistance r, so that
Rw=rL and Cw=cL.

IN

(r,c,L)
OUT

(r,c,L)

Req

IN

OUT
Cint

In order to take into the right consideration the effect of the distributed line, we can adopt for the line the
so called model or the T model, which both give the same result, and then apply the Elmore formula.

Rw
2

Rw

Rw
2

Cw
2

Cw
2

Cw

Applying the model, we get

Cw
C R

C
Re q ) + w (Re q + Rw ) = ( Cint + Cw ) R eq + w w .
(

2
2

2
If we apply the T-model we get the same result, being
R
C R

D = Cint (Re q ) + C Re q + w = ( Cint + Cw ) R eq + w w .

2
2

Note that the last contribution is the time constant of the line (thus its delay) evaluated with the
distributed model.
Now, a designer may ask whether breaking a long wire in small pieces and inserting an inverter between
two adjacent segments of the line can lead to an improvement in terms of overall propagation delay. This
expedient comes from the fact that the propagation delay of a wire is a quadratic function of its length.
Hence, breaking the line in small segments helps to reduce this quadratic dependence. Clearly, the prize of
this technique is that we have to insert buffers that add their delay while dissipating power consumption.
Let us consider a wire of length L featuring a specific resistance r and a specific capacitance c (Rw=rL and
Cw=cL). This wire is driven by a minimum-size inverter and terminated by a similar inverter.
LINE MODEL

D = Cint +

OUT
IN

(r,c,L)

Req
IN
Cint

Rw
2

Rw
2
Cw

For convenience, we have considered for the line the T model. The propagation delay results
rL

D = Cint (Re q ) + cL Re q + + Cint ( Re q + rL ) .

2

Now, lets break the wire in N pieces inserting a minimum size inverter among adjacent pieces.

OUT
Cg=Cint

N-1

2
(r,c,L/N)

(r,c,L/N)

N
(r,c,L/N)

The delay time is now

cL
rL
rL

D(N ) = N Cint ( Re q ) + Re q + + Cint Re q + .

N
N
2N

By differentiating this equation with respect to the variable N (the number of digital buffer, also known in
this case as repeaters) and equating this derivative to zero, we can obtain the optimum number of
segments for the considered wire.
It results
N
d D( )
crL2
cr
= 2Cint Re q 2 = 0 N = L
.
dN
2N
4Cint Re q
When the following condition is verified (just substituting N with 2 in the previous equation),
L

16Cint Re q

,
cr
its convenient to break the line and insert buffers.
For example, considering Cint=2fF, Req=11k and a wire in metal 1 having c=110aF/m and r=0.075/m,
we get
L>6500m=6.5mm. For a length larger than 6.5mm, its convenient to insert a buffer to reduce the
propagation delay.

TRANSMISSION LINE MODEL

This model predicts that the signal travels along the line at the speed of the light (or a fraction of the speed
light) as an electromagnetic wave. In practice, you have to think at the rising edge of the signal that travels
without changing its shape along the line. In this case, the line can be seen as a cascade of LC cells. This
model is accurate when the inductive effect is dominant and cannot be neglected. Since this does not
happen inside an integrated circuit, unless in rare cases, we will not enter the model in detail.
Why this well-known model is not suited for a wire inside an integrated circuit?
The model is appropriate if:
1) the rise/fall time of the signal is much lower than the time-of-flight along the wire;
2) the RC delay is much lower than the time-of-flight (i.e. the signal propagates as an electromagnetic
wave).
For what concerns the first condition, we can write:
t
tr t flight L r .
lc
L lc

The second condition leads to the following requirement for the length of the wire:
1 l
RC t flight L
,
r c
rcL2
L lc

Z0

l
is the so called characteristic impedance of the wire and areexpressed in . It typically
c
ranges from 50 to 200,
Thus, the two conditions give the following inequality:
tr
1 l
L
.
r c
lc

where Z 0 =

Z0

Let us consider our first level of aluminum metal in the 0.25m CMOS process that we use as reference
technology. In this case, r=0.075/um, c=110aF/m, l=0.39pH/m, Z0=60 and v=c/2=15ns/cm.
The previous inequality results
tr
L 800 m .
lc
We can plot the two inequalities in a graph having as horizontal axis the rise time and as vertical axis the
length of the wire.

L
10mm

1mm

RC delay dominates

inductance matters

rise time dominates

100um

10um
1ps

10ps

100ps

1ns

tr

Note that, since in our reference technology there can no exist a rise time lower than 10ps, the inductance
never matters. If we consider a metal5, which has a larger height and thus a lower specific resistance, the
horizontal line translates upwards and the region where inductance matters becomes larger. At a board
level, i.e., on a printed circuit board, where the wires are thicker and so the specific resistance is much
smaller, the transmission line model can be the most appropriate one in certain cases.
Also in the advanced integrated technologies, where copper is adopted for the upper level
interconnections, this model can come in handy.
In fact, lets assume a copper wire with a characteristic impedance of 200 and a resistance of 0.025/m.
The resulting maximum wire length equals 8mm. This length corresponds to a critical rise time of 53psec,
which is feasible in advanced technologies.

IMPACT OF TECHNOLOGY SCALING ON WIRE PERFORMANCE

Similar to what we have done for the MOS transistor, it is worthwhile to explore how the wire parameters
are affected by the technology scaling.
As transistor dimensions are reduced, also the interconnect dimensions have to be reduced to take full
advantage of the scaling process.
The simple approach consists in scaling down all the physical dimensions of the wires by the same factor S,
except for the length. Thus, the minimum width W, the height H and the dielectric thickness tdi are scaled
down by S. As far as the length of the wire is concerned, we need to distinguish between local and global
interconnections. Concerning the local interconnections, it can be inferred that their length decreases since
transistors are closer by the same factor S. Instead, concerning the global interconnections, we know that,
while transistor dimensions have continued to shrink over the last decades, the chip sizes have gradually
increased. In fact, the chip size increases by about 6% per year. Thus, we can assume that the global
interconnections are scaled by a factor of SC, being SC less than 1.
Under these conditions, the wire performance show the trend depicted in the following table. Be aware
that this is only a first-order analysis. It does not take into account such aspects like fringing capacitance
and advanced features, like low-k dielectrics and low-resistance interconnect materials.

Note that in local interconnections the resistance increases while the capacitance decreases, so that the
delay does not scale down and remains constant. The problem is exacerbated in global interconnections
where the delay even increases! This is the reason why with the technology scaling the wire acquires more
and more importance and need to be treated and modeled at the manner of the transistors.
Its evident that the ideal scaling approach clearly has problems, as it causes a rapid increase in wire
resistance. This has suggested a new way of scaling the wires, which can be identified as constant
resistance where the thickness of the wire is not scaled but left unchanged. This approach seems
advantageous but it brings to foreground the effects of fringing capacitance and inter-wire capacitance.
We can introduce the factor c (c>1) that takes into account the increases of the lateral capacitance of
the wire, always considering that the parallel-plate capacitance contribution is decreased by the reduced
dimensions of the wire. We get the following table.

Considering c<S we have a small advantage concerning the local interconnections while the problem of an
increased delay in the global wires is still present.
This consideration explains why the technologists are trying to improve the wire material (copper instead of
aluminum) and the insulation material (low-k dielectrics).