You are on page 1of 11

IRF640N/IRF640NS/IRF640NL

N-Channel Power MOSFETs


200V, 18A, 0.15
Features

Peak Current vs Pulse Width Curve

Ultra Low On-Resistance


- rDS(ON) = 0.102 (Typ), VGS = 10V

UIS Rateing Curve

Simulation Models
- Temperature Compensated PSPICE and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models

DRAIN
(FLANGE)

SOURCE
DRAIN
GATE

SOURCE
DRAIN
GATE

DRAIN
(FLANGE)

GATE
SOURCE
G

DRAIN
(FLANGE)

TO-263

TO-220

TO-262

MOSFET Maximum Ratings TA = 25C unless otherwise noted


Symbol
VDSS
VGS

ID

EAS
PD
TJ, TSTG

Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
Continuous (TC = 25oC, VGS = 10V)
Continuous (TC = 100oC, VGS = 10V)
Pulsed
Single Pulse Avalanche Energy (Note 1)
Power dissipation
Derate above 25oC
Operating and Storage Temperature

Ratings
200
20

Units
V
V

18

13
Figure 4
247
150
1.0
-55 to 175

A
A
mJ
W
W/oC
oC

Thermal Characteristics
RJC

Thermal Resistance Junction to Case TO-220, TO-262, TO-263

1.0

oC/W

RJA

Thermal Resistance Junction to Ambient TO-220, TO-262, TO-263

62

oC/W

40

oC/W

RJA

Thermal Resistance Junction to Ambient TO-263,

1in2

copper pad area

Package Marking and Ordering Information


Device Marking
640N
640N
640N

2002 Fairchild Semiconductor Corporation

Device
IRF640NS
IRF640NL
IRF640N

Package
TO-263AB
TO-262AA
TO-220AB

Reel Size
330mm
Tube
Tube

Tape Width
24mm
N/A
N/A

Quantity
800 units
50
50

Rev. B

IRF640N/IRF640NS/IRF640NL

January 2002

IRF640N/IRF640NS/IRF640NL

Electrical Characteristics TA = 25C unless otherwise noted


Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

ID = 250A, VGS = 0V

200

VDS = 200V, VGS = 0V

25

250

VGS = 20V

100

nA

Off Characteristics
BVDSS

Drain to Source Breakdown Voltage

IDSS

Zero Gate Voltage Drain Current

IGSS

Gate to Source Leakage Current

VDS = 160V

TC = 150o

On Characteristics
VGS(TH)

Gate to Source Threshold Voltage

VGS = VDS, ID = 250A

rDS(ON)

Drain to Source On Resistance

ID = 11A, VGS = 10V

gfs

Forward Transconductance

VDS = 50V, ID = 11A (Note 2)

0.102

0.15

6.8

2200

pF

Dynamic Characteristics
CISS

Input Capacitance
VDS = 25V, VGS = 0V,
f = 1MHz

COSS

Output Capacitance

CRSS

Reverse Transfer Capacitance

Qg(TOT)

Total Gate Charge at 20V

VGS = 0V to 20V

Qg(10)

Total Gate Charge at 10V

VGS = 0V to 10V V =100V


DD
VGS = 0V to 2V ID = 22A
Ig = 1.0mA

Qg(TH)

Threshold Gate Charge

Qgs

Gate to Source Gate Charge

Qgd

Gate to Drain Miller Charge

Switching Characteristics

400

pF

120

pF

117

152

nC

64

83

nC

nC

nC

24

nC

(VGS = 10V)

tON

Turn-On Time

44

ns

td(ON)

Turn-On Delay Time

10

ns

tr

Rise Time

19

ns

td(OFF)

Turn-Off Delay Time

23

ns

tf

Fall Time

5.5

ns

tOFF

Turn-Off Time

46

ns

VDD = 100V, ID = 11A


VGS = 10V, RGS = 2.5

Drain-Source Diode Characteristics


VSD

Source to Drain Diode Voltage

ISD = 11A

1.3

trr

Reverse Recovery Time

ISD = 11A, dISD/dt = 100A/s

251

ns

QRR

Reverse Recovered Charge

ISD = 11A, dISD/dt = 100A/s

1394

nC

Notes:
1: Starting TJ = 25C, L = 4.2mH, IAS = 11A.
2: Pulse width 400s; duty cycle 2%.

2002 Fairchild Semiconductor Corporation

Rev. B

1.2

20

POWER DISSIPATION MULTIPLIER

1.0
ID, DRAIN CURRENT (A)

15
0.8

0.6

0.4

0.2

10

0
0

25

50

75

100

150

125

175

25

50

75

TC , CASE TEMPERATURE (oC)

100

125

150

175

TC, CASE TEMPERATURE ( C)

Figure 1. Normalized Power Dissipation vs


Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs


Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01

THERMAL IMPEDANCE

ZJC, NORMALIZED

PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZJC x RJC + TC

SINGLE PULSE
0.01
10-5

10-4

10-3

10-2

10-1

100

101

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance


300

TC = 25oC

IDM, PEAK CURRENT (A)

FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
175 - TC

I = I25

150
VGS = 10V

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5

10-4

10-3

10-2

10-1

100

101

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

2002 Fairchild Semiconductor Corporation

Rev. B

IRF640N/IRF640NS/IRF640NL

Typical Characteristic

200

100

100
IAS, AVALANCHE CURRENT (A)

ID, DRAIN CURRENT (A)

100s

1ms
10
10ms

1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)

SINGLE PULSE
TJ = MAX RATED
TC = 25oC

10

If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]

0.1

1
1

10

100

300

0.001

0.01

0.1

Figure 5. Forward Bias Safe Operating Area

Figure 6. Unclamped Inductive Switching


Capability
40

40
PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX
VDD = 15V

VGS = 10V
VGS = 5V
30
ID, DRAIN CURRENT (A)

30

20
TJ = -55oC

TJ = 175oC
10

VGS =4.5V
20

10
PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX
TC = 25oC

TJ = 25oC
0

0
3

4
5
VGS, GATE TO SOURCE VOLTAGE (V)

Figure 8. Saturation Charactoristics

3.5
3.0

VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Charicteristics

1.2
VGS = VDS, ID = 250A

PULSE DURATION = 80s


DUTY CYCLE = 0.5% MAX

2.5

NORMALIZED GATE
THRESHOLD VOLTAGE

NORMALIZED DRAIN TO SOURCE


ON RESISTANCE

10

tAV, TIME IN AVALANCHE (ms)

VDS, DRAIN TO SOURCE VOLTAGE (V)

ID, DRAIN CURRENT (A)

STARTING TJ = 25oC

STARTING TJ = 150oC

2.0
1.5
1.0

1.0

0.8

0.5
VGS = 10V, ID = 22A
0.6

0
-80

-40

40

80

120

160

TJ, JUNCTION TEMPERATURE (oC)

Figure 9. Normalized Drain To Source On


Resistance vs Junction Temperature

2002 Fairchild Semiconductor Corporation

200

-80

-40

40

80

120

160

200

TJ, JUNCTION TEMPERATURE (oC)

Figure 10. Normalized Gate Threshold Voltage vs


Junction Temperature

Rev. B

IRF640N/IRF640NS/IRF640NL

Typical Characteristic (Continued)

10000

1.3

VGS = 0V, f = 1MHz


CISS = CGS + CGD

1.2

C, CAPACITANCE (pF)

NORMALIZED DRAIN TO SOURCE


BREAKDOWN VOLTAGE

ID = 250A

1.1

1.0

0.9

1000

COSS CDS + CGD


100

CRSS = CGD

0.8
-80

-40

40

80

160

120

10

200

0.1

1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)

TJ , JUNCTION TEMPERATURE (oC)

Figure 11. Normalized Drain To Source


Breakdown Voltage vs Junction Temperature

100 200

Figure 12. Capacitance vs Drain to Source


Voltage

10
VGS , GATE TO SOURCE VOLTAGE (V)

VDD = 100V
8

4
WAVEFORMS IN
DESCENDING ORDER:
2

ID = 22A
ID = 5A

0
0

10

20

30

40

50

60

70

Qg, GATE CHARGE (nC)

Figure 13. Gate Charge Waveforms for Constant Gate Currents

Test Circuits and Waveforms

BVDSS

VDS
tP

VDS

L
IAS

VDD

VARY tP TO OBTAIN
REQUIRED PEAK IAS

RG

VDD
-

VGS
DUT
tP
0V

IAS

0
0.01
tAV

Figure 14. Unclamped Energy Test Circuit

2002 Fairchild Semiconductor Corporation

Figure 15. Unclamped Energy Waveforms

Rev. B

IRF640N/IRF640NS/IRF640NL

Typical Characteristic (Continued)

IRF640N/IRF640NS/IRF640NL

Test Circuits and Waveforms (Continued)

VDS

VDD

Qg(TOT)

RL

VDS
VGS = 20V

VGS

Qg(10)

VDD

VGS = 10V

VGS

VGS = 2V

DUT
0

Ig(REF)

Qg(TH)
Qgs

Qgd

Ig(REF)
0

Figure 16. Gate Charge Test Circuit

Figure 17. Gate Charge Waveforms

VDS

tON

tOFF

td(ON)

td(OFF)
tr

RL
VDS

tf

90%

90%

VGS

VDD
-

10%

10%

DUT

90%

RGS
VGS

50%

50%
PULSE WIDTH

VGS

Figure 18. Switching Time Test Circuit

2002 Fairchild Semiconductor Corporation

10%

Figure 19. Switching Time Waveforms

Rev. B

( T JM T A )
P DM = ------------------------------Z JA

(EQ. 1)

In using surface mount devices such as the TO-263


package, the environment in which it is applied will have a
significant influence on the parts current and maximum
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.

80
RJA = 26.51+ 19.84/(0.262+Area)

60
RJA (oC/W)

The maximum rated junction temperature, TJM, and the


thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in
an application.
Therefore the applications ambient
temperature, TA (oC), and thermal resistance RJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.

40

20
0.1

10

AREA, TOP COPPER AREA (in2)

Figure 20. Thermal Resistance vs Mounting


Pad Area

2. The number of copper layers and the thickness of the


board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designers preliminary application evaluation. Figure 20
defines the RJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 20 or by calculation using
Equation 2. RJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.

19.84
( 0.262 + Area )

R JA = 26.51 + -------------------------------------

2002 Fairchild Semiconductor Corporation

(EQ. 2)

Rev. B

IRF640N/IRF640NS/IRF640NL

Thermal Resistance vs. Mounting Pad Area

IRF640N/IRF640NS/IRF640NL

PSPICE Electrical Model


.SUBCKT IRF640N 2 1 3 ;

rev 10 October 2000

CA 12 8 3.6e-9
CB 15 14 3.5e-9
CIN 6 8 2e-9
LDRAIN

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

DPLCAP
10

5
51
EVTHRES
+ 19 8

+
LGATE
GATE
1

EVTEMP
RGATE +
18 22
9
20

11
+

21

17
EBREAK 18
-

16

DBODY

MWEAK

MMED
MSTRO

RLGATE

LSOURCE

CIN

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 83.5e-3
RGATE 9 20 7.6e-1
RLDRAIN 2 5 10
RLGATE 1 9 57.8
RLSOURCE 3 7 39.2
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

ESLC
50

RDRAIN

6
8

ESG

DBREAK

RSLC2

IT 8 17 1

S1A
S1B
S2A
S2B

RLDRAIN

RSLC1
51

EBREAK 11 7 17 18 225
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

LDRAIN 2 5 1e-9
LGATE 1 9 5.78e-9
LSOURCE 3 7 3.92e-9

DRAIN
2

SOURCE
3

7
RSOURCE
RLSOURCE

S1A
12

S2A

13
8

S1B
CA

RBREAK

15

14
13

17

18
RVTEMP

S2B
13

CB
6
8

EGS

19
VBAT

5
8

EDS

IT

14

+
8
22
RVTHRES

6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*38),2.5))}
.MODEL DBODYMOD D (IS = 1.2e-12 RS = 5.5e-3
XTI = 5.5 TRS1 = 1e-5 TRS2 = 8e-6 + CJO = 12.5e-10 TT = 1e-7 M = 0.42)
.MODEL DBREAKMOD D (RS = 2.5 TRS1 = 1e-3 TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 2.5e-9 IS = 1e-30 N = 10 M = 0.9)
.MODEL MMEDMOD NMOS (VTO = 3.14 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.6e-1)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 100 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.76 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.6 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 =1.52e-3 TC2 = -2e-7)
.MODEL RDRAINMOD RES (TC1 = 9.8e-3 TC2 = 2.6e-5)
.MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.3e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.8e-3 TC2 = 1.7e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5

ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1

VON = -8.5 VOFF= -1)


VON = -1 VOFF= -8.5)
VON = -0.1 VOFF= 0.2)
VON = 0.2 VOFF= -0.1)

.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

2002 Fairchild Semiconductor Corporation

Rev. B

IRF640N/IRF640NS/IRF640NL

SABER Electrical Model


REV 10 October 2000
template IRF640N n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1.2e-12, rs=5.5e-3, trs1=1e-5, trs2=8e-6, cjo = 12.5e-10, m=0.42, tt = 1e-7, xti = 5.5)
dp..model dbreakmod = (rs=2.5, trs1=1e-3, trs2=-8.9e-6)
dp..model dplcapmod = (cjo = 2.5e-9, isl =10e-30, nl=10, m = 0.9)
m..model mmedmod = (type=_n, vto = 3.14, kp = 5, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.68, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.76, kp = 0.05, is = 1e-30, tox = 1, rs = 0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -8.5, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -8.5)
LDRAIN
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2)
DPLCAP 5
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1)
10

c.ca n12 n8 = 3.6e-9


c.cb n15 n14 = 3.5e-9
c.cin n6 n8 = 2e-9

DRAIN
2

RLDRAIN

RSLC1
51
RSLC2
ISCL

dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod

l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.78e-9
l.lsource n3 n7 = 3.92e-9

RDRAIN

6
8

ESG

i.it n8 n17 = 1

EVTHRES
+ 19 8

+
LGATE
GATE
1

EVTEMP
RGATE + 18 22
9
20

21

11

16
MWEAK

6
MSTRO
CIN

S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 1.52e-3, tc2 = -2e-7
12
15
14
13
res.rdrain n50 n16 = 83.5e-3, tc1 = 9.8e-3, tc2 = 2.6e-5
13
8
res.rgate n9 n20 = 7.6e-1
S1B
S2B
res.rldrain n2 n5 = 10
13
res.rlgate n1 n9 = 57.8
CB
CA
res.rlsource n3 n7 = 39.2
+ 14
+
res.rslc1 n5 n51 = 1e-6, tc1 = 3e-3, tc2 = 1e-6
6
5
EGS
EDS
8
8
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.7e-6
res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.3e-5

DBODY

EBREAK
+
17
18

MMED

RLGATE

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u


m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

DBREAK

50

LSOURCE
7

SOURCE
3

RSOURCE
RLSOURCE
RBREAK
17

18
RVTEMP
19

IT

VBAT
+
8

22
RVTHRES

spe.ebreak n11 n7 n17 n18 = 225


spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/38))** 2.5))
}
}

2002 Fairchild Semiconductor Corporation

Rev. B

th

IRF640N/IRF640NS/IRF640NL

SPICE Thermal Model

JUNCTION

REV 10 October 2000


IRF640N

CTHERM1 th 6 2.8e-3
CTHERM2 6 5 4.6e-3
CTHERM3 5 4 5.5e-3
CTHERM4 4 3 9.2e-3
CTHERM5 3 2 1.7e-2
CTHERM6 2 tl 4.3e-2
RTHERM1 th 6 5e-4
RTHERM2 6 5 1.5e-3
RTHERM3 5 4 2e-2
RTHERM4 4 3 9e-2
RTHERM5 3 2 1.9e-1
RTHERM6 2 tl 2.9e-1

SABER Thermal Model

RTHERM1

CTHERM1

CTHERM2

RTHERM2

CTHERM3

RTHERM3

IRF640N
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.8e-3
ctherm.ctherm2 6 5 = 4.6e-3
ctherm.ctherm3 5 4 = 5.5e-3
ctherm.ctherm4 4 3 = 9.2e-3
ctherm.ctherm5 3 2 = 1.7e-2
ctherm.ctherm6 2 tl = 4.3e-2
rtherm.rtherm1 th 6 = 5e-4
rtherm.rtherm2 6 5 = 1.5e-3
rtherm.rtherm3 5 4 = 2e-2
rtherm.rtherm4 4 3 = 9e-2
rtherm.rtherm5 3 2 = 1.9e-1
rtherm.rtherm6 2 tl = 2.9e-1
}

RTHERM4

CTHERM4

RTHERM5

CTHERM5

RTHERM6

CTHERM6

tl

2002 Fairchild Semiconductor Corporation

CASE

Rev. B

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx
Bottomless
CoolFET
CROSSVOLT
DenseTrench
DOME
EcoSPARK
E2CMOSTM
EnSignaTM
FACT
FACT Quiet Series

FAST
FASTr
FRFET
GlobalOptoisolator
GTO
HiSeC
ISOPLANAR
LittleFET
MicroFET
MicroPak
MICROWIRE

OPTOLOGIC
OPTOPLANAR
PACMAN
POP
Power247
PowerTrench
QFET
QS
QT Optoelectronics
Quiet Series
SILENT SWITCHER

SMART START
STAR*POWER
Stealth
SuperSOT-3
SuperSOT-6
SuperSOT-8
SyncFET
TinyLogic
TruTranslation
UHC
UltraFET

VCX

STAR*POWER is used under license

DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification

Product Status

Definition

Advance Information

Formative or
In Design

This datasheet contains the design specifications for


product development. Specifications may change in
any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and


supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed

Full Production

This datasheet contains final specifications. Fairchild


Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete

Not In Production

This datasheet contains specifications on a product


that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4