List of papers

1. 250V thin layer SOI Technology with Field pLDMOS for High-Voltage
Switching IC, Ming Qiao, IEEE TED, vol. 62, no. 6, June 2015.
2. A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS
Device, Ying Wang, IEEE TED, vol. 62, no. 1, Januray 2015.
3. An Improved Model of Self-Heating Effects for Ultrathin Body SOI nMOSFETs Based on Phonon Scattering Analysis, Guohe Zhang, IEEE EDL,
vol. 36, no. 6, June 2015.
4. An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors, Nitin Prasad, IEEE TED, vol. 62, no. 3, March 2015.
5. Analytical Model for the Inversion Gate Capacitance of DG and UTBB
MOSFETs at the Quantum Capacitance Limit, Gaspard Hiblot, IEEE
TED, vol. 62, no. 5, May 2015.
6. Atomic Level Modeling of Extremely Thin Silicon-on-Insulator MOSFETs
Including the Silicon Dioxide- Electronic Structure, IEEE TED, vol. 62,
no. 3, March 2015.
7. Back-Gate Effect on RON,sp and BV for Thin Layer SOI Field p-Channel
LDMOS, IEEE TED, vol. 62, no. 4, April 2015.
8. Comparison Between Bulk and FDSOI POM Flash Cell- A Multiscale
Simulation Study, Vihar P. Georgiev, IEEE TED, vol. 62, no. 2, February
2015.
9. Complementary SOI MESFETs at the 45nm CMOS node, William Lepkowski, IEEE EDL, vol. 36, no. 1, Januray 2015.
10. Drain-Current Flicker Noise Modeling in nMOSFETs from a 14-nm FDSOI Technology, Eleftherios G. Ioannidis, IEEE TED, vol. 62, no. 5, May
2015.
11. Enhanced Critical Electrical Characteristics in a Nanoscale Low-Voltage
SOI MOSFET With Dual Tunnel Diode, Mohammad Kazem Anvarifard,
IEEE TED, vol. 62, no. 5, May 2015.

12. Experimental and Theoretical Investigation of Magnetoresistance From

Linear Regime to Saturation in 14-nm FD-SOI MOS Devices, Minju Shin,
IEEE TED, vol. 62, no. 1, Januray 2015.
13. Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin
FD SOI MOSFETs, Fanyu Liu, IEEE EDL, vol. 36, no. 2, February 2015.
14. Fully Depleted SOI Characterization by Capacitance Analysis of p-i-n
Gated Diodes, Carlos Navarro, IEEE EDL, vol. 36, no. 1, January 2015.
15. High-Q MOS Varactors for Millimeter-Wave Applications in CMOS 28-nm
FDSOI, Thomas Quemerais, IEEE EDL, vol. 36, no. 2, February 2015.
16. Impact of Self-Heating on the Statistical Variability in Bulk and SOI FinFETs, Liping Wang, IEEE TED, vol. 62, no. 7, July 2015.
17. Impact of SourceDrain Series Resistance on Drain Current Mismatch in
Advanced Fully Depleted SOI n-MOSFETs, E. G. Ioannidis, IEEE EDL,
vol. 36, no. 5, May 2015.
18. Variation of Lateral Width Technique in SoI High-Voltage Lateral DoubleDiffused MetalOxideSemiconductor Transistors Using High-k Dielectric,
Yufeng Guo, IEEE EDL, vol. 36, no. 3, March 2015.
19. 3D Atomistic Simulations of Bulk, FDSOI and FinFETs Sensitivity to
Oxide Reliability, L. Gerrer, IEEE SISPAD, September 2014.
20. A mobility enhancement strategy for sub-14nm power-efficient FDSOI
technologies, B.DeSalvo, IEDM 2014.
21. A Simulation Study of SoI-Like Bulk Silicon MOSFET with Improved
Performance, Ying Wang, IEEE TED, vol. 61, no. 9, September 2014.
22. CMOS VT Characterization by Capacitance Measurements in FDSOI PIN
Gated Diodes, Carlos Navarro, ESSDERC 2014.
23. Dual Ground Plane EDMOS in Ultrathin FDSOI for 5V Energy Management Applications, Antoine Litty, ESSDERC 2014.
24. Evidence of Sub-Band Modulated Transport in Planar Fully Depleted
Silicon-on-Insulator MOSFETs, Gilberto A. Umana-Membreno, IEEE EDL,
vol. 35, no. 11, November 2014.
25. Experimental and theoretical investigation of the apparent mobility degradation in Bulk and UTBB-FDSOI devices- a focus on the near-spacerregion resistance, D. Rideau, SISPAD 2014.
26. FDSOI bottom MOSFETs stability versus top transistor thermal budget
featuring 3D monolithic integration, C. Fenouillet-Beranger, ESSDERC
2014.

27. FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX
Extendable to the 10nm Node, Q. Liu, IEDM 2014.
28. High Ion/Ioff Ge-source ultrathin body strained-SOI Tunnel FETs, Minsoo Kim, IEDM 2014.
29. Impacts of Back Gate Bias Stressing on Device Characteristics for Extremely Thin SoI (ETSoI) MOSFETs, Zhaoyun Tang, IEEE EDL, vol.
35, no. 3, March 2014.
30. Improvement of RF Performance by Using Tunnel Diode Body Contact
Structure in PD SOI nMOSFETs, Kai Lu, IEEE EDL, vol. 35, no. 1,
January 2014.
31. Joint Impact of Random Variations and RTN on Dynamic Writeability in
28nm Bulk and FDSOI SRAM, Brian Zimmer, ESSDERC 2014.
-EOT HfO2 UTBB-FD-SOI MOS32. Mobility Improvement Study for 8-A
FET Based on the Direct Extraction of the Back-Channel Mobility, Lionel
Trojman, IEEE TED, vol. 61, no. 11, November 2014.
33. Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI
MOSFETsPart I-Preparation for Modeling Based on Conformal Mapping, Tatsuya Yamada, IEEE TED, vol. 61, no. 9, September 2014.
34. Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI
MOSFETsPart II-Model Derivation and Validity Confirmation, Tatsuya
Yamada, IEEE TED, vol. 61, no. 9, September 2014.
35. Monte Carlo study of effective mobility in short channel FDSOI MOSFETs, Sebastien Guarnay, SISPAD 2014.
36. Overestimation of Short-Channel Effects Due to Intergate Coupling in
Advanced FDSOI nMOSFETs, Carlos Navarro, IEEE TED, vol. 61, no.
9, September 2014.
37. Quantum Modeling of the Carrier Mobility in FDSOI Devices, Viet-Hung
Nguyen, IEEE TED, vol. 61, no. 9, September 2014.
38. Statistical Analysis of Dynamic Variability in 28nm FD-SOI MOSFETs,
E.G.Ioannidis, ESSDERC 2014.
39. Strain and Layout Management in dual Channel (sSOI substrate, SiGe
channel) planar FDSOI MOSFETs, F. Andrieu, ESSDERC 2014.
40. Superior Performance and hot carrier reliability of Strained FDSOI nMOSFETs for Advanced CMOS Technology nodes, g. Besnard, ESSDERC
2014.

41. The importance of the spacer region to explain short channels mobility
collapse in 28nm Bulk and FDSOI technologies, F. Monsieur, ESSDERC
2014.
42. Back-Gate Bias Dependence of the Statistical Variability of FDSOI MOSFETs with thin BOX, Yunxiang Yang, IEEE TED, vol. 62, no. 2, February 2013.
43. Bias-Engineered Mobility in Advanced FD-SOI MOSFETs, Cristina Fernandez, IEEE EDL, vol. 34, no. 7, July 2013.
44. Compact Modeling of SOI MOSFETs with Ultra Thin Silicon and BOX
Layers, Mitiko Miura-Mattausch, IEEE TED, vol. 61, no. 2, February
2013.
45. Comparison of Self-Heating Effect (SHE) in Short-Channel Bulk and UltraThin BOX SOI MOSFETs-Impacts of Doped Well, Ambient Temperature,
and SOI or BOX Thicknesses on SHE, Tsunaki Takahashi, IEDM 2013.
46. Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs, Qian Xie, IEEE TED, vol. 60, no. 6, June 2013.
47. Evaluation of Spin Lifetime in Strained UT2B Silicon-On-Insulator MOSFETs, Dmitri Osintsev, SISPAD 2013.
48. Gate-Last Integration on Planar FDSOI MOSFET-Impact of Mechanical
Boosters and Channel Orientations, S. Morvan, IEDM 2013.
49. Heat Channeling in Extremely Thin SOI Devices-A Simulation Study,
Charis Mina Orfanidou, IEEE TED, vol. 60, no. 10, October 2013.
50. High Performance UTBB FDSOI Devices Featuring 20nm Gate Length
for 14nm Node and Beyond, Q. Liu, IEDM 2013.
51. High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs
Featuring SiGe Source and Drain-Vth Tuning, Variability, Access Resistance and Mobility Issues, Anthony Villalon, IEEE TED, vol. 60, no. 5,
May 2013.
52. Hole Transport in Strained and Relaxed SiGe Channel Extremely Thin
SOI MOSFETs, Ali Khakifirooz, IEEE EDL, vol. 34, no. 11, November
2013.
53. Impact of back biasing in Ultra Short Channel UTBB SOI nMOSFETs,
Kai Zhao, SISPAD 2013.
54. Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs- Experiment vs Simulation, Alexandre
Subirats, IEEE TED, vol. 60, no. 8, August 2013.

55. Improvement of Electrical Properties in a Novel PDSOI MOSFET with

Emphasizing on the Hysteresis Effect, Mohammad K. Anvarifard, IEEE
TED, vol. 60, no. 10, October 2013.
56. Innovative ESD Protections for UTBB FD-SOI Technology, Yohann Solaro, IEDM 2013.
57. Magnetoresistance measurements and unusual mobilitiy behavior in FD
MOSFETs, Sung-Jae Chang, ESSDERC 2013.
58. Mechanism of Super Steep Subthreshold Slope Characteristics with BodyTied SOI MOSFET, Takayiki Mori, SISPAD 2013.
59. Mobility in High-K Metal Gate UTBB-FDSOI Devices- from NEGF to
TCAD perspectives, D. Rideau, IEDM 2013.
60. Novel Back-Biased UTBB Lateral SCR for FDSOI ESD Protections, Yohann
Solaro, ESSDERC 2013.
61. Operating Voltage Constraints in 45-nm SOI nMOSFETs and Cascode
Cores, Rajan Arora, IEEE TED, vol. 60, no. 1, January 2013.
62. Quantitative Extraction of Electric Flux in the Buried Oxide Layer and
investigation of its effects on MOSFETs characteristics, Tatsuya Yamada,
IEEE TED, vol. 60, no. 12, December 2013.
63. Suppression of Drain-Induced Barrier Lowering in SOI MOSFETs through
Source-Drain Engineering for Low-Operating-Power System-on-Chip Applications, Tatsuya Yamada, IEEE TED, vol. 60, no. 1, January 2013.
64. Technology Downscaling Worsening Radiation Effects in Bulk- SOI to the
Rescue, Philippe Roche, IEDM 2013.
65. Threshold Voltage Extraction Techniques and Temperature Effect in Context of Global Variability in UTBB MOSFETs, S. Makovejev, ESSDERC
2013.
66. Why are SCE overestimated in FD-SOI MOSFETs, C. Navarro, ESSDERC 2013.
67. A Tunnel Diode Body Contact Structure for High-Performance SOI MOSFETs, Jiexin Luo, IEEE TED, vol. 59, no. 1, January 2012.
68. AC Transconductance: A Novel Method to Characterize Oxide Traps in
Advanced FETs without a Body Contact, X. Sun, IEDM 2012.
69. Accurate Calculation of Gate Tunneling Current in Double-Gate and SingleGate SOI MOSFETs Through Gate Dielectric Stacks, Ferney A. Chaves,
vol. 59, no. 10, October 2012.

70. Carrier-Mobility Enhancement via Strain Engineering in Future ThinBody MOSFETs, Nuo Xu, IEEE EDL, vol. 33, no. 3, March 2012.
71. Dependence of GenerationRecombination Noise with Gate Voltage in FDSOI MOSFETs, Abraham Luque Rodriguez, IEEE TED, vol. 59, no. 10,
October 2012.
72. Experimental Investigation of Hole Transport in Strained Si1 -xGex /SOI
pMOSFETsPart I: Scattering Mechanisms in Long-Channel Devices,
Mikael Casse, IEEE TED, vol. 59, no. 2, February 2012.
73. Experimental Investigation of Hole Transport in Strained Si1 -xGex /SOI
pMOSFETsPart II: Mobility and High-Field Transport in Nanoscaled
PMOS, Mikael Casse, IEEE TED, vol. 59, no. 3, March 2012.
74. Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs, Mohd Khairuddin Md Arshad, IEEE TED, vol. 59, no. 1, January
2012.
75. High Performance Extremely Thin SOI (ETSOI) Hybrid CMOS with Si
Channel NFET and Strained SiGe Channel PFET, K. Cheng, IEDM 2012.
76. Hole Mobilities of Si/Si0.5 Ge0.5 Quantum-Well Transistor on SOI and
Strained SOI, W. Yu, IEEE EDL, vol. 33, no. 6, June 2012.
77. Impact of front-back gate coupling on low frequency noise in 28 nm FDSOI
MOSFETs, Christoforos G. Theodorou, ESSDERC 2012.
78. Impact of Mechanical Strain on GIFBE in PD SOI p-MOSFETs as Indicated from NBTI Degradation, Wen-hung Lo, IEEE EDL, vol. 33, no. 3,
March 2012.
79. Investigation of Temperature-Dependent High-Frequency Noise Characteristics for Deep-Submicrometer Bulk and SOI MOSFETs, Sheng-Chung
Wan, IEEE TED, vol. 59, no. 3, March 2012.
80. Mobility Enhancement by Back-Gate Biasing in Ultrathin SOI MOSFETs
with Thin BOX, A. Ohata, IEEE EDL, vol. 33, no. 3, March 2012.
81. Multibranch Mobility Analysis for the Characterization of FDSOI Transistors, Carlos Navarro, IEEE EDL, vol. 33, no. 8, August 2012.
82. Multibranch Mobility- Characterization Evidence of Carrier Mobility Enhancement by Back-Gate Biasing in FD-SOI MOSFET, Carlos Navarro,
ESSDERC 2012.
83. New parameter extraction method based on split C-V for FDSOI MOSFETs, I. Ben Akkez, ESSDERC 2012.
84. On the Interpretation of Ballistic Injection Velocity in Deeply Scaled MOSFETs, Yang Liu, IEEE TED, vol. 59, no. 4, April 2012.
6

85. On The UTBB SOI MOSFET Performance Improvement In Quasi-DoubleGate Regime, V. Kilchytska, ESSDERC 2012.
86. Scalability of Extremely Thin SOI (ETSOI) MOSFETs to Sub-20nm Gate
Length, Ali Khakifirooz, IEEE EDL, vol. 33, no. 2, February 2012.
87. Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI-Impact
of Barrier Lowering, J. L. Padilla, IEEE TED, vol. 59, no. 5, May 2012.
88. Spatial Composition Grading of Binary Metal Alloy Gate Electrode for
Short-Channel SOI or SON MOSFET Application, Bibhas Manna, IEEE
TED, vol. 59, no. 10, October 2012.
89. Statistical Variability in Fully Depleted SOI MOSFETs due to RDF in
the source and drain extensions, Stanislav Markov, IEEE EDL, vol. 33,
no. 3, March 2012.
90. Subbandgap Optical Differential Body-Factor Technique and Characterization of Interface States in SOI MOSFETs, Euiyoun Hong, IEEE EDL,
vol. 33, no. 7, July 2012.
91. Switching Energy Efficiency Optimization for Advanced CPU thanks to
UTBB Technology, F.Arnaud, IEDM 2012.
92. The Best Control of Parasitic BJT Effect in SOI-LDMOS With SiGe Window Under Channel, Ali A. Orouji, IEEE TED, vol. 59, no. 2, February
2012.
93. UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm
node and below, L. Grenouillet, IEDM 2012.
94. A Tunnel Diode Body Contact Structure to Suppress the Floating-Body
Effect in Partially Depleted SOI MOSFETs, Jing Chen, IEEE EDL, vol.
32, no. 10, October 2011.
95. Analysis of Transconductance (gm) in Schottky Barrier MOSFETs, SungJin Choi, IEEE TED, vol. 58, no. 2, February 2011.
96. Assessment of Fully-Depleted Planar CMOS for Low Power Complex Circuit, Z. Ren, IEDM 2011.
97. Compact Capacitance and Capacitive Coupling-Noise Modeling of ThroughOxide Vias in FDSOI Based Ultra-High Density 3-D ICs, Chuan Xu,
IEDM 2011.
98. Compact Modeling of Partially Depleted SOI Drain-Extended MOSFET
(DEMOSFET) Including High-Voltage and Floating-Body Effects, Tarun
Kumar Agarwal, IEEE TED, vol. 58, no. 10, October 2011.

99. Comparison of SOI and Partial-SOI LDMOSFETs Using Electrical-ThermalStress Coupled-Field Effect, Cher Ming Tan, IEEE TED, vol. 58, no. 10,
October 2011.
100. Complementary Thin-Base Symmetric Lateral Bipolar Transistors on SOI,
Jin Cai, IEDM 2011.
101. Drain current variability and MOSFET parameters correlations in planar
FDSOI Technology, J. Mazurier, IEDM 2011.
102. Effects of Device Structure and Back Biasing on HCI and NBTI in SilicononThin-Box (SOTB) CMOSFET, IEEE TED, vol. 58, no. 4, April 2011.
103. Experimental Evidence of Increased Deformation Potential at MOS Interface and Its Impact on Characteristics of ETSOI FETs, Teruyuki Ohashi,
IEDM 2011.
104. First Demonstration of Ultrathin Body c-SiGe Channel FDSOI pMOSFETs combined with SiGe(B) RSD- Drastic Improvement of Electrostatics (Vth,p tuning, DIBL) and Transport (0, Isat) Properties down to
23nm Gate Length, C. Le Royer, IEDM 2011.
105. High-Performance Partially Depleted SOI PFETs With In Situ Doped
SiGe Raised Source-Drain and Implant-Free Extension, Ali Khakifirooz,
vol. 32, no. 3, March 2011.
106. Impact of Substrate Bias on GIDL for Thin-BOX ETSOI Devices, P.
Kulkarni, SISPAD 2011.
107. Improved extraction of GIDL in FDSOI devices for proper junction quality
analysis, C. Xu, ESSDERC 2011.
108. In-Depth Study of Quantum Effects in SOI DGMOSFETs for Different
Crystallographic Orientations, Mara Balaguer, IEEE TED, vol. 58, no.
10, October 2011.
109. Local-Stress-Induced Trap States in SOI Layers With Different Levels of
Roughness at SOI-BOX Interfaces, Yoshikata Nakajima, IEEE EDL, vol.
32, no. 3, March 2011.
110. Low frequency noise variability in high-k-metal gate stack 28nm bulk and
FD-SOI CMOS Transistors, E. G. Ioannidis, IEDM 2011.
111. Modeling of SOI-LDMOS Transistor Including Impact Ionization, Snapback, and Self Heating, Ujwal Radhakrishna, IEEE TED, vol. 58, no. 11,
November 2011.
112. Narrow-Width Effects on a Body-Tied Partially Depleted SOI MOSFET,
Raphael Valentin, IEEE TED, vol. 58, no. 11, November 2011.

113. On the MOSFET Threshold Voltage Extraction by Transonductance-toCurrent Ration Change Methods-Part I- Effect of Gate Voltage Dependent
Mobility, Tamara Rudenko, IEEE TED, vol. 58, no. 12, December 2011.
114. On the MOSFET Threshold Voltage Extraction by Transonductance-toCurrent Ration Change Methods-Part I- Effect of Drain Voltage, Tamara
Rudenko, IEEE TED, vol. 58, no. 12, December 2011.
115. On the Origin of Gate-Induced Floating-Body Effect in PD SOI p-MOSFETS,
Chih-Hao Dai, IEEE EDL, vol. 32, no. 7, July 2011.
116. Parasitic bipolar impact in 32nm undoped channel Ultra-Thin BOX (UTBOX) and biased Ground Plane FDSOI high-k metal gate technology,
C.Fenouillet-Beranger, ESSDERC 2011.
117. Performance of Localized-SOI MOS Devices on (110) Substrates-Impact
of Channel Direction, J.-L. Huguenin, IEEE EDL, vol. 32, no. 8, August
2011.
118. Self-Heating Induced Feedback Effect on Drain Current Mismatch and Its
Modeling, Jack J.-Y. Kuo, IEDM 2011.
119. Simulation of Ab Initio Quantum Confinement Scattering in UTB MOSFETs Using Three-Dimensional Ensemble Monte Carlo, Craig Riddet,
IEEE TED, vol. 58, no. 3, March 2011.
120. Transistor Matching and Silicon Thickness Variation in ETSOI Technology, Terence B. Hook, IEDM 2011.
121. Ultralow Specific On-Resistance High-Voltage SOI Lateral MOSFET, IEEE
EDL, vol. 32, no. 2, February 2011.
122. Unusual CV Characteristics of High-Resistivity SOI Wafers, P. Nayak,
IEEE EDL, vol. 32, no. 12, December 2011.
123. Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET
and Trigate Bulk MOSFET Designs, Xin Sun, IEEE TED, vol. 58, no.
10, October 2011.
124. A Low-Field Mobility Model for Bulk and Ultrathin-Body SOI p-MOSFETs
with Different Surface and Channel Orientations, Luca Silvestri, IEEE
TED, vol. 57, no. 12, December 2010.
125. A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide2D Simulation Study, Sajad A. Loan, IEEE TED, vol. 57, no. 3, March
2010.
126. Anomalous Electron Mobility in Extremely-Thin SOI (ETSOI) Diffusion
Layers with SOI Thickness of Less Than 10 nm and High Doping Concentration of Greater Than 11018 cm3 , Naotoshi Kadotani, IEDM 2010.

127. Direct Measurement of MOSFET Channel Strain by Means of Backside

Etching and Raman Spectroscopy on Long-Channel Devices, Rouzet M.
B. Agaiby, vol. 31, no. 5, May 2010.
128. Dual Channel and Strain for CMOS Co-Integration in FDSOI Device Architecture, C. Le Royer, ESSDERC 2010.
129. Effects of Substrate Orientation and Channel Stress on Short-Channel
Thin SOI MOSFETs, Amlan Majumdar, IEEE TED, vol. 57, no. 9,
September 2010.
130. External Stresses on Tensile and Compressive Contact Etching Stop Layer
SOI MOSFETs, Wen-Teng Chang, vol. 57, no. 8, August 2010.
131. Fully Depleted Silicon-On-Insulator with back bias and strain for Low
Power and High Performance applications, F. Andrieu, ICICDT 2010.
132. Fully Depleted Strained Silicon-on-Insulator pMOSFETs with Recessed
and Embedded Silicon-Germanium Source-Drain, Sophie Baudot, IEEE
EDL, vol. 31, no. 10, October 2010.
133. High Performance and Low Variability Fully-Depleted Strained-SOI MOSFETs, J. Mazurier, 2010 IEEE International SOI Conference.
134. High--Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source-Drain With sub-30nm Gate Length, Marwan H. Khater, IEEE
EDL, vol. 31, no. 4, April 2010.
135. Hybrid Integration of Ultrathin-Body Partially Insulated MOSFETs and
a Bulk MOSFET for Better IC Performance-A Multiple Vth Technology
Using Partial SOI Structure, Chang Woo Oh, IEEE EDL, vol. 31, no. 1,
January 2010.
136. Hybrid Localized SOI-Bulk technology for Low Power System-on-Chip, J.L. Huguenin, 2010 Symposium on VLSI Technology Digest of Technical
Papers.
137. Insights on Design and Scalability of Thin-Box FD or SOI CMOS, Siddharth Chouksey, IEEE TED, vol. 57, no. 9, September 2010.
138. LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide, Ran Yan, IEEE TED, vol. 57, no. 6, June
2010.
139. Local Vth Variability and Scalability in Silicon-on-Thin-BOX (SOTB)
CMOS With Small RDF, Nobuyuki Sugii, IEEE TED, vol. 57, no. 4,
April 2010.
140. Localized SOI Logic and Bulk I/O devices co-integration for Low Power
System-on-Chip Technology, J.-L. Huguenin, 2010 VLSI-TSA.

10

141. Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide
(UT2B) SOI Technology for 20nm Low Power CMOS and Beyond, F. Andrieu, 2010 Symposium on VLSI Technology Digest of Technical Papers.
142. New Insight on VT stability of HK-MG stacks with scaling in 30nm FDSOI
technology, L. Brunet, 2010 Symposium on VLSI Technology Digest of
Technical Papers.
143. Novel Low-k Dielectric Buried-Layer High-Voltage LDMOS on Partial
SOI, Xiaorong Luo, IEEE TED, vol. 57, no. 2, February 2010.
144. On the Origin of Hole Valence Band Injection on GIFBE in PD SOI nMOSFETs, Chih-Hao Dai, IEEE EDL, vol. 31, no. 6, June 2010.
145. Origins of Universal Mobility Violation in SOI MOSFETs, N. Rodriguez,
ESSDERC 2010.
146. PBTI/NBTI-Related Variability in TB-SOI and DG MOSFETs, B. Cheng,
IEEE EDL, vol. 31, no. 5, May 2010.
147. Planar FDSOI technology for sub 22nm nodes, O. Faynot, 2010 VLSITSA.
148. Planar Fully Depleted SOI Technology- a powerful architecture for the
20nm node and beyond, O. Faynot, IEDM 2010.
149. Radio-Frequency Study of Dopant-Segregated n-Type SB-MOSFETs on
Thin-Body SOI, Christoph Urban, IEEE EDL, vol. 31, no. 6, June 2010.
150. Realizing Super-Steep Subthreshold Slope with Conventional FDSOI CMOS
at Low-Bias Voltages, Z. Lu, IEDM 2010.
151. Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs,
Nima Dehdashti Akhavan, IEEE TED, vol. 57, no. 5, May 2010.
152. Stress Liner Effects for 32-nm SOI MOSFETs with HKMG, Ming Cai,
IEEE TED, vol. 57, no. 7, July 2010.
153. Suppression of Electron Mobility Degradation in (100)-Oriented DoubleGate Ultrathin Body nMOSFETs, Ken Shimizu, IEEE EDL, vol. 31, no.
4, April 2010.
154. The Impact of Oxide Traps Induced by SOI Thickness on Reliability of
Fully Silicide Metal-Gate Strained SOI MOSFET, Cheng-Li Lin, IEEE
EDL, vol. 31, no. 2, February 2010.
155. Thermal Circuit for SOI MOSFET Structure Accounting for Nonisothermal Effects, Kun Zhang, IEEE TED, vol. 57, no. 11, November 2010.
156. Thermal Noise in MOSFETs- A Two- or a Three-Parameter Noise Model,
Mostafa Emam, IEEE TED, vol. 57, no. 5, May 2010.
11

157. UT2B-FDSOI Device Architecture Dedicated to Low Power Design Techniques, J.-P. Noel, ESSDERC 2010.
158. Why the Universal Mobility Is Not, Sorin Cristoloveanu, IEEE TED, vol.
57, no. 6, June 2010.
159. A High-Voltage LDMOS Compatible With High-Voltage Integrated Circuits on p-Type SOI Layer, Xiaorong Luo, IEEE EDL, vol. 30, no. 10,
October 2009.
160. Gate Length and Performance Scaling of Undoped-Body Extremely Thin
SOI MOSFETs, Amlan Majumdar, IEEE EDL, vol. 30, no. 4, April 2009.
161. In Situ Comparison of Si/High-k and Si/SiO2 Channel Properties in SOI
MOSFETs, vol. 30, no. 10, October 2009.
162. A New Technique to Extract the Source/Drain Series Resistance of MOSFETs, Dominique Fleury, IEEE EDL, vol. 30, no. 9, September 2009.
163. Eliminating Back-Gate Bias Effects in a Novel SOI High-Voltage Device
Structure, Xiaorong Luo, IEEE TED, vol. 56, no. 8, August 2009.
164. Analog/RF Performance of Multichannel SOI MOSFET, Tao Chuan Lim,
IEEE TED, vol. 56, no. 7, July 2009.
165. Asymmetric Schottky Tunneling Source SOI MOSFET Design for MixedMode Applications, Ritesh Jhaveri, IEEE TED, vol. 56, no. 1, January
2009.
166. Self-Heating Effects in Nanoscale FD SOI Devices: The Role of the Substrate, Boundary Conditions at Various Interfaces, and the Dielectric Material Type for the BOX, Dragica Vasileska, IEEE TED, vol. 56, no. 12,
December 2009.
167. Revisited Pseudo-MOSFET Models for the Characterization of Ultrathin
SOI Wafers, Noel Rodriguez, IEEE TED, vol. 56, no. 7, July 2009.
168. Thermal Modeling and Device Noise Properties of Three-DimensionalSOI
Technology, Tze Wee Chen, IEEE TED, vol. 56, no. 4, April 2009.
169. Undoped-Body Extremely Thin SOI MOSFETs With Back Gates, Tze
Wee Chen, IEEE TED, vol. 56, no. 10, October 2009.
170. Impact of Lateral Asymmetric Channel Doping on 45-nm-Technology NType SOI MOSFETs, Hasan M. Nayfeh, IEEE TED, vol. 56, no. 12,
December 2009.
171. Field Enhancement for Dielectric Layer of High-Voltage Devices on Silicon
on Insulator, Bo Zhang, IEEE TED, vol. 56, no. 10, October 2009.

12

172. Impact Ionization and Freeze-Out Model for Simulation of Low Gate Bias
Kink Effect in SOI-MOSFETs Operating at Liquid He Temperature, A.
Akturk, SISPAD 2009.
173. Dual metallic source and drain integration on planar Single and Double
Gate SOI CMOS down to 20nm: Performance and scalability assessment,
L. Hutin, IEDM 2009.
174. Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for
Low Power System-on-Chip Applications , K. Cheng, IEDM 2009.
175. Technologies to further reduce soft error susceptibility in SOI, P. Oldiges,
IEDM 2009.
176. Hybrid FDSOI/Bulk high-k/Metal gate platform for Low Power (LP) multimedia technology, C.Fenouillet-Beranger, IEDM 2009.
177. Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below, C. Fenouillet-Beranger, ESSDERC
2009.
178. A simple and efficient concept for setting up multi-VT devices in thin BOx
fully-depleted SOI technology, J.-P. Noel, ESSDERC 2009.
179. Width and orientation effects in strained FDSOI MOSFETs: strain and
device characterization, S. Baudot, ESSDERC 2009.
180. Comparison between 65nm bulk and PD-SOI MOSFETs: Si/BOX interface effect on point defects and doping profiles, E.M. Bazizi, ESSDERC
2009.
181. Analog, RF and nonlinear behaviors of submicron graded channel partially
depleted SOI MOSFETs, M. Emam, ESSDERC 2009.
182. Drain / substrate coupling impact on DIBL of Ultra Thin Body and BOX
SOI MOSFETs with undoped channel, S. Burignat, ESSDERC 2009.
183. Realization of High Voltage ( 700 V) in New SOI Devices With a Compound Buried Layer, Xiaorong Luo, IEEE EDL, vol. 29, no. 12, December
2008.
184. High-Performance Undoped-Body 8-nm-Thin SOI Field-Effect Transistors, IEEE EDL, vol. 29, no. 5, May 2008.
185. Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STIInduced Mechanical Stress Effect, V. C. Su, IEEE EDL, vol. 29, no. 6,
June 2008.
186. SB-MOSFETs in UTB-SOI Featuring PtSi Source/Drain With Dopant
Segregation, Zhen Zhang, IEEE EDL, vol. 29, no. 1, January 2008.

13

187. Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI
pMOSFETs, Rahul Mishra, IEEE EDL, vol. 29, no. 3, March 2008.
188. Is SOD Technology the Solution to Heating Problems in SOI Devices?,
Katerina Raleva, IEEE EDL, vol. 29, no. 6, June 2008.
189. Characterization of the Back Interface in Strained-Silicon-on-Insulator
Channel and Enhancement of Electrical Properties by Heat Treatment,
Myung-Ho Jung, IEEE EDL, vol. 29, no. 12, December 2008.
190. Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation, Claudio Fiegna, IEEE TED, vol. 55, no. 1, January
2008.
191. Characterization of Distribution of Trap States in Silicon-on-Insulator
Layers by Front-Gate Characteristics in n-Channel SOI MOSFETs, Kenji
Kajiwara, IEEE TED, vol. 55, no. 7, July 2008.
192. Physical Model of Noise Mechanisms in SOI and Bulk-Silicon MOSFETs
for RF Applications, Alberto O. Adan, IEEE TED, vol. 55, no. 3, March
2008.
193. Threshold Voltage Model of Short-Channel FD-SOI MOSFETs With Vertical Gaussian Profile, Guohe Zhang, IEEE TED, vol. 55, no. 3, March
2008.
194. Threshold Voltage Variation in SOI Schottky-Barrier MOSFETs, Min
Zhang, IEEE TED, vol. 55, no. 3, March 2008.
195. Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for
Adaptive Threshold Voltage and Leakage Control, Tetsu Ohtou, IEEE
TED, vol. 55, no. 1, January 2008.
196. Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region, Pradeep Agarwal, IEEE TED, vol. 55, no. 3,
March 2008.
197. A New Impact-Ionization Current Model Applicable to Both Bulk and SOI
MOSFETs by Considering Self-Lattice-Heating, Chengqing Wei, IEEE
TED, vol. 55, no. 9, September 2008.
198. A New Impact-Ionization Current Model Applicable to Both Bulk and SOI
MOSFETs by Considering Self-Lattice-Heating, Chengqing Wei, IEEE
TED, vol. 55, no. 9, September 2008.
199. Shallow-Trench-Isolation (STI)-Induced Mechanical-Stress-Related KinkEffect Behaviors of 40-nm PD SOI NMOS Device, V. C. Su, IEEE TED,
vol. 55, no. 6, June 2008.

14

200. Investigation of Thermal Crosstalk Between SOI FETs by the Subthreshold Sensing Technique, Manu Shamsa, IEEE TED, vol. 55, no. 7, July
2008.
201. The Ground Plane in Buried Oxide for Controlling Short-Channel Effects
in Nanoscale SOI MOSFETs, M. Jagadesh Kumar, IEEE TED, vol. 55,
no. 6, June 2008.
202. A Tight-Binding Study of the Ballistic Injection Velocity for UltrathinBody SOI MOSFETs, Yang Liu, IEEE TED, vol. 55, no. 3, March 2008.
203. Optimal Dual- VT Design in Sub-100-nm PD/SOI and Double-Gate Technologies, Aditya Bansal, IEEE TED, vol. 55, no. 5, May 2008.
204. Consistent higher-order transport models for SOI MOSFETs, Martin Vasicek, SISPAD 2008.
205. Experimental investigation on the origin of direction dependence of Si
(110) hole mobility utilizing ultra-thin body pMOSFETs, Ken Shimizu,
IEDM 2008.
206. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding, O. Weber, IEDM 2008.
207. On the difference of temperature dependence of metal gate and poly gate
SOI MOSFET threshold voltages, Shu-Jen Han, IEDM 2008.
208. Gate length scaling and high drive currents enabled for high performance
SOI technology using high-k/metal gate, K. Henson, IEDM 2008.
209. Implementation and optimization of asymmetric transistors in advanced
SOI CMOS technologies for high performance microprocessors, J. Hoentschel,
IEDM 2008.
210. Process-induced SOI strain via sacrificial Ge-Si, Daniel Connelly, ESSDERC 2008.
211. Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs, B. Cheng, ESSDERC 2008.
212. New floating-body effect in partially depleted SOI pMOSFET due to
direct-tunneling current in the partial n+ poly gate, G. Guegan, ESSDERC 2008.
213. On the stability of fully depleted SOI MOSFETs under lithography process
variations, Christian Kampen, ESSDERC 2008.
214. FDSOI devices with thin BOX and ground plane integration for 32nm
node and below, C. Fenouillet-Beranger, ESSDERC 2008.

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215. Duration of the High Breakdown Voltage Phase in Deep Depletion SOI
LDMOS, Ettore Napoli, IEEE EDL, vol. 28, no. 8, August 2007.
216. Impact of Parameter Variations and Random Dopant Fluctuations on
Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX,
Tetsu Ohtou, IEEE EDL, vol. 28, no. 8, August 2007.
217. Improved Carrier Injection in Ultrathin-Body SOI Schottky-Barrier MOSFETs, M. Zhang, IEEE EDL, vol. 28, no. 3, March 2007.
218. Substrate Bias Effect Linked to Parasitic Series Resistance in MultipleGate SOI MOSFETs, Tamara Rudenko, IEEE EDL, vol. 28, no. 9,
September 2007.
219. Impact of High-k Offset Spacer in 65-nm Node SOI Devices, Ming-Wen
Ma, IEEE EDL, vol. 28, no. 3, March 2007.
220. Electron Transport in Strained-Silicon Directly on Insulator UltrathinBody n-MOSFETs With Body Thickness Ranging From 2 to 25 nm,
Leonardo Gomez, IEEE EDL, vol. 28, no. 4, April 2007.
221. On the Origin of the Excess Low-Frequency Noise in Graded-Channel
Silicon-on-Insulator nMOSFETs, Eddy Simoen, IEEE EDL, vol. 28, no.
10, October 2007.
222. Valence Band Offset Measurements on Thin Silicon-on-Insulator MOSFETs, J.-L. P. J. van der Steen, IEEE EDL, vol. 28, no. 9, September
2007.
223. Modeling of Surface-Roughness Scattering in Ultrathin-Body SOI MOSFETs, Seonghoon Jin, IEEE TED, vol. 54, no. 9, September 2007.
224. Low-Field Electron Mobility Model for Ultrathin-Body SOI and DoubleGate MOSFETs With Extremely Small Silicon Thicknesses, Susanna Reggiani, IEEE TED, vol. 54, no. 9, September 2007.
225. A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs, Weimin Wu, IEEE TED, vol. 54, no. 2,
February 2007.
226. Threshold-Voltage Control of AC Performance Degradation-Free FD SOI
MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme,
Tetsu Ohtou, IEEE TED, vol. 54, no. 2, February 2007.
227. Characterization of the Body Node in PD SOI MOSFETs Using Multiport VNA Measurements, Dimitri Lederer, IEEE TED, vol. 54, no. 11,
November 2007.
228. Multisubband Monte Carlo Study of Transport, Quantization, and ElectronGas Degeneration in Ultrathin SOI n-MOSFETs, Luca Lucci, IEEE TED,
vol. 54, no. 5, May 2007.
16

229. A Simulation Study of the Switching Times of 22- and 17-nm Gate-Length
SOI nFETs on High Mobility Substrates and Si, Steven E. Laux, IEEE
TED, vol. 54, no. 9, September 2007.
230. Record RF performance of 45-nm SOI CMOS Technology, Sungjae Lee,
IEDM 2007.
231. 45nm SOI CMOS Technology with 3X hole mobility enhancement and
Asymmetric transistor for high performance CPU application, Samuel
K.H. Fung, IEDM 2007.
232. Measurements of Inter-and-Intra Device Transient Thermal Transport on
SOI FETs, P. M. Solomon, IEDM 2007.
233. Localized SOI technology: an innovative Low Cost self-aligned process for
Ultra Thin Si-film on thin BOX integration for Low Power applications,
S.Monfay, IEDM 2007.
234. Mobility Enhancement in Uniaxially Strained (110) Oriented Ultra-Thin
Body Single- and Double-Gate MOSFETs with SOI Thickness of Less
Than 4 nm, Ken Shimizu, IEDM 2007.
235. Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and
Beyond, Jin Cai, IEDM 2007.
236. Impact of the gate stack on the electrical performances of 3D multi-channel
MOSFET (MCFET) on SOI, E. Bernard, ESSDERC 2007.
237. Thermal resistance reduction in power MOSFETs integrated in a 65nm
SOI technology, O. Bon, ESSDERC 2007.
238. Trading off static power and dynamic performance in CMOS digital circuits: bulk versus double gate SOI MOSFETs, M. Agostinelli, ESSDERC
2007.
239. Fully-depleted SOI CMOS technology using WXN metal gate and HfSixOyNZ high-k dielectric, D. Aime, ESSDERC 2007.
240. Mobility issues in double-gate SOI MOSFETs: Characterization and analysis, N. Rodriguez, ESSDERC 2007.
241. Fabrication, characterization and modeling of strained SOI MOSFETs
with very large effective mobility, F.Driussi, ESSDERC 2007.
242. Scalability of Hole Mobility Enhancement in Biaxially Strained Ultrathin
Body SOI, Ali Khakifirooz, IEEE EDL, vol. 27, no. 5, May 2006.
243. Abnormal drain current (ADC) effect and its mechanism in FD SOI MOSFETs, Jang-Gn Yun, IEEE EDL, vol. 27, no.

17

244. Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC
channels, J. Hallstedt, IEEE EDL, vol. 27, no. 6, June 2006.
245. Effect of tensile uniaxial stress on the electron transport properties of
deeply scaled FD-SOI n-type MOSFETs, H. M. Nayfeh, IEEE EDL, vol.
27, no. 4, April 2006.
246. Gate-dielectric permitivity and metal-gate work-function tradeoff in Lmet=25nm
PDSOI device characteristicss, Dechao Guo, IEEE EDL, vol. 27, no. 6,
June 2006.
247. Substrate engineering for improved transient breakdown voltage in SOI
lateral power MOS, Ettore Napoli, IEEE EDL, vol. 27, no. 8, August
2006.
248. Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/BuriedOxide Interface Stress for Partially Depleted SOI, Chien-Ting Lin, IEEE
EDL, vol. 27, no. 12, December 2006.
249. Off-state modulation of SOI floating-body, Josephine B. Chang, IEEE
EDL, vol. 27, no. 7, July 2006.
250. On the performance of single-gated ultrathin-body SOI Schottky-barrier
MOSFETs, Joachim Knoch, IEEE TED, vol. 53, no. 7, July 2006.
251. Completely Surface-Potential-Based Compact Model of the Fully Depleted
SOI-MOSFET Including Short-Channel Effects, Norio Sadachika, vol. 53,
no. 9, September 2006.
252. Performance enhancement of partially and fully depleted strained-SOI
MOSFETs, Toshinori Numata, vol. 53, no. 5, May 2006.
253. Analysis of the gate-source/drain capacitance behavior of a narrow-channel
FD SOI NMOS device considering the 3-D fringing capacitances using 3-D
simulation, Chien-Chung Chen, vol. 53, no. 10, October 2006.
254. SOI technology for radio-frequency integrated-circuit applications, Rong
Yang, vol. 53, no. 6, June 2006.
255. On the scaling limit of ultrathin SOI MOSFETs, Wei-Yuan Lu, vol. 53,
no. 5, May 2006.
256. The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs, Chieh-Ming Lai, vol.
53, no. 11, November 2006.
257. Gate capacitances behavior of nanometer FD SOI CMOS devices with
HfO2 high-k gate dielectric considering vertical and fringing displacement
effects using 2-D Simulation, Yu-Sheng Lin, IEEE TED, vol. 53, no. 6,
June 2006.

18

258. Quantum-mechanical suppression and enhancement of SCEs in ultrathin

SOI MOSFETs, Yasuhisa Omura, IEEE TED, vol. 53, no. 4, April 2006.
259. Mobility and threshold-voltage comparison between [110]- and (100)-oriented
ultrathin-body silicon MOSFETs, Gen Tsutsui, vol. 53, no. 10, October
2006.
260. Efficient Density Gradient Quantum Corrections for 3D Monte Carlo Simulations, C. Riddet, SISPAD 2006.
261. Simulation Study on Channel Length Scaling of High Performance Partially Depleted Metal Gate and Poly Gate SOI MOSFETs, Xinlin Wang,,
SISPAD 2006.
262. Effect of Body Doping on the Scaling of Ultrathin SOI MOSFETs, WeiYuan Lu, SISPAD 2006.
263. Power/Performance Based Scalability Comparisons between Conventional
and Novel Transistors Down to 32nm Technology Node, P. Kapur, SISPAD
2006.
264. Modeling of the Leakage Current Distribution of 16M Stacked Single Crystal (SC)-like SOI pMOSFETs using Greens function method, Byungjoon
Hwang, SISPAD 2006.
265. Strain Effects on Quasi-Bound State Tunneling in Advanced SOI CMOS
Technologies, M. Kamer, SISPAD 2006.
266. Novel Anisotropic Strain Engineering on (110)-Surface SOI CMOS Devices
using Combination of Local/Global Strain Techniques, T. Mizuno, IEDM
2006.
267. High Performance 45-nm SOI Technology with Enhanced Strain, Porous
Low-k BEOL, and Immersion Lithography, S. Narasimha, IEDM 2006.
268. Challenges and Opportunities for High Performance 32 nm CMOS Technology, J.W. Sleight, IEDM 2006.
269. Experimental Demonstrations of Superior Characteristics of Variable BodyFactor () Fully-Depleted SOI MOSFETs with Extremely Thin BOX of
10 nm, Tetsu Ohtou, IEDM 2006.
270. First ultra-thin film FDSOI devices with CMP-less TOtally SIlicided (TOSI)
gate Integration, C. Fenouillet-Beranger, ESSDERC 2006.
271. Orientation Dependence of the Low Field Mobility in Double-and Singlegate SOI FETs, Viktor Sverdlov, ESSDERC 2006.
272. High Performance 65nm SOI Transistors Using Laser Spike Annealing,
Tenko Yamashita, ESSDERC 2006.

19

273. A novel SOI lateral-power MOSFET with a self-aligned drift region, Lingpeng Guan, IEEE EDL, vol. 26, no. 4, April 2005.
274. Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs, Gen Tsutsui, IEEE EDL, vol. 26, no. 11, November 2005.
275. 30-nm recessed S/D SOI MOSFET with an ultrathin body and a low SDE
resistance, Chang-Geun Ahn, IEEE EDL, vol. 26, no. 7, July 2005.
276. Electrical characterization of SOI substrates incorporating WSix ground
planes, M. Bain, IEEE EDL, vol. 26, no. 2, February 2005.
277. Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain, Wei Zhao, IEEE EDL, vol. 26, no. 6, June
2005.
278. Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects, Valeriya Kilchytska, IEEE EDL, vol. 26, no. 10, October 2005.
279. Nanoscale FD/SOI CMOS: thick or thin BOX?, V. P. Trivedi, IEEE EDL,
vol. 26, no. 1, January 2005.
280. Hole transport in UTB MOSFETs in strained-Si directly on insulator with
strained-Si thickness less than 5 nm, Ingvar Aberg, IEEE EDL, vol. 26,
no. 9, September 2005.
281. Enhancement of electron mobility in ultrathin-body silicon-on-insulator
MOSFETs with uniaxial strain, Isaac Lauer, IEEE EDL, vol. 26, no. 5,
May 2005.
110 -surface strained-SOI CMOS devices, Tomohisa Mizuno, IEEE TED, vol.
52, no. 3, March 2005.
282. On the prediction of geometry-dependent floating-body effect in SOI MOSFETs, PinSu, IEEE TED, vol. 52, no. 7, July 2005.
283. Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation, Dragica
Vasileska, IEEE TED, vol. 52, no. 2, February 2005.
284. Two-dimensional analytical threshold voltage model of nanoscale fully depleted SOI MOSFET with electrically induced S/D extensions, M. Jagadesh Kumar, IEEE TED, vol. 52, no. 7, July 2005.
285. Control of threshold-voltage and short-channel effects in ultrathin strainedSOI CMOS devices, Toshinori Numata, IEEE TED, vol. 52, no. 8, August
2005.
286. Analysis and optimization of the back-gate effect on lateral high-voltage
SOI devices, Stefan Schwantes, IEEE TED, vol. 52, no. 7, July 2005.
20

287. Advantages of the graded-channel SOI FD MOSFET for application as a

quasi-linear resistor, Antonio Cerdeira, IEEE TED, vol. 52, no. 5, May
2005.
288. Quantum-Based Simulation Analysis of Scaling in Ultrathin Body Device
Structures, Arvind Kumar, IEEE TED, vol. 52, no. 4, April 2005.
289. Implementation of ESD Protection in SOI Technology: A Simulation
Study, V. Axelrad, SISPAD 2005.
290. An Accurate Separation of Floating-Body and Self-Heating Effects for
High-Frequency Characterization of SOI MOSFETs, Noriyuki Miura, SISPAD 2005.
291. Threshold Voltage Model of Single Gate SOI MOSFETs Derived from
Asymptotic Method, Junichi Aoyama, SISPAD 2005.
292. Simulation Analysis of Series Resistance for SOI MOSFET in Nanometer
Regime, Xinlin Wang, SISPAD 2005.
293. High performance 65 nm SOI technology with enhanced transistor strain
and advanced-low-K BEOL, W-H. Lee, IEDM 2005.
294. Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain
regions for performance enhancement, Kah-Wee Ang, IEDM 2005.
295. Selective Epitaxial Channel Ground Plane Thin SOI CMOS Devices, Zhibin
Ren, IEDM 2005.
296. On the scalability of source/drain current enhancement in thin film sSOI,
E. Augendre, ESSDERC 2005.
297. Using direct-tunneling mechanism to suppress hysteresis effect in floatingbody partially depleted SOI devices, Shiao-Shien Chen, IEEE EDL, vol.
25, no. 5, May 2004.
298. Self-Align Recessed Source Drain Ultrathin Body SOI MOSFET, Zhikuan
Zhang, IEEE EDL, vol. 25, no. 11, November 2004.
299. Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping
technique, Won-Ju Cho, IEEE EDL, vol. 25, no. 6, June 2004.
300. Fully depleted n-MOSFETs on supercritical thickness strained SOI, Isaac
Lauer, IEEE EDL, vol. 25, no. 2, February 2004.
301. AC behavior of gate-induced floating body effects in ultrathin oxide PD
SOI MOSFETs, Dimitri Lederer, IEEE EDL, vol. 25, no. 2, February
2004.
302. Modeling of thermal behavior in SOI structures, Feixia Yu, IEEE TED,
vol. 51, no. 1, January 2004.
21

303. On the modeling of surface roughness limited mobility in SOI MOSFETs

and its correlation to the transistor effective field, David Esseni, IEEE
TED, vol. 51, no. 3, March 2004.
304. Device design for subthreshold slope and threshold voltage control in sub100-nm fully depleted SOI MOSFETs, Toshinori Numata, IEEE TED,
vol. 51, no. 12, December 2004.
305. Critical discussion of the front-back gate coupling effect on the low-frequency
noise in fully depleted SOI MOSFETs, Eddy Simoen, IEEE TED, vol. 51,
no. 6, June 2004.
306. Thin-film strained-SOI CMOS Devices-physical mechanisms for reduction
of carrier mobility, Tomohisa Mizuno, IEEE TED, vol. 51, no. 7, July
2004.
307. Engineering S/D diffusion for sub-100-nm channel SOI MOSFETs, Akihiro Kawamoto, IEEE TED, vol. 51, no. 6, June 2004.
308. Partially depleted SOI MOSFETs under uniaxial tensile strain, Wei Zhao,
IEEE TED, vol. 51, no. 3, March 2004.
309. Impact of downscaling on high-frequency noise performance of bulk and
SOI MOSFETs, Guillaume Pailloncy, IEEE TED, vol. 51, no. 10, October
2004.
310. Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs, Ken Uchida, IEDM 2004.
311. Performance enhancement of partially- and fully-depleted strained-SOI
MOSFETs and characterization of strained-Si device parameters, Toshinori Numata, IEDM 2004.
312. Analysis of the back gate effect on the breakdown behaviour of SOI LDMOS transistors, Stefan Schwantes, ESSDERC 2004.
313. Thermal scaling of ultra-thin SOI: reduced resistance at low temperature
RTA, Jong-Heon Yang, ESSDERC 2004.
314. Off current adjustment in ultra-thin SOI MOSFETs, J. Hartwich, ESSDERC 2004.
315. Self-aligned recessed source/drain ultra-thin body SOI MOSFET technology, Zhikuan Zhang, ESSDERC 2004.
316. Comparative analysis of basic transport properties in the inversion layer
of bulk and SOI MOSFETs: a Monte-Carlo study, Luca Lucci, ESSDERC
2004.
317. On the body-source built-in potential lowering of SOI MOSFETs, Pin Su,
IEEE EDL, vol. 24, no. 2, February 2003.
22

110 strained-SOI n-MOSFETs with higher electron mobility, T. Mizuno, IEEE

EDL, vol. 24, no. 4, April 2003.
318. Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs,
J. P. Colinge, IEEE EDL, vol. 24, no. 8, August 2003.
319. Inversion-layer induced body current in SOI MOSFETs with body contacts, Hongchin Lin, IEEE EDL, vol. 24, no. 2, February 2003.
320. On the body-source built-in potential lowering of SOI MOSFETs, Pin Su,
IEEE EDL, vol. 24, no. 2, February 2003.
321. Short-channel single-gate SOI MOSFET model, Kunihiro Suzuki, IEEE
TED, vol. 50, no. 5, May 2003.
322. Design guideline for minimum channel length in silicon-on-insulator (SOI)
MOSFET, Akihiro Kawamoto, IEEE TED, vol. 50, no. 11, November
2003.
323. Scaling fully depleted SOI CMOS, Vishal P. Trivedi, IEEE TED, vol. 50,
no. 10, October 2003.
324. Modeling the fringing electric field effect on the threshold voltage of FD
SOI nMOS devices with the LDD/sidewall oxide spacer structure, S. C.
Lin, IEEE TED, vol. 50, no. 12, December 2003.
325. Experimental study on carrier transport mechanism in ultrathin-body SOI
MOSFETs, Ken Uchida, SISPAD 2003.
326. Mobility in UTB-SOI PFETS: local coordinate-based modeling with the
density gradient method, Daniel Connelly, SISPAD 2003.
327. Atomistic tight-binding calculations for the investigation of transport in
extremely scaled SOI transistors, M. Stadele, IEDM 2003.
328. Locally strained ultra-thin channel 25nm narrow FDSOI devices with
metal gate and mesa isolation, Z. Krivokapic, IEDM 2003.
329. A 65nm node strained SOI technology with slim spacer, Fu-Liang Yang,
IEDM 2003.
330. Device design considerations for ultra-thin SOI MOSFETs, B. Dons, IEDM
2003.
331. High performance CMOS devices on SOI for 90 nm technology enhanced
by RSD (raised source/drain) and thermal cycle/spacer engineering, H.
Park, IEDM 2003.
332. Mixed-signal performance of sub-100nm fully-depleted SOI devices with
metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions, A. Vandooren, IEDM 2003.
23

333. Interface coupling and film thickness measurement on thin oxide thin film
fully depleted SOI MOSFETs, M. Casse, ESSDERC 2003.
334. Carrier quantization in SOI MOSFETs using an effective potential based
Monte-Carlo tool, P. Palestri, ESSDERC 2003.
335. 45nm gate length Bulk/PD-SOI CMOS transistors with low gate leakage
current for high speed and low power applications, C. K. Yang, ESSDERC
2003.
336. Drain leakage mechanisms in fully depleted SOI devices with undoped
channel, R.J. Luyken, ESSDERC 2003.
337. Comparison between bulk and SOI MOSFETs for sub-100nm mixed mode
applications, Sushant S. Suryagandh, ESSDERC 2003.
338. Temperature dependence of hot-carrier-induced degradation in 0.1 m SOI
nMOSFETs with thin oxide, Wen-Kuan Yeh, IEEE EDL, vol. 23, no. 7,
July 2002.
339. Hot carrier-induced SOI MOSFET degradation under AC stress conditions, Jae-Ki Lee, IEEE EDL, vol. 23, no. 3, March 2002.
340. Enhanced Substrate Current in SOI MOSFETs, Pin Su, IEEE EDL, vol.
23, no. 5, May 2002.
341. On the high-temperature subthreshold slope of thin-film SOI MOSFETs,
T. Rudenko, IEEE EDL, vol. 23, no. 3, March 2002.
342. Principles of transient charge pumping on partially depleted SOI MOSFETs, S. Okhonin, IEEE EDL, vol. 23, no. 5, May 2002.
343. An experimental study on transport issues and electrostatics of ultrathin
body SOI pMOSFETs, Zhibin Ren, IEEE EDL, vol. 23, no. 10, October
2002.
344. Gate-induced floating body effect excess noise in partially depleted SOI
MOSFETs, Francois Dieudonne, IEEE EDL, vol. 23, no. 12, December
2002.
345. Reduced floating body effects in narrow channel SOI MOSFETs, J. Pretet,
IEEE EDL, vol. 23, no. 1, January 2002.
346. Measurement of the effect of self-heating in strained-silicon MOSFETs, K.
A. Jenkins, IEEE EDL, vol. 23, no. 6, June 2002.
347. A method to extract mobility degradation and total series resistance of
fully-depleted SOI MOSFETs, Francisco J. Garcia Sanchez, IEEE TED,
vol. 49, no. 1, January 2002.

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348. Electron and hole mobility enhancement in strained SOI by wafer bonding,
Lijuan Huang, IEEE TED, vol. 49, no. 9, September 2002.
349. On the performance advantage of PD/SOI CMOS with floating bodies,
Mario M. Pelella, IEEE TED, vol. 49, no. 1, January 2002.
350. Influences of buried-oxide interface on inversion-layer mobility in ultrathin SOI MOSFETs, Junji Koga, IEEE TED, vol. 49, no. 6, June 2002.
351. Off-leakage and drive current characteristics of sub-100-nm SOI MOSFETs and impact of quantum tunnel current, Hidehiko Nakajima, IEEE
TED, vol. 49, no. 10, October 2002.
352. Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 m
CMOSFET with 2-nm thin gate oxide, Wen-Kuan Yeh, IEEE TED, vol.
49, no. 12, December 2002.
353. Clarification of floating-body effects on drive current and short channel
effect in deep sub-0.25 m partially depleted SOI MOSFETs, Takuji Matsumoto, IEEE TED, vol. 49, no. 1, January 2002.
354. Quantum simulations of an ultrashort channel single-gated n-MOSFET
on SOI, J. Knoch, IEEE TED, vol. 49, no. 7, July 2002.
355. Fully-depleted SOI CMOSFETs with the fully-silicided source/drain structure, Takashi Ichimor, IEEE TED, vol. 49, no. 12, December 2002.
356. Closed-form analytical drain current model considering energy transport
and self-heating for short-channel fully-depleted SOI NMOS devices with
lightly-doped drain structure biased in strong inversion, Shih-Chia Lin,
IEEE TED, vol. 49, no. 12, December 2002.
357. Technology modeling for emerging SOI devices, Meikei Ieong, SISPAD
2002.
358. Design for scaled thin film strained-SOI CMOS devices with higher carrier
mobility, T. Mizuno, IEDM 2002.
359. Experimental Study on Carrier Transport Mechanism in Ultrathin-body
SOI n- and p-MOSFETs with SOI Thickness less than 5 nm, Ken Uchida,
IEDM 2002.
360. Examination of hole mobility in ultra-thin body SOI MOSFETs, Zhibin
Ren, IEDM 2002.
361. Substrate Effects on the Small-Signal Characteristics of SOI MOSFETs,
V. Kilchytska, ESSDERC 2002.
362. New Mechanism of Body Charging in Partially Depleted SOI-MOSFETs
with Ultra-thin Gate Oxides, J. Pretet, ESSDERC 2002.

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363. Temperature dependency of 0.1 m partially depleted SOI CMOSFET,

Wen-Kuan Yeh, IEEE EDL, vol. 22, no. 7, July 2001.
364. Back gate effects on threshold voltage sensitivity to SOI thickness in fullydepleted SOI MOSFETs, Mitsuhiro Noguchi, IEEE EDL, vol. 22, no. 1,
January 2001.
365. A study of the threshold voltage variation for ultra-small bulk and SOI
CMOS, Kiyoshi Takeuchi, IEEE TED, vol. 48, no. 9, September 2001.
366. Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application, David
Esseni, IEEE TED, vol. 48, no. 12, December 2001.
367. Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET, Zhi-Yuan Cheng, IEEE TED, vol. 48, no. 2, February 2001.
368. Highly stable SOI technology to suppress floating body effect for high
performance CMOS device, Hee Sung Kang, IEDM 2001.
369. Gate length scaling accelerated to 30 nm regime using ultra-thin film PDSOI technology, Samuel K. H. Fung, IEDM 2001.
370. Experimental evidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance, and threshold voltage of ultrathin body SOI
MOSFETs, Ken Uchida, IEDM 2001.
371. The Effect of Impact Ionization on the Subthreshold Leakage Current
in N-Channel Double-Gate SOI Transistors, Jae-Kwan Park, ESSDERC
2001.
372. Effect of starting SOI material quality on low-frequency noise characteristics in partially depleted floating-body SOI MOSFETs, Takeo Ushiki,
IEEE EDL, vol. 21, no. 12, December 2000.
373. Reduced reverse narrow channel effect in thin SOI nMOSFETs, Chun-Yen
Chang, IEEE EDL, vol. 21, no. 9, September 2000.
374. Deep submicrometer SOI MOSFET drain current model including series
resistance, self-heating and velocity overshoot effects, J. B. Roldan, IEEE
EDL, vol. 21, no. 5, May 2000.
375. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era, Yang-Kyu
Choi, IEEE EDL, vol. 21, no. 5, May 2000.
376. High-frequency characterization of sub-0.25-m fully depleted silicon-oninsulator MOSFETs, C. L. Chen, IEEE EDL, vol. 21, no. 10, October
2000.
377. Highly suppressed short-channel effects in ultrathin SOI n-MOSFETs, Eiichi Suzuki, IEEE TED, vol. 47, no. 2, February 2000.
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378. Hot-carrier degradation behavior of thin-film SOI nMOSFET with isolation scheme and buried oxide thickness, Jong-Wook Lee, IEEE TED, vol.
47, no. 5, May 2000.
379. A steady state drain current technique for generation and recombination
lifetime measurement in the SOI MOSFET, Zhi-Yuan Cheng, IEEE TED,
vol. 47, no. 1, January 2000.
380. Light Dependence of SOI MOSFET with Nonuniform Doping Profile,
George K. Abraham, IEEE TED, vol. 47, no. 7, July 2000.
381. Reliability issues for silicon-on-insulator, R. Bolam, IEDM 2000.
382. Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements
and implications on the performance of ultra-short MOSFETs, D.Esseni,
IEDM 2000.
383. A novel SiGe-inserted SOI structure for high performance PDSOI CMOSFETs, G. J. Bae, IEDM 2000.

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