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TDS I: Lecture 1
Todays Lecture
Logistics
Course Outline
Introduction
TDS I: Lecture 1
Logistics
Lecture:
TDS I: Lecture 1
Logistics (cont)
Requirements
Logic Design
Computer Architecture
TDS I: Lecture 1
Reference Books
Textbook
Recommended
TDS I: Lecture 1
Course Outline
Basics
Test generation methods
Design for Testability (DFT)
I try to be flexible. The order and contents may be changed
as we proceed.
TDS I: Lecture 1
Outline: Basics
Introduction
Failures and errors
Fault models
Functional vs Structural testing
TDS I: Lecture 1
TDS I: Lecture 1
TDS I: Lecture 1
Introduction
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Definitions
Design synthesis:
Verification:
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Design Steps
High-level
High
level
Description
Specifications
Behavioral
VHDL, C
Functional
Description
Structural
VHDL
Figs. [Sherwani]
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Specifications
Physical
Design
Placed
& Routed
Design
Packaging
Functional
Description
Synthesis
Technology
Mapping
Gate-level
Gate
level
Design
Fabrication
Logic
Description
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
TDS I: Lecture 1
Figs. [Sherwani]
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Testing
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Testing (cont)
Process yield, Y,
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Statistically estimated
Not feasible to thoroughly test all parts
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Testing Process
Components, Raw Materials
Manufacturing
Process
Yield
Testing
Fraction of
good parts
20%-90%
Shipped
Parts
Quality: DPM
Defective Parts
per Million
50-500 DPM
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Mostly
good
chips
Fabricated
chips
Defective chips
Prob(bad) = 1- y
Mostly
bad
chips
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Transient Disturbance
Power or Temperature Specification Violated
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Specification
Verification Technique
Synthesis
Matching of Two Design Paths
Simulation Emulation
Formal Verification
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Verifies correctness of
design.
Performed by
simulation, hardware
emulation, or formal
methods.
Performed once prior to
manufacturing.
Responsible for quality
of design.
Verifies correctness of
manufactured hardware.
Two-part process:
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11
Definition
Problems
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Real Tests
The fraction (or percentage) of such chips is called the yield loss.
The fraction (or percentage) of bad chips among all passing chips is
called the defect level.
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Costs of Testing
Manufacturing test
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13
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
Digital ASIC test time: 6 seconds or 27 cents
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Roles of Testing
Detection:
Determination whether or not the device under test (DUT) has
some fault.
Diagnosis:
Identification of a specific fault that is present on DUT.
Device characterization:
Determination and correction of errors in design and/or test
procedure.
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Test automation
Testable designs
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