A Single-supply

True Voltage
Level Shifter
Rajesh Garg
Gagandeep Mallarapu
Sunil P. Khatri

Department of Electrical and Computer

Engineering,
Texas A&M University,
College Station, TX
1

Outline

Introduction

Previous Work

Our Approach

Experimental Results

Conclusions
2

Introduction

System-on-chip and multi-core computing

architectures
Increasingly used for many applications
Employ voltage scaling to meet power and
energy requirements
Contain many voltage domains operating at
different supply voltage levels

Different voltage domains communicate

with each other

Efficient voltage level shifters (VLS) are

required to interface these voltage domains

Should be fast, and also consume low power

(leakage and dynamic)
3

Introduction

Input (VDDI) and output (VDDO) domains

When VDDI > VDDO, an inverter can be used

When VDDI < VDDO, special VLS required.

DVS is employed to further reduce power

consumption

In case an inverter is used, leakage may be too high.

Conventional VLS need two supply voltages
Need to route VDDI supply voltage along with signal wire
Supply wires are typically very wide
May result in routing congestion and excessive area utilization

At different times, VDDI can be greater than or less than

VDDO
Conventional VLSs need supply voltages of all input
signals from different domains
Further increase area utilization and make routing more
complex

We would like to address both the above

issues. In
4
other words

Introduction

Need single supply VLSs

Need true VLSs

Perform voltage level conversions using only VDDO

supply voltage
This will ease placement and as well as routing
constraints
The same VLS should handle the cases when VDDI <
VDDO and VDDI > VDDO

Our VLS presented is this talk meets these

requirements
No prior approach exist which can perform
both low-to-high and high-to-low voltage level
conversion using a single supply voltage
5

Previous Work

Several previous approaches utilize dual supply

voltage
[ Wang et al. 2001, Tan et al. 2002]

Puri et al. 2003 proposed single supply VLS to

convert low level to high voltage level

Focused on minimizing power and energy consumption

Utilize both VDDI and VDDO supply voltages

Limited range of operation due to the usage of diodeconnected NMOS device to generate lower supply voltage
Leakage currents are higher when VDDO greater than
VDDI + VT

Khan et al. 2006 addressed the issue of voltage

range

Can perform only low to high voltage level conversion

6
Higher leakage currents

Our Single Supply-True

VLS

Convert signal level from VDDI domain to

VDDO domain

VDDI
Domain

Using only VDDO supply

VDDI
Works for VDDI < VDDO as well as VDDI > VDDO
in

GND
VDDO

node1

GND
VDDO

node2

GND
VDDO

outb
ctrl

GND

Vctrl

VTM 2

Our Single Supply-True

VLS
Maximum voltage
at ctrl node

Vctrl

When VDDI < VDDO

min(VDDI , VDDO VTM 8 )

VDDI
Domain

When VDDI > VDDO

Vctrl min(VDDO,VDDI VTM 7 )

This means that when

in = VDDI (and node2 =
VDDO), M1 never turns
on, for both VDDI >
VDDO and VDDI < VDDO
Low VT
device
All devices were sized
to reduce leakage currents

To minimize
leakage current,
use high VT devices

Speed and leakage power tradeoff

8
All transistors except M4, M6 and M8
are

Experimental Results

Implemented our SS-TVLS in PTM 90nm

Compared with a combination of
Inverter and VLS of Khan et al.
(Combined VLS)
Inverter is used when VDDI > VDDO
VLS of Khan et al. when VDDI < VDDO
Requires control signal
to indicate whether
VDDI < VDDO or
VDDI > VDDO

Experimental Results

Low-to-high conversion VDDI = 0.8V and

Performance
Parameter
Our SS-TVLS
Combined VLS
Ratio
VDDO
= 1.2V
Delay Rise (ps)

22

122.6

5.6

Delay Fall (ps)

33.3

50.5

1.5

Power Rise (W)

27.6

71.87

2.6

Power Fall (W)

33.8

119.27

3.5

Leakage Current High (nA)

20.8

157.2

7.6

Leakage Current Low (nA)

3.6

71.1

19.8

Performance Parameter
Our SS-TVLS
Combined VLS
High-to-Low
conversion
VDDI
= 1.2VRatio
and
34.9
46.5
1.3
Delay Rise (ps)
VDDO
= 0.8V
15.7
35.2
2.2
Delay Fall (ps)
Power Rise (W)

27.3

20.7

0.8

Power Fall (W)

59.3

56.8

1.0

Leakage Current High (nA)

7.3

32.5

4.5

Leakage Current Low (nA)

3.9

36.3

10

9.3

Experimental Results

Performed Monte Carlo simulations for

process and temperature variations

3 = 10% for W, L and VT and for T = 27o, 60o and 90o C

Our SS-TVLS performs correctly in all Monte Carlo
simulations
VDDI = 0.8V and VDDO = 1.2V

VDDI = 1.2V and VDDO = 0.8V

Performance Parameter

T = 27oC

Our SS-TVLS

Combined VLS

Our SS-TVLS

Combined VLS

Delay Rise (ps)

22.08

1.1

129.4

27.4

35.1

2.4

52

3.9

Delay Fall (ps)

33.2

1.9

50.4

15.6

0.8

34.8

1.3

Power Rise (W)

27.7

0.8

78.9

7.3

27.5

1.3

22.5

1.1

Power Fall (W)

33.8

0.4

114.2

7.2

59.5

0.6

52.5

0.1

Leakage Current High (nA)

31.5

13.7

218.8

158.6

8.6

41.4

14.1

3.8
102.9
75.41
1.3
o C as9.0
Similar results
are3.8obtained
for
T = 3.6
60 o and
9032.3
11
well

Leakage
Current Low (nA)

Experimental Results

Voltage translation range

Varied VDDI and VDDO from 0.8V to 1.4V in steps of

5mV
Our SS-TVLS performed efficiently for all VDDI and
VDDO
combinations
Rising
Falling
Delay

Delay

Performed layout of our SS-TVLS

Area is 4.47m2 ( Width = 0.837m and height = 5.355m)

12

Conclusions

Our single supply-true voltage level shifter can

interface different voltage domains

The delay of our SS-TVLS is much lower than

combined VLS

5.5x (1.3x) lower for a rising output when VDDI<

VDDO (VDDI > VDDO)
1.5x (2.2x) lower for a falling output when VDDI<
VDDO (VDDI > VDDO)

The leakage currents are also substantially

lower for our SS-TVLS compared to the
combined VLS

Convert any voltage level to any other desired

voltage level by using only VDDO supply voltage

7.5x (4.4x) lower for a high output and 19.5x (9.3x)

lower for a low output when VDDI< VDDO (VDDI >
VDDO)

Our SS-TVLS is also more robust to process

and
13
temperature variations

THANK YOU!

14