ModelSim Altera 6.

5d

TOOL MANUAL

Compiled By

Dr.K.Sivasankaran,
Associate Professor,
School of Electronics Engineering,
VIT University
Vellore-632014

FPGA BASED SYSTEM DESIGN

ModelSim Tutorial
This is a brief tutorial on how to run the ModelSim VerilogHDL editor and the ModelSim
waveform generator.

Step:1 Invoking the Tool

Go to start up and choose ModelSim Altera 6.5d (Quartus II 9.1) Starter Edition.
The following window will be opened.

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Tool Manual

FPGA BASED SYSTEM DESIGN

Step: 2 Creating a Project and VerilogHDL Design

File
Click on "File" -> New and then " Project"

Create a folder in the "Project Location: part as shown below

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Tool Manual

FPGA BASED SYSTEM DESIGN

Then enter a project name and Click OK

The new pop-window will open as shown below and click Yes to create new project directory.

Select Create a New File from the pop-up menu.

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Tool Manual

FPGA BASED SYSTEM DESIGN

In the following pop-up window type the filename andgate and choose the Add file as type
Verilog

Type the file name for example andgate and select the file type as VerilogHDL. This will
create a file name andgate.v which is visible in the work space window as shown below. Now by
right click on project work space choose Add to project -> NewFile

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Tool Manual

FPGA BASED SYSTEM DESIGN

Now a pop-up window as shown below will appear

In the following pop-up window type the filename and_tst and choose the Add file as type
Verilog

This will create a file name and_tst.v which is visible in the work space window as shown below.
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Tool Manual

FPGA BASED SYSTEM DESIGN

Step:3 Editing VerilogHDL

Now, double click on the link andgate.v in the work space window to invoke the VerilogHDL
editor that you can type in your program. Enter in the VerilogHDL code for and gate.

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Tool Manual

FPGA BASED SYSTEM DESIGN

Now, double click on the link and_tst.v in the work space window to invoke the VerilogHDL
editor that you can type in your program. . Enter in the VerilogHDL code for and gate using
test bench.

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Tool Manual

FPGA BASED SYSTEM DESIGN

After editing the code, save the file (Ctrl+S)

Step: 4 Compilation
Click on Compile in the Tool bar and select Compile All. The message appearing should say
# Compile of andgate.v was successful.
# Compile of and_tst.v was successful.
# 2 compiles, 0 failed with no errors.

Step:5 Simulation
To start the simulation click on the Simulation menu from the Tool bar and select Start
Simulation. You will get the following pop-up window, choose the module name of your test
bench code under the work library, in this case and_tst and click OK.

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The next window should appear

The Objects window will display the signals available from this signals can be added to the
waveform
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To add a signal, select the signal, right click on the signal "Add-> To Wave" then " Signals in
Design"

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The Wave window will be where your data will output to

Step 6: Analyzing Output

By clicking the Run icon
output as shown below

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(next to 100ps refer fig. below) continuously we can visualize the

Tool Manual