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ISRN KTH/EKT/FR-2001/2-SE

DC Parameter Extraction and Modeling of


Bipolar Transistors
Martin Linder

KTH, Royal Institute of Technology


Department of Microelectronics and Information Technology
Device Technology Laboratory
Stockholm 2001

DC Parameter Extraction and Modeling of


Bipolar Transistors
Martin Linder

KTH, Royal Institute of Technology


Department of Microelectronics and Information Technology
Device Technology Laboratory
Stockholm 2001

DC Parameter Extraction and Modeling of Bipolar Transistors

A dissertation submitted to Kungliga Tekniska Hgskolan, Stockholm, Sweden,


in partial fulfillment of the requirements for the degree of Teknisk Doktor.

2001 Martin Linder


KTH, Royal Institute of Technology
Department of Microelectronics and Information Technology
Electrum 229
S-164 40 Kista
SWEDEN

ISRN KTH/EKT/FR-2001/2-SE
ISSN 0284-0545
TRITA - EKT
Forskningsrapport 2001:2

Printed in 250 copies by Kista Snabbtryck AB, Kista 2001.

Linder, Martin: DC Parameter Extraction and Modeling of Bipolar Transistors,


ISRN KTH/EKT/FR-2001/2-SE,
KTH, Royal Institute of Technology, Department of Microelectronics and
Information Technology, Stockholm 2001.

Abstract
This thesis deals with DC parameter extraction and modeling of bipolar
transistors (BJTs). Parameter extraction is performed using the dual base terminal BJT
test structure. Extraction procedures for compact model parameters such as the emitter
resistance RE and the intrinsic and the extrinsic base resistance (RBInt and RBExt
respectively) are presented. The dual base terminal test structure is also utilized for
DC extraction of the bias dependent Early voltages VEF and VER. From the extracted
Early voltage parameters, it is shown that the built-in potential of the base-emitter and
the base-collector junctions together with the grading coefficients of the junctions can
be extracted from DC measurements. Normally, extraction of these parameters
requires capacitance-voltage measurements. Further on, extraction of the zero bias
intrinsic base sheet resistance RS00 is demonstrated by considering the Early effect.
The concept of the dual base terminal test structure is also applied to the collector
region and a new type of test structure is proposed. The test structure uses two
terminals for the base and two terminals for the collector. It is shown that using the
new test structure, it is possible to directly measure the constant part of the collector
resistance RCC and to monitor the onset of the base push-out effect (Kirk effect).
Finally, a general model formulation for the distributed nature of the base-emitter
junction is presented. The proposed model includes both the Early effect and the
effect of charge storage in the base. Therefore, accurate calculation of the base
resistance and the potential, current and base charge distribution along the intrinsic
base region is enabled.

Keywords: bipolar transistors, parameter extraction, test structure, modeling,


distributed model, base resistance, emitter resistance, collector resistance, Early
effect, base push-out, current crowding, base conductivity modulation.

Acknowledgements
First of all I would like to thank Prof. Mikael stling for giving me the
opportunity to pursue my Ph.D. degree at the department. He is always encouraging
and optimistic. I have had a good time working with you. I am also grateful to Dr. Jan
V. Grahn who, with his excellent lecturing, got me interested in the subject. Dr. Jan
V. Grahn also supervised my Master of Science thesis and I am glad that it worked
out so well that he offered me a Ph.D. student position in the bipolar group, regardless
of my background in material physics. One of the strongest impressions from the
beginning of my studies was the time when Dr. Shili Zhang and myself sat down to
design test structures to be manufactured in our in - house process BIP#2. I remember
we thought something may come out of it but I could never imagine that it would
turnout to be so rewarding. Maybe he did. During the years we have had many
discussions around device physics and mathematics. In short, he taught me a lot,
thanks.
During my second year I attended a summer school in France called MIGAS.
There I met Prof. Kjell Jeppson and Fredrik Ingvarson. We started a discussion
regarding the extraction of parasitic resistances. It turned into a long and fruitful
collaboration. Without them, I am sure that the scope of this thesis would have been
totally different. Many thanks to both of you!
Dr. Ping-Xi Ma, who spent a post doc year in our group, is acknowledged for
encouraging discussions and that he always was there to help out. Of course, the rest
of the Bipolar group are acknowledged: Martin Sandn (many thanks for Fig. 1 in
Paper 2, Fig. 3 in Paper 3 and Fig. 1 in Paper 4), Johan Pejnefors, Gunnar Malm,
Dr. Wlodek Kaplan, Erdal Suvar and Dr. Tord Karlin. It has been stimulating and fun
working with you. I think all the people that work within the EKT and FTE
departments deserve my sincere gratitude. It has been five very stimulating years,
thank you all!
Finally, I would also like to take the opportunity to thank my family for
encouraging me to pursue the Ph.D. degree. Most of all, I would like to thank my
fiance Jessica and our daughter Cajsa. Their inspiration, patience and support have
been invaluable during my time as a Ph.D. Student.
Martin Linder, Kista 2001

Appended Papers
1.

M. Linder, B. G. Malm, P. Ma, J. V. Grahn, S.-L. Zhang and M. stling, The


Effect of Emitter Overetch and Base Implantation Tilt on the Performance of
Double Polysilicon Bipolar Transistors, Physica Scripta, T79, p.246-249, 1999.

2.

M. Linder, F. Ingvarson, K.O. Jeppson, J.V. Grahn, S.-L. Zhang and M.stling,
Extraction of Emitter and Base Series Resistances of Bipolar Transistors from
a Single DC Measurement, IEEE Trans. Semicond. Manufact., 13, p.119-126,
2000.

3.

M. Linder, F. Ingvarson, K.O. Jeppson, J.V. Grahn, S.-L. Zhang and M.stling,
On DC Modeling of the Base Resistance in Bipolar Transistors, Solid-State
Electronics, 44, p.1411-1418, 2000.

4.

F. Ingvarson, M. Linder, K.O. Jeppson, S.-L. Zhang and M.stling, Extraction


of the Intrinsic Base Region Sheet Resistance in Bipolar Transistors, In Proc.
Bipolar and BiCMOS Tech. Meeting, p.184-186, 2000.

5.

M. Linder, F. Ingvarson, K.O. Jeppson, S.-L. Zhang, J.V. Grahn and M.


stling., A New Test Structure for Parasitic Resistance Extraction of Bipolar
Transistors, In Proc. IEEE Int. Conf. Microelectronic Test Structures, p.25-30,
2001.

6.

F. Ingvarson, M. Linder, K.O. Jeppson, S.-L. Zhang, J.V. Grahn and M. stling,
A Procedure for Characterizing the BJT Base Resistance and Early Voltages
Utilizing a Dual Base Transistor Test Structure, In Proc. IEEE Int. Conf.
Microelectronic Test Structures, p.31-36, 2001.

7.

M. Linder and F. Ingvarson, A Distributed Model of the Base-Emitter Junction


in Bipolar Transistors Including the Early Effect, In manuscript.

Related Papers Not Included in the Thesis


8.

M. Linder, M. Sandn, J. Pejnefors, P. Ma, T. E. Karlin, W. Kaplan, J. V.


Grahn, S.-L. Zhang and M. stling, Extraction of Parasitic Resistances for
Silicon High Frequency Bipolar Transistors, In Proc. 1997 Gigahertz Meeting,
Oct 1997.

9.

M. Sandn, T. E. Karlin, J. Pejnefors, M. Linder, W. Kaplan, J. V. Grahn, S.-L.


Zhang and M. stling, Enhanced High Frequency Performance of IDP-Emitter
Bipolar Junction Transistors by Hydrogen Passivation, In Proc. 1997
Gigahertz Meeting, Oct 1997.

10.

J. V. Grahn, M. Linder and E. Fredriksson, In Situ Growth of Evaporated TiO2


Thin Films using Oxygen Radicals: Effect of Deposition Temperature, Journal
of Vac. Sc. and Tech., 16, p.2495-2500, 1998.

11.

W. Kaplan, J. Pejnefors, M. Linder, M. Sandn, T. E. Karlin, B. G. Malm, S.-L.


Zhang, J. V. Grahn and M. stling, A Simplified High-Speed Bipolar Process
with Ti Salicide Metallization: Implementation of In Situ p-Doped Polysilicon
Emitter, Physica Scripta, T79, p.318-321, 1999.

12.

B. G. Malm, O. Tornblad, M. Linder and M. stling, Modelling of Highly


Doped Launcher Layer in SiGe Heterojunction Bipolar Transistors, In Proc.
RadioVetenskap och Kommunikation, 1999.

13.

J. V. Grahn, B. G. Malm, B. Mohadjeri, J. Pejnefors, M. Sandn, Y. B. Wang,


H. H. Radamson, P. Jnsson, M. Jargelius, H. Fosshaug, M. Linder, G.
Landgren and M. stling, A High Speed SiGe HBT Process using
Non-Selective Epitaxy and In Situ Phosphorus Doped Emitter, In Proc.
European Solid-St. Dev. Research Conf., p.728-731, 1999.

14.

M. Linder, F. Ingvarson, K.O. Jeppson, J.V. Grahn, S.-L. Zhang and M.stling,
A New Procedure for Extraction of Series Resistances for Bipolar Transistors
from DC Measurements, In Proc. IEEE Int. Conf. Microelectronic Test
Structures, p.147-151, 1999.

15.

J. V. Grahn, H. Fosshaug, M. Jargelius, P. Jnsson, M. Linder, B. G. Malm, B.


Mohadjeri, J. Pejnefors, H. H. Radamson, M. Sandn, Y. B. Wang, G. Landgren
and M. stling, A Low-Complexity 62-GHz fT SiGe Heterojunction Bipolar
Transistor Process using Differential Epitaxy and In Situ Phosphorus-Doped
Poly-Si Emitter at Very Low Thermal Budget, Solid-State Electronics, 44,
p.549-554, 2000.

16.

J. V. Grahn, B. G. Malm, B. Mohadjeri, J. Pejnefors, M. Sandn, Y.-B. Wang,


H. H. Radamson, P. Jnsson, M. Jargelius, H. Fosshaug, M. Linder, G.
Landgren and M. stling, "A 62-Ghz fT SiGe HBT Process," In Proc. 5th
Symposium on Gigahertz Electronics, p.11-14, 2000.

17.

P. Ma, M. Linder, M. Sandn, S.-L. Zhang and M. stling, An Analytical


Model for Space-Charge Region Capacitance Based on Practical Doping
Profiles under Any Bias Conditions, Solid-State Electronics, 45, p.159-167,
2001.

18.

M. Linder, P. Ma, M. Sandn, S.-L. Zhang and M. stling, Extraction and


Modeling of the Planar and Peripheral Parts of the BaseEmitter Capacitance,
In manuscript, 2001.

19.

F. Ingvarson and M. Linder, A Method for Extracting the Bias Dependent


Early Effect in Bipolar Transistors from DC Measurements, In manuscript,
2001.

Table of Contents

1. INTRODUCTION ...............................................................1
2. THE BIPOLAR TRANSISTOR .............................................3
2.1. Fabrication of BJTs .............................................................. 3
2.2. Bipolar Transistor Operation ................................................ 7
2.3. Compact BJT Modeling...................................................... 14

3. MODELING OF THE BASE RESISTANCE ...........................19


3.1. Basic Concepts .................................................................. 20
3.2. Distributed Transistor Modeling.......................................... 22
3.3. Compact Models of the Base Resistance .......................... 25
3.4. Small Signal Modeling of the Base Resistance .................. 26

4. DC EXTRACTION OF COMPACT MODEL PARAMETERS .....29


4.1. Intrinsic Parameters ........................................................... 30
4.2. Parasitic Resistances......................................................... 33
4.3. Dual Base Terminal Test Structure .................................... 38
4.4. Dual Collector Terminal Test Structure .............................. 39

5. CONCLUDING REMARKS ...............................................43


6. REFERENCES ...............................................................45
7. SUMMARY OF THE APPENDED PAPERS ...........................51

Chapter 1. Introduction

1. Introduction
The tremendous market growth for the electronic industry in the
past years is predicted to continue [1]. Even though most of the
microelectronic applications are digital systems manufactured in CMOS
technology (Complementary Metal-Oxide-Semiconductor), properties
such as low noise performance, high frequency operation and high
linearity renders state-of-the-art Si and SiGe bipolar transistors an
attractive technology choice for high frequency analog and high-speed
digital applications [2]. Typical circuit elements utilizing bipolar
transistors are Voltage Controlled Oscillators (VCOs), Low Noise
Amplifiers (LNAs) and mixers for high-speed circuit operation.
During the last decade, the market for wireless applications and
high-speed integrated digital circuits has switched from purely military
and space applications to the consumer market. The low cost issue has
therefore become more important and silicon technology is the most costeffective choice. However, the competition from CMOS and III-V
technologies necessitates a continuous development of Si and SiGe bipolar
transistor technologies. As the technology is improved and the device
dimensions are scaled down, improved accuracy of the compact modeling
of the device behavior is required by the circuit designers [3-7]. This
1

DC Parameter Extraction and Modeling of Bipolar Transistors

requirement comprises both more accurate compact models with a clear


coupling to the device physics and accurate determination of model
parameters. Further on, the increased complexity of the manufacturing
process inherently translates to increased production costs. Fast and simple
characterization techniques for automated wafer mapping are thus required
in order to enable yield control during manufacturing.
As the title suggests, this thesis deals with parameter extraction
and modeling of high performance bipolar transistors. In Chapter 2,
general aspects of bipolar transistor operation and compact modeling are
discussed. Models of the bias-dependent base resistance are reviewed in
Chapter 3, both regarding compact models and more complex model
formulations. Chapter 4 discusses parameter extraction for compact
bipolar transistor models, focusing on DC measurements. Finally, in
Chapter 5, concluding remarks are given together with suggestions for
future work.

Chapter 2. The Bipolar Transistor

2. The Bipolar Transistor


In this chapter, the different fabrication technologies of bipolar
junction transistors (BJTs) are explained with emphasis on the double
poly-Si technology. Second order effects that occur in the BJT, especially
at high current levels, are discussed. Finally, a brief presentation of the
different compact models of the BJT is given.

2.1. Fabrication of BJTs


Bipolar transistor process technologies are under constant
development. It can be noticed that the process schemes are not as unified
as for CMOS technology, where every company seems to follow the same
path of development. For bipolar transistors, a variety of different process
schemes exists, all showing both strengths and weaknesses.

Single Polysilicon Technology


The first technology reviewed here is the single polysilicon
process. One of the main advantages of this technology is the

DC Parameter Extraction and Modeling of Bipolar Transistors

a)
LOCOS
n+

n-

p+

n+

p+

b)
Intrinsic base implant
Resist
LOCOS
n+

n-

p+

n+

p+

c)
n+ poly-Si
LOCOS

p
n-

n+

n+

p+

d)
E
LOCOS
p+

C
B

B
p+

p+

n+

nn+

p+

Figure 1. Schematic process flow for a single poly-Si bipolar transistor.

straightforward implementation in a CMOS process. This so-called


BiCMOS process offers the advantages of having both bipolar,
NMOSFETs and PMOSFETs in the same process. The process flow of the
bipolar transistors is not very different from that of the MOSFET
transistors. A simplified process flow is described in Fig. 1.

Double Polysilicon Technology


The double poly-Si bipolar technology not only uses an n+ doped
poly-Si emitter but also allows the extrinsic base to be contacted with a p+
doped poly-Si layer. This feature enables full self-alignment of the active

Chapter 2. The Bipolar Transistor

a)
LOCOS
n-

p+

p+

n+
p

b)
n+ Collector plugg implant

Resist
LOCOS
n-

p+

p+

n+
p

c)
Intrinsic base implant
Si02
p+-poly-Si
LOCOS
+

p+ n

p+

n+

n+

p+

d)

E
B

p -poly-Si
LOCOS
p+

p+ n

p+

n+

n+

p+

Figure 2. Schematic process flow for a double poly-Si bipolar transistor.

layers of the transistor [8, 9]. A schematic process flow for a double polySi technology is shown in Fig. 2.
In order to minimize the fabrication time required to complete the
whole process, a simplified double poly-Si process was developed [10].
The process was simplified by omitting both trench isolation (as well as
junction isolation) and metallization. Consequently, the process is
completed using only four lithographic mask steps. The transistor is
electrically probed directly on the silicide that is formed on the emitter and
base poly-Si. However, the design of the intrinsic BJT is identical to the

DC Parameter Extraction and Modeling of Bipolar Transistors

full-scale process. As can be seen in Fig. 2(a), the first lithography step of
the process is the LOCOS mask, which defines the active areas and the
collector contacts. The second mask is the collector plug implantation
mask, Fig. 2(b). After deposition and boron implantation of the base polySi, an oxide is deposited which serves as an isolating layer between the
emitter and base poly-Si. Then the base poly-Si mask is exposed and both
the oxide layer and the base poly-Si layer are etched. Figure 2(c) shows
the structure after removal of the resist followed by a drive in anneal for
forming the extrinsic base regions. The intrinsic base is then implanted
through the emitter window. After spacer formation the emitter poly-Si is
deposited and implanted. The emitter poly-Si also serves as contact to the
collector window. The emitter poly-Si and the underlying oxide are then
etched after exposure and development of the last mask. Finally, the
uncovered areas of both the base and the emitter poly-Si are silicided.
The simplified process was used as a test vehicle for implementing
new process segments, e.g. in-situ phosphorous doped poly-Si
emitter [11]. Further on, the effect of the emitter window opening and the
intrinsic base implantation was investigated. As can be seen in Fig. 2, the
emitter window is opened by etching through the p+ poly-Si. Ideally, the
etching should stop at the interface between the p+ poly-Si and the n- epiSi. Since there is no possibility to detect this interface during etching, an
overetch is performed to guarantee that the n- epi-Si is reached. In addition
to this effect the intrinsic base implantation is usually tilted 5-7 in order
to avoid channeling of the implanted species. The relatively high sidewalls
of the emitter window can then shadow parts of the window from the
implantation. Together with the overetch, the shadowing may cause the
formation of a potential barrier between the extrinsic and the intrinsic base
at the shadowed side of the window. Naturally, this causes an increase in
the base resistance and consequently a decrease in the maximum
frequency of oscillation, fMAX. However, near the potential barrier between
the extrinsic and the intrinsic base regions, the intrinsic base will be
thinner than below the emitter. This raises the maximum cut-off frequency
fT,MAX since the base transit time is reduced. The effect of the overetch on

Chapter 2. The Bipolar Transistor

the high frequency performance and the breakdown characteristics of the


transistor is investigated in detail in Paper 1. In order to avoid the overetch
effects on the process stability, a thin oxide layer between the p+ poly-Si
and the n- epi-Si may be introduced [12]. This oxide is used as an etch stop
for the emitter window etch and the overetch is thus avoided. However,
formation of a low resistance base link between the extrinsic and the
intrinsic base regions becomes more elaborate.

2.2. Bipolar Transistor Operation


The BJT is essentially two pn diodes connected back to back, see
Fig. 3. From basic pn diode theory it is well known that the current
passing through the diode is given by:

VT

I = IS e
1

(1)

where V is the voltage over the diode, is the ideality factor,


VT (= kT/q 0.026 V) is the thermal voltage and IS is the saturation
current. Ideally, the base and collector currents should be similarly
dependent upon the applied voltages. However, in reality a large number
of effects occur which causes a deviation from the ideal theory. This is
clearly illustrated in Fig. 4, where the base and collector currents are
plotted versus the base-emitter voltage. The dotted lines are the ideal
behavior according to the simple theory and the solid lines represents a
real transistor.

DC Parameter Extraction and Modeling of Bipolar Transistors

E
n+
B

n-

n+

Figure 3. The one dimensional representation of the BJT, together with


the equivalent circuit of the ideal case.

The deviation of the measurements from the ideal behavior in the high
current regime, shown in Fig. 4, is due to various second order effects.
These second order effects will be described in the following paragraphs.

-2

Currents, IB and IC (A)

10

-3

10

-4

10

-5

10

-6

10

IC

-7

10

-8

IB

10

-9

10

-10

10

-11

10

-12

10

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Base - Emitter Voltage, VBE (V)


Figure 4. A typical Gummel plot for a BJT. The solid lines are real
transistor data and the dotted lines represent the ideal case.

Chapter 2. The Bipolar Transistor

The Early Effect


When changing the bias of the transistor, the width of the depletion
layers of the base-emitter and base-collector junctions will change. This
modulates the thickness of the quasi-neutral base region, and thus affects
the current transport of the transistor. This effect is called the Early effect
[13] or base width modulation and is observed as a non-zero output
conductance. Typical output characteristics are shown in Fig. 5. The
extrapolated intercept of the collector current IC data with the
collector-emitter voltage VCE axis is often referred to as the forward Early
voltage VAF. Similarly, in reverse mode of operation the intercept of the
emitter current IE(VEC) plot is called the reverse Early voltage (or Late
voltage) VAR. VAF is an important figure of merit for the BJT, and should
be as high as possible. A simple way to increase VAF is to increase the base
Gummel number, i.e. to increase the doping and/or the base width which
unfortunately reduces the DC current gain . Therefore, the VAF product
is often referred to, as a more relevant figure of merit for a bipolar
technology. The Early voltages are also important parameters for compact

Collector Current, IC (mA)

BJT models and will be discussed in more detail in Chapter 2.4.

0.7

0.5

IB = 5.0 A
IB = 4.0 A

0.4

IB = 3.0 A

0.3

IB = 2.0 A

0.6

0.2

IB = 1.0 A

0.1
0.0

Collector - Emitter Voltage, VCE (V)


Figure 5. Output characteristics of a BJT. The reason for the VCE
dependence of IC is the Early effect.
9

DC Parameter Extraction and Modeling of Bipolar Transistors

Intrinsic transistor
REPoly

RBPoly
RBpoly-Epi
LOCOS

p+
Rn-epi

RCPlug

n-

p+

RBuriedC

n+
n+

Figure 6. Schematic cross section of a double poly-Si transistor showing


different parasitic resistances.

Resistive Voltage Drops


The intrinsic transistor only constitutes a small part of the layout as
can be seen in Fig. 6. The extrinsic parts, such as the extrinsic base and the
buried collector, contribute to parasitic resistances that the terminal
currents must pass through. Figure 6 depicts the different resistances
present in the double poly-Si BJT.
For

large

terminal

current

densities,

typically

above

1-10105 A/cm2, the voltage drop over the parasitic resistances must be
considered.

Base Current, IB (A)

10

The

effects

of

these

resistances

are

shown

-1

VBE
10

10

10

10

-3

-5

-7

-9

0.50

0.75

1.00

1.25

1.50

Emitter-Base Voltage, VBE (V)


Figure 7. IB plotted against VBE. The dotted line represents IBIdeal and the
straight line is the measured IB.
10

p+

Chapter 2. The Bipolar Transistor

in Fig. 7, where the base current IB is plotted vs. the base-emitter voltage
VBE. The deviation from the ideal behavior of IB is VBE = IBRBTot +
IERE, where RBTot is the total base resistance and RE is the emitter
resistance. As will be discussed later, the voltage drop over the collector
resistance may force the transistor into quasi saturation.

Emitter Current Crowding


The distributed nature of the base-emitter junction causes the
potential of the intrinsic base region to vary laterally. This is due to the
lateral voltage drop over the intrinsic base resistance, caused by the base
current. Since the base current is injected from the sides of the intrinsic
base, the base-emitter junction is more forward biased near the edges of
the emitter window and more electrons will be injected there as compared
to the center region of the emitter. Figure 8 shows the potential
distribution along the intrinsic base region. The base current is injected
from the right hand side in Fig. 8. In the transistor behavior, this effect
appears as a lowering of the intrinsic base resistance and will be discussed
in detail in Chapter 3.

1.06

Voltage, V(x) (V)

1.04
1.02
1.00
0.98
0.96
0.94
0.92
0.90
0.88
0.0

0.2

0.4

0.6

0.8

1.0

Distance, x (m)
Figure 8. Schematic potential distribution along the intrinsic base region
in forward mode of operation.
11

DC Parameter Extraction and Modeling of Bipolar Transistors

Further on, the current crowding effect causes other high injection effects
to appear locally for smaller currents than can be expected when assuming
uniform current distribution.

Base Conductivity Modulation


When the concentration of the injected minority carriers in the base
region is comparable with the background doping, the conductivity is
modulated according to:
=

q = p p 0
1
= q ( p p + n n ) = b
q p p 0 qb .

p >> n

(2)

For low currents, qb = 1 and = qpp0. However, when the base current
increases, the hole concentration in the base increases and p > p0.
Therefore the conductivity in the base is increased. Since the intrinsic base
resistance is reduced by this effect, the voltage drop that causes the emitter
current crowding is reduced. Consequently, the base conductivity
modulation effect and the current crowding effect counteract each other.
In Paper 3, the current dependence of the base resistance reduction is
investigated for both of these effects. It is shown that the two effects cause
different current dependence of the base resistance, this will be discussed
further in Chapter 3.

The Kirk Effect


The Kirk effect [5, 14, 15], also called base push-out, occurs when
the concentration of the injected electrons from the base-emitter junction
into the collector region is comparable with the doping level in the lowdoped collector region. As IC increases, the electron concentration in the
epitaxial collector exceeds NC,EPI. Thus the positive space charge in the
collector side of the base-collector depletion region is overcompensated by
electrons injected from the emitter. The electrical base-collector junction
is then pushed to the n- - n+ junction in the collector. Holes are injected
into the n- collector region to fulfill quasi neutrality, resulting in an
increased IB due to recombination currents. Therefore, the current gain is
degraded. The Kirk effect is demonstrated in Fig. 9,

12

Potential (V)

Chapter 2. The Bipolar Transistor

0.4

0.70 V

0.2

0.80 V
0.85 V

0.0
-0.2

0.90 V

-0.4

1.00 V

-0.6 Emitter Base


0.00

0.25

0.50

Collector
0.75

1.00

1.25

1.50

1.75

2.00

Distance (m)
Figure 9. The potential through the transistor for VBE = 0.7, 0.8, 0.85, 0.9
and 1 V.

showing the electrostatic potential for different VBE, simulated using the
Silvaco software [16]. The collector current density when the Kirk effect
starts (JC,KIRK) may be defined as when the electron concentration in the
epitaxial collector (nC,EPI) becomes 10% of NC,EPI, implying that:
JC,KIRK 0.1 q vs NC,EPI

(3)

where vs is the saturation velocity for electrons in the base-collector


depletion region. From Fig. 9, it is clear that the Kirk effect causes the
internal

base-collector

junction

to

become

forward

biased

for

0.85 V < VBE < 0.9 V. This behavior is similar to what is observed when
the transistor is operated under quasi saturation conditions.

Quasi Saturation
This effect occurs when the voltage drop over the collector
resistance (IC RC) is large enough to cause the base collector junction
to be forward biased, even though it is externally reverse biased.
Consequently, holes are injected into the collector region, IB increases and
decreases. The effect of quasi saturation is indeed similar to the Kirk
effect and no physical difference can be found in the intrinsic transistor
[5]. However, the quasi saturation effect is clearly evident in the output
13

Collector Current, IC (mA)

DC Parameter Extraction and Modeling of Bipolar Transistors

0.20

IB = 1.0 A

0.15

0.10

0.05

0.00

Collector - Emitter Voltage, VCE (V)


Figure 10. IC(VCE) characteristics at IB = 1 A for three different ncollector thicknesses, wn-. Squares represent wn- = 0.5 m, circles wn- =
1.0 m and triangles wn- = 1.5 m.

characteristics of the transistor. In Fig. 10, simulated output characteristics


is shown for three cases. The simulated structures are similar except for
the thickness of the n- epitaxial collector layer, wn-. A larger wn- results in a
higher collector resistance RC. Thus, the quasi saturation effect becomes
more pronounced as wn- is increased. The slower increase in IC for larger
wn- that can be observed in Fig. 10 is typical for the quasi saturation effect.

2.3. Compact BJT Modeling


For efficient circuit design, accurate transistor models are crucial.
The history of compact bipolar transistor models starts with the EbersMoll model [17]. It is a simple model of two back-to-back diodes. This
model is still the basis of all the modern bipolar models. The evolution
continued with the development of the Gummel-Poon [18] model. The
normalized majority base charge qb was introduced and consequently the
14

Chapter 2. The Bipolar Transistor

base width modulation effects (Early effect) [13] are included in the
model. Most of the following models are based on the qb concept. More
recent models, such as the VBIC95 [3] and the MEXTRAM [4] model
also includes quasi saturation effect [15], Kirk effect [14] and base
conductivity modulation. The models for describing the non-linearity in
the different parasitic capacitances and resistances have also been further
improved. In addition, careful modeling of the parasitic pnp transistor
(base-collector-substrate) is included. The resulting transistor models are
complex, consisting of a large number of model parameters. However, the
ability to predict transistor performance is greatly improved compared to
earlier models. This chapter briefly reviews the different compact BJT
models that can be found in the literature and that has been used or
referred to in the appended papers.

The Gummel Poon Model


Gummel and Poon [18] improved the Ebers-Moll model by
introducing the integral charge control concept. By using the normalized
majority base charge qb, the model inherently considers the base width
modulation (Early effect). Further on, a current-dependent base resistance
RB(IB) was introduced. A detailed discussion about modeling of the base
resistance is given in Chapter 3. Later, the model was extended to include
quasi-saturation or the Kirk effect [14, 15]. However, the model of these
effects is not very smooth which may cause problems with convergence.
Further on, the modeling of the cut-off frequency and output conductance
is not very accurate since they are given by the derivatives of the currents.
Figure 11 shows the equivalent circuit of the Gummel-Poon model.

15

DC Parameter Extraction and Modeling of Bipolar Transistors

C
RC

VBC

nCLVT
C4 I S e
1

RB

CSUB

C
IEC
R

CjC

CDC

ICT=ICC-IEC

V B E

n V
C 2 I S e EL T 1

ICC
F

CjE

CDE

E
RE

E
Figure 11. Equivalent circuit of the Gummel Poon model.

The transport current ICT is given by:


V B 'C '
V B 'E '
I SS VT
e VT
I CT =
e
qb

(4)

where ISS is a fundamental device parameter given by


I SS =

qADn ni2

(5)

xC

N A (x )dx

xE

with xC and xE given at zero bias. The normalized base charge qb is defined
as
2

q
q
qb = 1 + 1 + q 2
2
2

(6)

where q1 models the base width modulation effect (Early effect) and q2 the
high injection effects. By assuming constant junction capacitances, i.e.
that the depletion charges are linearly dependent upon voltage, q1 is given
by

16

Chapter 2. The Bipolar Transistor

V
V
q1 = 1 B ' E ' B ' C '
V AR
V AF

(7)

Equation (7) is actually not the correct formulation of q1. A more correct
formulation is [20]
V
V
q1 = 1 + B ' E ' + B 'C ' .
V AR
V AF

(8)

The reason that Eq. (7) was used in the Gummel-Poon model is that the
resulting current expression then was consistent with the Ebers-Moll
model [20]. In the more recent versions of the Gummel-Poon model
Eq. (8) is used for calculating q1. The high injection base charge q2 is
modeled according to

V B 'E '

I SS N F VT
1 +
q2 =
e
I KF

V B 'C '

I SS N RVT
1 ,
e
I KR

(9)

where IKF and IKR are the forward and reverse knee currents, respectively.
The VBIC95 Model
The VBIC model (Vertical Bipolar Inter Company) was developed
in a joint project including many of the largest bipolar manufacturers in
the world [3]. It is based on the Gummel-Poon model [18]. However,
some major improvements are presented. The q1 formulation is not the one
based on the linearized depletion charges used in the Gummel-Poon
model. In VBIC95, q1 is given by:
q1 = 1 +

q je
VER

q jc
VEF

(10)

where qje and qjc are functions describing the voltage dependence of the
base-emitter and the base-collector depletion charges, respectively. The
parameters VER and VEF are referred to as the bias-dependent reverse and
forward Early voltages, respectively, in contrast to VAR and VAF which are
constant model parameters. It is notable that qje, qjc, VER and VEF are
dimensionless parameters. By using functions for describing the depletion
charges the prediction of output conductance and cut-off frequency is

17

DC Parameter Extraction and Modeling of Bipolar Transistors

greatly improved compared to the Gummel-Poon model [20]. Further on,


the modeling of the quasi saturation effect is improved.

The MEXTRAM 504 Model


The MEXTRAM model (Most EXquisite TRAnsistor Model) is a
very complex compact model [4]. The model was developed by Philips
and is a subject of continuous development [e.g. 21]. The latest version,
MEXTRAM 504, requires close to 90 model parameters. In its
formulation, this model is much similar to the VBIC95 model. However,
major improvements are made in the smoothing functions used for
describing the high injection effects in the collector epilayer [5]. These
improvements serve to both increase the model accuracy and the
convergence of the model since the derivatives are continuous functions.
As in VBIC95, the MEXTRAM 504 model for the intrinsic base resistance
considers only base conductivity modulation. However, the model uses an
additional base emitter diode, connecting to the base between the
extrinsic and the intrinsic part of the base resistance. Thus, one could
argue that MEXTRAM 504 is a first order distributed model and therefore
current crowding effects are included in the model. Further on, the
MEXTRAM 504 model for the intrinsic base resistance includes both
current crowding and base conductivity modulation effects.

18

Chapter 3. Modeling of the Base Resistance

3. Modeling of the Base Resistance


The base resistance has a large impact on device performance, both
for DC and high frequency operation. Therefore, the accuracy of a
compact transistor model is much determined by its ability to predict the
base resistance of the device. Modeling of the non-linear current
dependence of the base resistance has drawn much attention in the
literature [e.g. 19, 22-26]. In this chapter, the different definitions of the
base resistance are first reviewed. Then, the distributed models found in
the literature are discussed and the model presented in Paper 7 is
described. In compact BJT models, the base resistance models should
preferably be direct functions of the current and/or voltages of the device.
Therefore, the distributed models are not suitable for implementation in
circuit simulators. The last section of this chapter deals with the different
compact base resistance models that are used in BJT models. Also, a brief
description of the compact base resistance model presented in Paper 3 will
be given.

19

DC Parameter Extraction and Modeling of Bipolar Transistors

Total Base Resistance,


RBTot(IB) ()

175
150
125
100
75
50
25
-6
10

-5

10

10

-4

-3

10

10

-2

Base Current, IB (A)


Figure 12. Schematic IB dependence of RBTot.

3.1. Basic Concepts


The total base resistance RBTot, consists of two parts, one extrinsic
part RBExt and one intrinsic part RBInt. A typical RBTot vs. IB plot is shown in
Fig. 12. The decrease in RBTot is due to the decrease of the intrinsic part
RBInt. As discussed earlier, the reason for the current dependence of RBInt is
mainly due to current crowding and base conductivity modulation.
In the literature, many different definitions of the intrinsic base
resistance can be found [19, 26, 27]. One way of defining RBInt(IB) is to
state that the power dissipation in the intrinsic base region PBase should be
the same as the power dissipated in RBInt(IB) by IB. Thus, RBInt is given by
PBase ( I B ) =

Power
I B RBInt
(I B )

WE

I 2 ( x)

R B 0 dx
qb ( x ) W E

(11)

where RB0 = RSq.WE/LE is the physical resistance of the intrinsic base


region for small IB and RSq. is the intrinsic base region sheet resistance.
Historically, the power dissipation definition has been the most widely
used, due to the fact that it was used in the derivation of the Gummel-Poon
model of RBTot(IB) [19, 28]. However, as is mentioned in [29] and shown in
Paper 7, this definition is not compatible with the definition used when
20

Chapter 3. Modeling of the Base Resistance

formulating compact BJT models. In the compact models RBInt is defined


according to Fig. 13. Consequently, RBInt is given by

Compact
RBInt
(I B )

Eff
VBE VBE
=

IB

I
VBE VT ln B
IS
=
IB

(12)

Eff
where VBE
is the effective base-emitter voltage. A third definition that is

useful for extraction of the base resistance parameters is the dual base
terminal definition. This definition is convenient when measuring the base
resistance using the dual base terminal test structure and will be discussed
in detail in Chapter 4.3. RBInt(IB) is defined as the voltage drop over the
whole intrinsic base region divided by IB. Thus, it reads
Dual Base
RBInt
(I B ) =

V (WE ) V (0)
IB

(13)

where V(WE) is the applied voltage at one side of the base region and V(0)
is the resulting voltage at the other side.

IB

B
RBInt(IB)
Figure 13. The base-emitter branch of a compact BJT model. The emitter
resistance RE and the extrinsic base resistance RBExt are left out for clarity.

21

Intrinsic Base Resistance,


RBInt(IB) ()

DC Parameter Extraction and Modeling of Bipolar Transistors

200

150

100

50

0
-6
10

Dual Base def.


Compact Model def.
Power Dissipation def.
10

-5

10

-4

10

-3

10

-2

Base Current, IB (A)


Figure 14. Three different definitions of RBInt, simulated with the
distributed model presented in Paper 7.

In Fig. 14, the three definitions of RBInt are plotted versus IB. Data are
calculated using the distributed model presented in Paper 7. The physical
resistance RB0 in the calculations is 400 . The low current value for the
dual base terminal definition (Eq. (13)) corresponds to 1/2RB0. For the
other definitions this value is 1/3RB0 which is known from textbooks [e.g.
30]. This difference has to be corrected for when using the dual base
terminal test structure for extracting the base resistance model parameters.
It is also clear that the power dissipation definition is not compatible with
the compact model definition.

3.2. Distributed Transistor Modeling


In compact models, two-dimensional effects (such as current
crowding) are not always easy to implement with a clear coupling to the
physical layout. In order to model these effects accurately, the distributed
nature of e.g. the base emitter junction must be considered. The
equivalent circuit of a distributed model is shown in Fig. 15.

22

Chapter 3. Modeling of the Base Resistance

IT

RE

E
VBEi(x)

B
x

RBInt dx
WE

RBExt
x=WE

Figure 15. Equivalent circuit of a distributed transistor model.

In Fig. 15, the potential drop dV over a segment dx is given by

dV ( x) =

R BInt
RB 0
I ( x) dx =
I ( x) dx .
WE
W E qb ( x )

(14)

Further on, the change in current dI in that segment is [19, 25-27]

dI ( x) =

V ( x)
IS
dx
exp
WE
VT

(15)

The resulting differential equation when combining Eqs.(14) and (15) is


RB 0 I S
V ( x) dq b ( x) dV ( x)
1
d 2V ( x)


exp
=

qb ( x) WE2
V
dx
dx
dx 2
T

(16)

The boundary conditions for Eq. (16) are [19, 25-27]

dV ( x)
dx

=0

(17)

x =0

V (0) = V0 .

(18)

If the complete formulation of qb(x) is used in Eq. (16), numerical solution


is required. Earlier studies have either neglected the base conductivity
modulation, i.e. qb = 1 [19, 26, 27], or used a simplified formulation of qb
that is not very correct for large voltages [25]. No distributed model that
includes the Early effect has previously been presented. In Paper 7, such a
model is presented and analysed in detail. By including the Early effect in
the qb formulation of the model, the VCE dependence of qb(x) and RBInt(IB)
is described, see Fig. 16.

23

Normalized Base Charge,


qb(x)

DC Parameter Extraction and Modeling of Bipolar Transistors

2.00

VCE = 1 V
VCE = 3 V
VCE = 5 V

1.75

1.50

1.25

1.00

0.0

qb = 1
0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Normalized Distance, x
Figure 16. The VCE dependence of the qb distribution along the intrinsic
base region. The calculations are for VAF = 10 V and VAR = 5 V, the other
parameters are those presented in Paper 7.

By neglecting qb, i.e. qb(x)=1, both the Early effect and base
conductivity modulation are neglected. Equation (16) then corresponds to
the model presented in [19]. The solution of Eq. (16) is then [19]
cos[Z (1 x WE )]
V ( x ) = V (WE ) 2VT ln
.
cos( Z )

(19)

where Z is an intermediate parameter given by


Z tan( Z ) =

RB0 I B
.
2VT

(20)

Adopting the power dissipation definition (Eq. (11)), RBInt(IB) may be


written
tan( Z ) Z
.
RBInt ( I B ) = RBInt (0)
Z tan 2 ( Z )

(21)

The RBTot model used in the SPICE version of the Gummel-Poon model is
based on Eq. (21). However, a simplified expression for Z(IB) is used,
which will be treated in the following section.

24

Chapter 3. Modeling of the Base Resistance

3.3. Compact Models of the Base Resistance


In the Ebers-Moll model, the base resistance, RBInt was modeled as
a constant resistance. The current dependence of RBInt was first included in
the Gummel-Poon model. The RBInt(IB) model was a simplified
formulation of the distributed model derived by Hauser [19], shown in Eq.
(21). However, in order to make the RBInt(IB) expression an explicit
function of IB, Z(IB) is simplified compared to the formulation in [19] (Eq.
(20)) and reads:
Z (I B ) =

1 + 1 + 144 I B / 2 I rB

(24 / )
2

(22)

I B / I rB

where IrB is defined as the base current at which RBInt(IB) = 1/2 RBInt(0).
Since the model is based on a distributed transistor model it accounts for
current crowding effects. However, the effect of base conductivity
modulation is neglected. Further on, the derivation of Eq.(21) is based on
the power dissipation definition of RBInt [19] which was shown earlier and
in Paper 7 to not be compatible with the compact model definition.
In the base resistance models included in MEXTRAM and
VBIC95, the current dependence of RBInt is solely due to the base
conductivity modulation. RBInt(IB) is then given by:

RBInt ( I B ) =

RBInt 0
,
qb ( I B )

(23)

where RBInt0 is the low current value of the base resistance. In [3], the need
for a compact model of RBInt(IB) that considers both current crowding and
base conductivity modulation was pointed out. Such a model is presented
in Paper 3. By adding a new parameter to the qb formulation used in
Eq.(23), the model for RBInt(IB) in VBIC95 is modified to also include the
effects of current crowding. The new qb(VBE), qb,(VBE) for large currents,
including the new parameter, may be written as

V
I
1
qb, (VBE ) = 1 + 1 + 4 S exp BE
2
I KF
N F VT

(24)

25

DC Parameter Extraction and Modeling of Bipolar Transistors

where = 0.5 is the usual qb formulation. If instead is used as a fitting


parameter, allowed to vary between 0.5 and 1, it is shown in Paper 3 that
Eq. (24) also covers the case of current crowding.

3.4. Small Signal Modeling of the Base Resistance


The intrinsic base resistance in the linearized small signal
transistor model (from now on rB) is given by the differential resistance rB
which is defined as [19, 26, 27, 31, 32]:
rB = RBInt +

dRBInt
IB
dI B

(25)

Inserting the large signal model of RBInt(IB) presented in Paper 3 into


Eq. (25), the resulting small signal model of rB is:

rB =

2 x (1 + 2 x ) 1
2 RBInt 0

1 + (1 + 2 x )
1 + (1 + 2 x )

(26)

where x = IB / IRB. Equation (26) can be rewritten as:


2 x (1 + 2 x ) 1

rB = RBInt 1

1 + (1 + 2 x )

(27)

This small signal model considers both emitter current crowding ( close
to 1) and base conductivity modulation ( close to 0.5) as causing the
decrease in RBInt at high currents, as shown in Paper 3. In Fig. 17, the
small signal model is compared to the large signal model for three
different values of . Since dR BInt dI B in Eq. (25) always is negative, rB
is smaller than RBInt.

26

Chapter 3. Modeling of the Base Resistance

Normalized RB, rB

1.0

(a)

0.8
0.6

= 0.5

0.4
0.2

Normalized RB, rB

0.0
1.0

(b)

0.8
0.6

= 0.75

0.4
0.2

Normalized RB, rB

0.0
1.0

(c)

0.8
0.6

= 1.00

0.4
0.2

Large Signal RB
Small Signal rB

0.0
-4
-3
-2
-1
0
10
10 10
10
10
IB / IRB

10

10

10

Figure 17. Comparison between the small signal model (dashed lines) and
the large signal model (solid lines) of the intrinsic base resistance for (a)
= 0.50, (b) = 0.75 and (c) = 1.00.

27

DC Parameter Extraction and Modeling of Bipolar Transistors

28

Chapter 4. DC Extraction of Compact Model Parameters

4. DC Extraction of Compact Model Parameters


For a transistor model to be accurate it is important that the model
parameters are correct. First we have to define what is meant by correct. It
is not always true that the correct value of a physical parameter gives the
best accuracy of the transistor model. This is due to two reasons. First, the
model formulation is based on some assumptions and simplifications that
make the parameters difficult to interpret physically. Second, many
parameters are coupled to each other, meaning that a small error in one
parameter may require another parameter to take non-physical
proportions. However, since the modern parameter extraction routines [33]
utilize a global optimization scheme, it is extremely important that the
initial model parameters are close to the correct ones. Otherwise, the
optimization routine may be trapped in a local minimum.
In the following section, extraction of the intrinsic model
parameters is described. Extraction of the parasitic resistances is presented
in section 4.2. The dual base terminal test structure is presented in section
4.3. As shown in Paper 2, Paper 3, Paper 4 and Paper 6, this test structure
enables extraction of both resistances and Early voltage parameters. In the
final section of this chapter, the dual collector terminal test structure,
presented in Paper 5, is discussed.

29

DC Parameter Extraction and Modeling of Bipolar Transistors

4.1. Intrinsic Parameters


The intrinsic model parameters e.g. the Early voltages VAF, VAR, the
saturation currents IS and the ideality factors NF and NR, are of crucial
importance for accurate BJT modeling. Different extraction schemes have
been proposed in the literature [18, 20, 34, 35]. For an extraction
procedure to be accurate it is important that it is based on the physics of
the model. For example, VAF and VAR extraction must be coupled since
both the emitter-base and the base-collector depletion widths are
modulated simultaneously. Typically, the extraction procedure is based on
forward and reverse output and Gummel characteristics.

Early Voltages
Historically, the forward Early voltage VAF has been extracted from
the intercept with the VCE axis of the extrapolated IC(VCE) plot for constant
IB or VBE, as shown in Fig. 18. The reverse Early voltage VAR has similarly
been extracted as the intercept with the VEC axis of the extrapolated
IE(VEC) plot for constant IB or VBC [35]. This extraction technique
decouples the two effects (forward and reverse Early effect). This means
that when extracting VAF the reverse Early effect is neglected and vice
versa. In [34], a technique for extracting both VAF and VAR in a coupled
manner was presented. It is based on a procedure where normalized data
are used. As discussed previously, when modeling the Early effect with
constant Early voltages, the output conductance is assumed to be constant.
In the more recent compact models like VBIC95 and MEXTRAM, the
Early voltages are modeled as bias-dependent quantities and the prediction
of the output conductance is much improved. A technique for extracting
the bias-dependent Early voltage parameters are presented in [20]. Base
emitter and base collector capacitance data are used to extract the builtin potential Pe and Pc and the grading coefficient mje and mjc for

30

Chapter 4. DC Extraction of Compact Model Parameters

Collector Current, IC (nA)

5
4
3
2
1
0

VAF = 28 V

-30

-25

-20

-15

-10

-5

Collector - Emitter Voltage, VCE (V)


Figure 18. Traditional extraction of VAF.
the respective junction. These parameters are used in the models for the
junction charges qje(VBE) and qjc(VBC). The bias-dependent Early voltage
parameters VEF and VER are then calculated from forward and reverse
output data for low biases. In Paper 6, an alternative extraction procedure
for the bias-dependent Early voltage parameters is presented. The
procedure is based on DC measurements on the dual base terminal test
structure. Since the capacitance parameters are extracted from DC
measurements, no C-V measurements are required. This extraction
procedure is discussed further in section 4.3.

Current Parameters
When the Early effect parameters are known, the current
parameters ISS, IKF, IKR, F and R are extracted. Typically, forward and
reverse Gummel characteristics are used, see Fig. 19. Since qb is known,
ISS and the forward ideality factor NF can be extracted by fitting
IC =

VBE
VT

I SS e
q b (VBE )VBC =0

(28)

31

Collector Current, IC (A)

DC Parameter Extraction and Modeling of Bipolar Transistors

-3

10

-5

10

-7

10

-9

10

Extraction of IS

-11

10

-13

10

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Base - Emitter Voltage, VBE (V)


Figure 19. Region used for extraction of the saturation current IS by
fitting Eq. (28) to measurement data. Measurement is performed
for VBC = 0 V.
at VBC = 0 V. Typically, the curve fitting is performed in the voltage range
0.4 V < VBE < 0.8 V [36], see Fig. 19. The forward knee current IKF is
extracted from the F (= IC / IB) versus log(IC) plot as the value of IC when
F has dropped to half its peak value, see Fig. 20. The reverse knee current
IKR is extracted in the same way for data in reverse mode of operation. In
modern extraction software [e.g. 33], these parameters are then optimized
after the resistances are extracted in the high current operation regime.

32

Forward Current Gain, F

Chapter 4. DC Extraction of Compact Model Parameters

250

200

150

100

Forward Knee Current, IKF


50

0
-6
10

-5

10

-4

10

-3

10

Collector Current, IC (A)


Figure 20. Extraction of the forward knee current, IKF.

4.2. Parasitic Resistances


For large currents, the parasitic resistances of the model are
important since the voltage drops over these resistances are significant.
High frequency transistors are usually operated in this regime, making
these parameters very important for accurate prediction of transistor
behavior. It is possible to calculate the resistances out of the doping levels
and geometry. However, current distribution and small geometries makes
it difficult to achieve satisfactory agreement between measurements and
simulations using the calculated resistances. Extraction of these
parameters may be performed from e.g. S-parameter [37], AC [22], noise
[38] and DC measurements [e.g. 39-41]. DC extraction techniques are
generally preferred due to the fact that they are both time and cost
effective. This in turn enables automated statistical wafer mapping to be
performed for increased accuracy of the model parameters as well as
increased process control. In this section, the most widely used DC
extraction techniques will be reviewed.

33

DC Parameter Extraction and Modeling of Bipolar Transistors

Ning-Tang method
The Ning-Tang method allows extraction of RE, RBExt and RBInt
[39]. From IB(VBE) data at large voltages, the deviation from the ideal
behavior VBE is written as
VBE = RE I E + RBTot I B

(29)

where VBE is extracted from the Gummel characteristics. Equation (29)


can be rewritten to read
VBE
= RE + (RE + RBTot ) 1
IC

(30)

where IE = IC + IB and IB = IC has been used. By assuming that RBInt is


proportional to , the plot of VBE / IC versus -1 will be a straight line
with a slope equal to RE + RBExt and the intercept with the y-axis equal to
RE + RBInt / . In Fig. 21, extraction according to this method is
demonstrated. The slope ( 300 ) roughly corresponds to RBExt since RE
is normally much smaller then RBExt. The intercept with the y-axis ( 30
) is more difficult to interpret due to the RBInt / term. However, by
using different emitter geometries separation of RE and RBInt / is enabled.
It is worth to mention that the assumption that RBInt is proportional
to is only valid when current crowding effects are negligible.

500
40
30

300

20

200

10
0
0.010

100

0.015

0.020

0
0.025

Reciprocal Current Gain, 1/


Figure 21. Resistance extraction according to the
Ning-Tang method [39].
34

Slope ()

VB1E / IC ()

400

Chapter 4. DC Extraction of Compact Model Parameters

Otherwise, the current dependence of RBInt will be different and not


directly proportional to . In that case, as is shown in Paper 2, the VBE /
IC versus -1 plot will not be linear and thus the parameter extraction
ambiguous.

Weng method
Weng et al. proposed a method for extraction of RBExt and RBInt
[23]. The method is based on a test structure consisting of a transistor with
two separated base terminals, B1 and B2, respectively. This test structure
will be discussed in detail in Chapter 4.3. In [23], the extraction procedure
included measurements of forward operation data while the additional
base terminal senses the voltage. The sense voltage VB2 is assumed to be
that of the intrinsic base. The total base resistance RBTot (= RBExt + RBInt) is
then calculated according to:
V V
RBTot ( I B ) = B1 B 2
I B1

(31)

where VB1 is the biasing voltage and IB1 is the current supplied by terminal
B1. RBInt(IB) is formulated to read
RBInt ( I B ) =

W 2d
1
RSq. E
3
LE

(32)

where RSq. is the sheet resistance of the intrinsic base, WE and LE is the
drawn emitter width and length, respectively and d is the deviation of the
real WE from the drawn. By plotting the extracted RBTot vs. WE for various
VB1E the point where the lines intercept corresponds to WE = 2d and
RBTot = RBExt. However, measurement data reveals that this intercept is
bias-dependent, implying that RBExt varies with bias, which is nonphysical. The reason for this is that when assuming Eq. (32) to be valid,
current crowding is neglected. All of the current dependence of RBInt is
then included in RSq.. Consequently, base conductivity modulation is
assumed to be the only cause for the decrease in RBInt(IB). If current
crowding is present, RBInt should be formulated to read
RBInt ( I B ) = f CC ( I B ) RSq.

WE
LE

(33)

35

DC Parameter Extraction and Modeling of Bipolar Transistors

where fCC(IB) is a function that describes the current crowding effect. The
fact that current crowding is neglected results in a bias dependence of the
intercept observed in Fig. 22. Further on, the factor of 1/3 in Eq. (32),
although accurate for compact models, should not be used when RBInt is
measured according to Eq. (31). As is pointed out in Paper 4, a prefactor
of 1/2 should be used instead.

Fly-back method
This method was first proposed by Kulke and Miller in [40]. Later,
Giacoletto [41] proposed a similar procedure. The method allows for
extraction of either RE or RC. For extraction of RE, VCE is measured as a
function of IB with the collector terminal left open, i.e. IC = 0 A. This
means that the transistor is operating in saturation. The saturation voltage
VCE,sat can be expressed as
VCE , sat = VC ' E ' + I C RC + I E R E

(34)

where VC'E' is the internal voltage between the collector and emitter node.

Base Resistance, RBTot (k)

By using the Ebers-Moll model formulation for VC'E' , Eq. (34) can be

14
VBE = 0.80 V

12
10

VBE = 0.85 V

8
VBE = 0.90 V

6
4
2
0
0

2
3
4
5
Emitter Width, WE (m)

Figure 22. Measured RBTot as a function of drawn WE for VBE = 0.8, 0.85
and 0.9 V.

36

Chapter 4. DC Extraction of Compact Model Parameters

written as
I

1 C

I B
VCE , sat = VT ln R
1 + (1 ) I C
R

IB

+ I C RC + I E RE

(35)

where R is the reverse common base current gain. Since IC = 0 A and IE =


IB, Eq. (35) is reduced to
VCE , sat = C + I B RE

(36)

where C is a constant. Therefore, RE can be extracted as the slope of the


VCE,sat(IB) plot, as is shown in Fig. 23. RC can be extracted in a similar
manner by leaving the emitter terminal open during measurements.
However, it is worth to mention that the measured RC only corresponds to
the part of the collector resistance originating from the buried collector
and contact resistance, i.e. the constant part RCC. The variable part RCV
may not be measured using this method. Recently, improvements of this
extraction method were proposed which also includes the substrate effects
[42].

Base Current, IB (A)

10

1/RE
4

5.20

5.25

5.30

Collector - Emitter Voltage, VCE (mV)


Figure 23. Extraction of RE using the fly-back method. Data are from
Silvaco simulations [16].
37

DC Parameter Extraction and Modeling of Bipolar Transistors

4.3. Dual Base Terminal Test Structure


The different trade-offs regarding the design of the dual base
terminal test structure is presented in Paper 5. A schematic layout of the
test structure is shown in Fig. 24. Parameter extraction is done by using
one of the base contacts as a voltage tap, i.e. setting the current to zero and
measuring the voltage [23, 27]. RBTot(IB) is given directly according to
V VB 2
RBTot ( I B ) = B1
.
I B1

(37)

However, as is shown in Chapter 3, this base resistance is measured


according to the dual base terminal definition of RBInt. Therefore, a
conversion is required if the compact model parameters are searched for.
A conversion scheme is presented in Paper 3.
The dual base terminal test structure also allows for extraction of
RE from the same measurement data. The voltage difference between the
sense terminal B2 and the emitter can be written as
Eff
VB 2 E = VBE
+ RE I E .

(38)

Eff
where VBE
is the effective base emitter voltage. If current crowding
Eff
dominates, VBE
becomes pinned to a certain value, even though VB1E is

further increased [27]. RE may then be extracted from the slope of the VB2E
versus IE plot. However, if base conductivity modulation occurs, the VB2E

E
B1

Contact holes

LOCOS

B2

Emitter Poly-Si

Figure 24. Simplified layout of a single poly-Si dual base terminal test
structure.

38

Chapter 4. DC Extraction of Compact Model Parameters

versus IE plot will not be linear, rendering the extraction of RE more


elaborate. In Paper 2, a procedure for extracting RE under these
Eff
circumstances is proposed. Using a simple diode model, VBE
in Eq. (38)

is calculated from
I
I B1 = S
F

Eff
exp VBE

N F VT


1 .

(39)

The sheet resistance of the intrinsic base region RSq. can also be
extracted using the dual base terminal test structure. A procedure for
extraction of RSq. is presented in Paper 4. The measurement procedure is
the same as for the pinched base measurements. However, by considering
the Early effect, the zero bias sheet resistance is extracted with large
accuracy. Further on, in Paper 6 extraction of the bias-dependent Early
voltage parameters is demonstrated using only DC measurements on the
dual base terminal test structure. By measuring the current between
terminals B1 and B2 for different collector and emitter biases, the Early
voltage can be calculated for each bias point. Thus, the bias-dependent
Early voltages are extracted. This in turn allows for calculation of the
built-in potentials and grading coefficients for both the emitter-base and
the base-collector junctions. Consequently, the capacitance measurements,
otherwise needed for extraction of these parameters, are not necessary.
The measurement effort is thus considerably reduced.

4.4. Dual Collector Terminal Test Structure


In Paper 5, a new type of test structure is proposed which adopts
the basic ideas from the dual base terminal test structure. A second
collector terminal C2 is added on the adjacent side of the emitter to C1.
Figure 25 shows a schematic layout of the proposed test structure. The C2
terminal is used for sensing the voltage in the buried collector. RCC is
given directly under forward biasing conditions from

RCC =

VC1 VC 2
.
I C1

(40)

39

DC Parameter Extraction and Modeling of Bipolar Transistors

C1
B1

C2
B2

Figure 25. A simplified layout of the dual collector terminal test structure.

All measurements and extraction procedures developed for the dual base
terminal test structure are possible to transfer to the dual collector terminal
test structure. However, since the collector region is not modeled in the
same way as the base region, only extraction of RCC is directly applicable
to compact BJT modeling.
In Fig. 26, RCC extracted according to Eq. (40) is plotted for three
different emitter widths as a function of the collector current. As shown in
Paper 5, the dramatic drop that occurs for high currents is due to the Kirk
effect [14]. It was observed in SILVACO simulations [16] that the
collector current takes a shortcut along the field oxide and thus never
passing through the n+-epi layer.
Similar to the pinched base measurements, the additional collector
terminal allows for pinched collector measurements. In such a way, the
sheet resistance of the buried collector layer can be determined. However,
knowledge of the drawn dimensions of the buried collector layer is
required.

40

Collector Resistance, RCC ()

Chapter 4. DC Extraction of Compact Model Parameters

28
26

WE = 3 m

24
WE = 1.2 m

22

WE = 0.6 m

20
18
-4
10

-3

10

10

-2

10

-1

Collector Current, IC1 (A)


Figure 26. RCC extracted according to Eq. (40) for
WE = 0.6, 1.2 and 3.0 m.

41

DC Parameter Extraction and Modeling of Bipolar Transistors

42

Chapter 5. Concluding Remarks

5. Concluding Remarks

In this thesis, different aspects of DC parameter extraction and


modeling of bipolar transistors have been treated. Emphasis is given to the
dual base terminal BJT test structure which is shown to enable extraction
of the emitter resistance RE, the extrinsic and intrinsic base resistance RBExt
and RBInt and the sheet resistance of the intrinsic base region RS00 from DC
measurements. DC extraction of parameters traditionally requiring
capacitance measurements is also shown. These parameters are the biasdependent Early voltages VER and VEF, the built-in potentials Pe and Pc and
the grading coefficients mje and mjc of the base-emitter and the basecollector junctions, respectively. A compact model of the currentdependent base resistance is proposed. The formulation is compatible with
state-of-the-art compact BJT models. Further on, a new test structure is
proposed which uses two separated base terminals and two separated
collector terminals. Measurements on this test structure enable direct
extraction of the constant part of the collector resistance and monitoring of
the base push-out effect. Finally, a general formulation of a distributed
model of the base-emitter junction is presented. By including the Early
effect in the model formulation, more accurate calculations of the base
resistance and the current, voltage and base charge distributions along the
intrinsic base region is enabled, compared to earlier formulations.
43

DC Parameter Extraction and Modeling of Bipolar Transistors

During my time working with test structures, I have learned that


the industry is relatively conservative regarding the use of test structures
for extraction of compact model parameters. This is mostly due to the fact
that there is always a physical difference between the test structure and the
actual transistor. Even though this thesis has shown that accurate
parameter determination is feasible using the dual base and dual collector
terminal test structure, I doubt that the method will extensively be utilized
by industry for extraction of parameters for compact BJT modeling.
However, the fact that DC measurements on the test structure yields
information about the collector layer, the extrinsic and intrinsic base
regions, the emitter region, the built-in potentials and the grading
coefficient of the pn-junctions renders it very suitable for process control
in

an

industrial

environment

where

automated

wafer

mapping

measurements are extensively used.


Looking into the future, an interesting continuation of Paper 7
would be to include the distributed b-e capacitance in the model. Thus, the
AC debiasing of the base-emitter junction may be calculated as a function
of frequency. The same effect is also a serious concern for RF applications
of deep submicron CMOS circuits, where the distributed gate resistance
and capacitance debias the gate electrode.
Regarding the test structure, the separation of the extrinsic and the
intrinsic base resistance could be improved. One idea would be to extract
the intrinsic part using the method proposed in [43] and then subtract this
resistance from the measured total base resistance. The result is then the
extrinsic base resistance. This would however require additional
measurements. Further on, only one method has been proposed for DC
extraction of the bias-dependent collector resistance RCV [44]. The result
from this method is difficult to interpret. The physical location of RCV (the
quasi-neutral part of the epitaxial collector) makes it difficult to assess
directly from measurements. Therefore, further work is required since
determination of RCV is highly needed for accurate modeling of future high
frequency BJTs.

44

Chapter 6. References

6. References
1.

SIA Roadmap, "http://www.semichips.org/", 2001.

2.

P. R. Gray and R. G. Meyer, "Analysis and Design of Analog


Integrated Circuits," John Wiley & Sons, Inc., 1993.

3.

C. C. McAndrew, J. A. Seitchik, D. F. Bowers, M. Dunn, M.


Foisy, I. Getreu, M. McSwain, S. Moinian, J. Parker, D. J.
Roulston, M. Schrter, P. van Wijnen and L. F. Wagner, "VBIC95,
the Vertical Bipolar Inter-Company Model," IEEE Journal of
Solid-State Circuits, vol. 31, p. 1476, 1996.

4.

J. C. J. Paasschens and W. J. Kloosterman, "The Mextram Bipolar


Transistor Model level 504," Philips Electronics, Unclassified NLUR 2000/811, June 2000.

5.

J. C. J. Paasschens, W. J. Kloosterman, R. J. Havens and H. C. de


Graaff, "Improved Modeling of Output Conductance and Cut-off
Frequency of Bipolar Transistors," In Proc. 2000 Bipolar/BiCMOS
Circuits and Technology Meeting, p. 62, 2000.

6.

H. Stbing and H. M. Rein, "A Compact Physical Large-Signal


Model for High-Speed Bipolar Transistors at High Current
Densities - Part I: One-Dimensional Model," IEEE Trans Electron
Dev., 34, p. 1741-1751, 1987.

45

DC Parameter Extraction and Modeling of Bipolar Transistors

7.

H. M. Rein and M. Schrter, "A Compact Physical Large-Signal


Model for High-Speed Bipolar Transistors at High Current
Densities - Part II: Two-Dimensional Model and Experimental
Results," IEEE Trans Electron Dev., 34, p. 1752-1761, 1987.

8.

T. H. Ning, R. D: Isaac, P. M. Solomon, D. D.-L. Tang, H.-N. Yu,


G. C. Feth, S. K. Wiedmann, "Self-Aligned Bipolar Transistors for
High-Performance and Low Power Delay VLSI," IEEE Trans
Electron Dev., ED-28, p. 1010, 1981.

9.

P. C. Hunt and M. P. Cooke, "Process HE: a highly advanced


trench isolated bipolar technology for analogue and digital
applications," In Proc. IEEE Custom Integrated Circuits Conf.,
22.2.1, 1988.

10.

W. Kaplan, J. Pejnefors, M. Linder, M. Sandn, T. E. Karlin, G.


Malm, S.-L. Zhang, J. V. Grahn and M. stling, "A Simplified
High-Speed Bipolar Process With Ti SALICIDE Metallization:
Implementation of In Situ P-Doped Polysilicon Emitter," Physica
Scripta, vol. T79, pp. 318-321, 1999.

11.

J. V. Grahn, J. Pejnefors, M. Sandn, S.-L. Zhang and M. stling,


"Characterisation of In Situ Phosphorus-Doped Polycrystalline
Silicon Films by Disilane-Based Low-Pressure Chemical Vapor
Deposistion," J. Electrochem Soc, 144, p.3952, 1997.

12.

L. Ailloud, J. de Pontacharra, G. Bartoletti, J. Kirtsch, G. Auvert


and A. Chantre, "A Performance Comparison Between 0.35 m
Self-Aligned and Quasi-Self-Aligned Double-Polysilicon Bipolar
Transistors," In Proc. European Semicond. Dev. Research Conf.,
p.412-415, 1997.

13.

J. M. Early, "Effects of Space-Charge Layer Widening in Junction


Transistors," Proceedings of the IRE, 11, p.1401, 1952.

14.

C. T. Kirk, "Theory of Transistor Cut-Off Frequency Roll-Off at


High Current Density," IRE Trans. Electron Dev., ED-9, p.164,
1962.

46

Chapter 6. References

15.

G.M. Kull, L. W. Nagel, S.-W. Lee, P. Lloyd, E. J. Prendergast


and H. Dirks, "A Unified Circuit Model for Bipolar Transistors
Including Quasi-Saturation Effects", IEEE Trans Electron Dev,
ED-32, p.1103-1113, 1985.

16.

Silvaco Virtual Wafer Fab software manual, Silvaco International


(1997).

17.

J. J. Ebers and J. L. Moll, "Large-Signal Behaviour of Junction


Transistors," Proc IRE, 42, p. 1761-1772, 1954.

18.

H. K. Gummel and H. C. Poon, "An Integral Charge Control


Model of Bipolar Transistors," The Bell System Technical Journal,
vol. 49, pp. 827-852, May-June 1970.

19.

J. R. Hauser, "The Effects of Distributed Base Potential on Emitter


Current Injection Density and Effective Base Resistance for Stripe
Transistor Geometries," IEEE Trans Electron Dev, ED-11, p. 238242, 1964.

20.

C. C. McAndrew and L. W. Nagel, "Early Effect Modeling in


SPICE," IEEE Journal of Solid State Circuits, 31, p.136-138,
1996.

21.

W. J. Kloosterman, J. C. J. Paasschens and R. J. Havens, "A


Comprehensive Bipolar Avalanche Multiplication Compact Model
for Circuit Simulation," In Proc. 2000 Bipolar/BiCMOS Circuits
and Technology Meeting, p. 172, 2000.

22.

W. M. C. Sansen and R. G. Meyer, Characterization and


Measurement of the Base and Emitter Resistances of Bipolar
Transistors, IEEE Journal of Solid-State Circuits, vol. SC-7, p.
492-498, 1972.

23.

J. Weng, J. Holz and T. F. Meister, New Method to Determine the


Base Resistance of Bipolar Transistors, IEEE Electron Device
Letters, vol. 13, p. 158-160, 1992.

24.

E. Dubois, P. H. Bricout and E. Robilliart, Extraction Method of


the Base Series Resistances in Bipolar Transistor in Presence of
Current Crowding, IEEE Journal of Solid-State Circuits, vol. 31,
p. 132-135, Jan. 1996.

47

DC Parameter Extraction and Modeling of Bipolar Transistors

25.

T.-Y. Chiu, P. K. Tien, J. Sung and T.-Y. M. Liu, "A New


Analytical Model and the Impact of Base Charge Storage on Base
Potential Distribution, Emitter Current Crowding and Base
Resistance," Proc. 1992 International Electron Device Meeting.
p.573, 1992.

26.

J. E. Lary and R. L. Anderson, "Effective Base Resistance of


Bipolar Transistors," IEEE Trans Electron Devices, ED-32,
p.2503, 1985.

27.

R. C. Taft and J. D. Plummer, An Eight-Terminal Kelvin Tapped


Bipolar Transistor for Extracting Parasitic Series Resistances,
IEEE Trans Electron Dev, vol. 38, p. 2139-2154, 1991.

28.

G. Massobrio and P. Antognetti, "Semiconductor Device Modeling


with SPICE," McGraw-Hill, 1993.

29.

M. Schrter, "A Survey of Present Compact Models for HighSpeed Bipolar Transistors," Frequenz, 47, p. 178-190, 1993.

30.

P. Ashburn, "Design and Realization of Bipolar Transistors," John


Wiley & Sons, Inc., 1988.

31.

T. Fuse and Y. Sasaki, "An analysis of small-signal and largesignal base resistances for submicrometer BJT's," IEEE Trans
Electron Dev, vol. 42, p. 534-539, 1995.

32.

H. N. Gosh, "A Distributed Model of the Junction Transistor and


its Application in the Prediction of the Emitter-Base Diode
Characteristic, Base Impedance, and Pulse Response of the
Device," IEEE Trans Electron Dev, ED-12, p.513, 1965.

33.

IC-Cap Manual, Hewlett Packard.

34.

F. Ingvarson and K. O. Jeppson, A New Direct Extraction


Algorithm for Intrinsic Gummel-Poon BJT Model Parameters, in
Proceedings of the International Conference on Microelectronic
Test Structures, p. 159-164, 1998.

35.

I. Getreu, "Modeling the Bipolar Transistor," Tektronix, Inc., 1976

36.

C. Xiaochong, J. McMacken, K. Stiles, P. Layman, J. J. Liou, A.


Oritz-Conde and S. Moinian, "Comparison of the new VBIC and
conventional Gummel-Poon bipolar transistor models ," IEEE
Trans Electron Dev, 47, p.427-433, 2000.

48

Chapter 6. References

37.

S. Lee, B. R. Ryum and S. W. Kang, A New Parameter Extraction


Technique for Small-Signal Equivalent Circuit of Polysilicon
Emitter Bipolar Transistors, IEEE Trans Electron Dev, 41, pp.
233-238, 1994.

38.

T. G. M. Kleinpenning, "Location of Low-Frequency Noise


Sources in Submicrometer Bipolar Transistors," IEEE Trans
Electron Dev, 39, p.1501, 1992.

39.

T. H. Ning and D. D. Tang, Method for Determining the Emitter


and Base Series Resistances of Bipolar Transistors, IEEE Trans
Electron Dev, ED-31, p. 409-412, 1984.

40.

B. Kulke and S. L. Miller, Accurate measurement of emitter and


collector series resistances in transistors, in Proc. IRE, 45, p. 90,
1957.

41.

L. J. Giacoletto, Measurement of Emitter and Collector Series


Resistances, IEEE Trans Electron Dev, ED-19, p. 692-693, 1972.

42.

D. MacSweeney, K. McCarthy, A. Mathewson, J. A. Power and S.


C. Kelly, Inclusion of Substrate Effects in the Flyback method for
BJT Resistance Characterisation,

in

Proceedings

of

the

International Conference on Microelectronic Test Structures, p.


194-199, 1999.
43.

M. Schrter, "Simulation and Modeling of the Low-Frequency


Base Resistance of Bipolar Transistors and its Dependence on
Current and Geometry," IEEE Trans Electron Dev, 38, p.538,
1991.

44.

J.-S. Park, A. Neugroschel, V. de la Torre and P. Zdebel,


"Measurement of Collector and Emitter Resistances in Bipolar
Transistors," IEEE Trans Electron Dev, 38, p.365, 1991.

49

DC Parameter Extraction and Modeling of Bipolar Transistors

50

Chapter 7. Summary of the Appended Papers

7. Summary of the Appended Papers


In this chapter, the main achievements presented in the appended
papers are briefly summarized. Further on, the contributions of the author
are specified.

Paper 1.

The Effect of Emitter Overetch and Base Implantation Tilt

on the Performance of Double Polysilicon Bipolar Transistors


The effect of the emitter window overetch in a double poly-Si BJT
process is investigated. The results indicate that an increased overetch
raises the maximum cut-off frequency fT,max on the expense of a reduced
maximum frequency of oscillation fMAX. The effect of the overetch is
increased when using a tilted geometry when performing the intrinsic base
implantation.
Contributions: The author participated in process development and
processing of the devices, performed the simulations and wrote the
manuscript.

51

DC Parameter Extraction and Modeling of Bipolar Transistors

Paper 2.

Extraction of Emitter and Base Series Resistances of

Bipolar Transistors from a Single DC Measurement


A new procedure for extraction of the base and emitter resistances
of a BJT is presented. The procedure only requires one measurement in
forward mode of operation on a dual base terminal test structure.
Contributions: The author designed and measured the double poly-Si test
structures. In addition, most of the writing of the manuscript was
performed by the author.

Paper 3.

On DC modeling of the base resistance in bipolar

transistors
A compact model of the intrinsic base resistance is presented. By
introducing a new model parameter, the existing model in e.g. the VBIC95
BJT model is improved so that both current crowding and base
conductivity modulation are considered. A scheme for extraction of the
base resistance parameters is also presented.
Contributions: The author came up with the idea, performed some of the
measurements and most of the writing of the manuscript.

Paper 4.

Extraction of the Intrinsic Base Region Sheet Resistance in

Bipolar Transistors
This paper presents a procedure that allows for extraction of the
zero bias intrinsic base sheet resistance, RS00 from pinched base
measurements. The extraction procedure considers base conductivity
modulation, current crowding and base width modulation (Early effect).
Contributions: The author performed some measurements, contributed in
the development of the method and assisted in writing the manuscript.

52

Chapter 7. Summary of the Appended Papers

Paper 5.

A New Test Structure for Parasitic Resistance Extraction of

Bipolar Transistors
By using an additional collector terminal, direct extraction of the
constant part of the collector resistance is enabled. Also, monitoring of the
Kirk effect using the additional collector terminal is demonstrated.
Contributions: The author came up with the idea, performed the design of
the double poly-Si test structures, all the simulations, some of the
measurements and wrote the manuscript.

Paper 6.

A Procedure for Characterizing the BJT Base Resistance

and Early Voltages Utilizing a Dual Base Transistor Test Structure


A simple way of extracting the bias-dependent Early voltage
parameters from pinched base measurements is presented. Separation of
the intrinsic and extrinsic parts of the base resistance is discussed.
Contributions: The author performed some measurements, contributed in
the development of the method and assisted in writing the manuscript.

Paper 7.

A Distributed Model of the Base - Emitter Junction

in Bipolar Transistors Including the Early Effect


A distributed model of the base-emitter junction is presented. The
model accounts for current crowding, base conductivity modulation and
base width modulation (the Early effect). In addition, a complete review of
previous work on distributed transistor models are presented.
Contributions: The author came up with the idea, performed all the
calculations and measurements. Further on, the author wrote the
manuscript.

53

DC Parameter Extraction and Modeling of Bipolar Transistors

54