EE669: VLSI TECHNOLOGY

Autumn Semester Graduate Course

2014-2015 Session
by
Arun N. Chandorkar
Emeritus Fellow Professor
Department of Electrical Engineering
Indian Institute of Technology, Bombay
Powai, Mumbai-400076,India
E-Mail: anc@ee.iitb.ac.in

Course Syllabus
Crystal Growth. Clean rooms. Solid State diffusion modelling and
technology. Ion Implantation modelling, technology and damage annealing,
characterization of Impurity profiles. Oxidation: Kinetics of Silicon dioxide
growth both for thick, thin and ultrathin films. Oxidation technologies in
VLSI and ULSI, Characterization of oxide films, High k and low k
dielectrics for ULSI. Lithography: Photolithography, E-beam lithography
and newer lithography techniques for VLSI/ULSI; Mask generation.
Chemical Vapour Deposition techniques: CVD techniques for deposition of
polysilicon, silicon dioxide, silicon nitride and metal films, Epitaxial growth
of silicon, modelling and technology. Metal film deposition: Evaporation and
sputtering techniques. Failure mechanisms in metal interconnects, Multilevel metallisation schemes. Plasma and Rapid Thermal Processing:
PECVD, Plasma etching and RIE techniques, RTP techniques for annealing,
growth and deposition of various films for use in ULSI.
Process integration for NMOS, CMOS ICs.
Introduction to Silicon Solar Cell technologies.

Examination Schedules
Autumn Semester Exam Dates:
Quiz/Cum Test : 4th Week in August 2014
Test -1
: 2nd Week in October 2014
Mid-Semester Exam: September 2014( Institute Time table
or as decided by us)
End-Semester Exam: Mid- November 2014
All Examinations except
Mid-semester and End semester ones will be from
8.45 to 10.45 PM slot in
GG 001 and GG 002
Home assignments/Project submission as per announced
dates , time to time.

Grading Policy :
Total of 4 Exams:
Quiz, Test, Mid-Semester and End-Semester
Weightage in % : 8 +8+20+ 50 = 86
AND some Design Project/Problem Assignments
Weightage: = 15%
PLUS 7 % Total bonus on
Attendance ( 80 % Min), Sincerity, Project preparation
and excellence in Exams.
TOTAL

: 100 % ( 108 in actual number)

Micro to Nano
A Journey into Integrated Circuit Technology
Lecture No 1
EE669:VLSITECHNOLOGY
by
ArunN.Chandorkar
EmeritusFellowProfessor
DepartmentofElectricalEngineering
IndianInstituteofTechnology,Bombay
Powai,Mumbai400076,India
EMail:anc@ee.iitb.ac.in

History of Electronic Devices

2000

Low Power
High speed
High integration

ULSI
VLSI

70
60
50
30
20
10
1900

LSI

LSI

Si-MOSFET
IC
IC
bipolar 1st Transistor
MOSFET
MISFET

CMOS
10 years
30 years

Low Power
High speed
High integration

Silicon Technology
High Integration

Solid-State Circuits
High reliability

Transistor
Concept

Low Power
20 years

Triode
Diode

Vacuum tube

1st Electronic circuits

IwaiHiroshi

1906: Vacuum Tube : Triode

Lee De Forest

IwaiHiroshi

J. E. LILIENFELD
DEVICES FOR CONTROLLED ELECTRIC CURRENT

Filed March 28, 1928

J.E.LILIENFELD

IwaiHiroshi

1947: 1st transistor

J. Bardeen, W. Bratten,
W. Shockley

IwaiHiroshi

First Bipolar Ge Transistor

1958: 1st Integrated Circuit

Jack S. Kilby

IwaiHiroshi

1958 - Integrated circuit invented

September12th1958JackKilbyat
Texasinstrumenthadbuilta
simpleoscillatorICwithfiveintegrated
components(resistors,capacitors,
distributedcapacitorsandtransistors)
In2000theimportanceoftheICwas
recognizedwhenKilbysharedtheNobel
prizeinphysicswithtwoothers.Kilby
wassitedbytheNobelcommittee"forhis
partintheinventionoftheintegrated
circuit

asimpleoscillatorIC

UniversityofsouthernAlabama

1959: 1st Planar Integrated

Circuit

Robert N. Noyce

IwaiHiroshi

1960:FirstMOSFET
byD.KahngandM.Atalla

Top View

e
t
a
G

l
A

Si

e
c
r
u
So

Al

n
i
a
Dr
Si

SiO2
Si
Si/SiO2 Interface is
extraordinarily good

First Computer Eniac: made of huge number of vacuum tubes 1946

Big size, huge power, short life time filament
dreamed of replacing vacuum tube with solid-state device
Today's pocket PC
made of
semiconductor has
much higher
performance with
extremely low power
consumption

IwaiHiroshi

1970,71:1stgenerationofLSIs
DRAMIntel1103

MPUIntel4004

In2012
MostRecentSDCard
128GB(Byte)
=128GX8bit
=1T(Tera)bit
1T=1012= Trillion
WorldPopulation 7Billion
BrainCell 10 100Billion
StarsinGalaxy 100Billion
IwaiHiroshi

128GB=1Tbit
2.4cm X 3.2cm X 0.21cm
Volume 1.6cm

Weight 2g

Voltage 2.73.6V
OldVacuumTube
5cmX5cmX10cm,100g,50W
Whatarevolume,weight,powerconsumptionfor
1Tbit

IwaiHiroshi

OldVacuumTube
5cmX5cmX10cm

PinganIntenational
FinanceCenter
Shanghai,China
(Year2016)

Volume=(5cmX10,000)X(5cmX10,000)
X(10cmX10,000)
=0.5kmX0.5kmX1km
IndianTower
Mumbai,India
(Year2016)

BurjiKhalifa
Dubai,UAE
(Year2010)

500m

1,000m

828m

700m

700m

Iwai
Hiroshi

1Tbit=10,000X10,000X10,000bit

1Tbit

OldVacuumTube
50W
NuclearPowerGenerator
1MkW=1BW

1Tbit=1012bit
Power=0.05kWX1012=50TW
Weneed50,000NuclearPowerPlantforjustone
128GBmemory
InJapanwehaveonly54Nuclear
PowerGenerator
LastsummerTokyoElectricPower
Company(TEPCO)cansupplyonly
55BW.
Weneed1000TEPCOjustone128
GBmemory
Imaginehowmanymemoriesareusedin
Iwai
theworld!
Hiros

Soprogressofintegrated
circuitsisextremely
importantforpowersaving.

Brain:IntegratedCircuits
Ear,Eye Sensor
Mouth RF/Optodevice
Stomach PVdevice
Hands,Legs Powerdevice
IwaiHiroshi

Nearfuturesmartsocietyhastotreathugedata.

DemandtohighperformanceandlowpowerCMOSbecom
muchmorestronger.

IwaiHiroshi

SemiconductorDeviceMarketwillgrow5
timesin12years,eventhough,itisvery
maturedmarket!!
2011
300BUSD

2025
1,500BUSD

Gartner:ByK.Kim,CSTIC2012

1970,71: 1st generation of LSIs

DRAM Intel 1103

MPU

Intel 4004

INTEL

Today, silicon device is the indispensable and

most important devices for our human society.
Everything has to be controlled by Si device.
Si realized extremely high-frequency (speed)
operation with extremely low cost, low power,
small size, high reliability.
Todays IT -- such as internet, i-mode, cellular
phone, GPS navigation, game machine,
Entertainment robot could not be realized
Without Si integrated circuit development.

INTEL

INTEL

1900Electronicsstarted.
Device:Vacuumtube
Devicefeaturesize:Severalcm
MajorAppl.:Amplifier(Radio,TV,Wirelessetc.)
TechnologyRevolution
1970MicroElectronicsstarted.
Device:SiMOSintegratedcircuits
Devicefeaturesize:10m
MajorAppl.:Digital(Computer,PC,etc.)
TechnologyRevolution

2000NanoElectronicsstarted.
Device:Still,SiCMOSintegratedcircuits
Devicefeaturesize:100nm
MajorAppl.:Digital(processor,cellphone,etc.)
TechnologyRevolution??
Maybe,justevolutionandinnovation!
Butgreatevolutionorinnovations!
andsomanyinnovations!

Now,2014NanoElectronicscontinued.
Device:Still,SiCMOSintegratedcircuits
Devicefeaturesize:around10nm
MajorAppl.:StillDigital(processor,cellphone,etc.)
Stillevolutionandinnovation.

Goal: 1TIPS by 2010

1000000
100000

Pentium 4 Architecture

10000

Pentium Pro Architecture

MIPS

1000

Pentium Architecture

100
10
1

8086

286

386

486

0.1
0.01
1970

1980

1990

2000

2010

How do you get there?

INTEL

Technology Scaling
SOURCE Xj

GATE

DRAIN

SOURCE

GATE

BODY

DRAIN

Tox
BODY

Leff

Dimensionsscaledownby Doublestransistordensity
30%
Oxidethicknessscalesdown Fastertransistor,higher
performance
Vdd&Vtscaling

Loweractivepower

Technology has scaled well, will it in the future?

Scaling Evolution

IwaiHiroshi

MICRO to NANO Journey Milestones

J.L.Hoyt
MIT

Scaling:
Importance of Downsizing

Downsizing:
Capacitance reduction
High integration

Power reduction
Speed increase
Function increase
Parallel processing
Speed increase
IwaiHiroshi

Demand for future VLSI:

Much higher performance
Much lower power consumption
Thus, downsizing of Si devices is
the most important and critical issue.
IwaiHiroshi

Prediction of Scaling limit

Vacuum tube era even m size could not be imagined
Since Si IC started
Period
Expected
Cause
limit(size)
Late 1970s 1m:
Early 1980s 0.5m:
Early 1980s 0.25m:
Late 1980s 0.1m:
Today
Today

50nm:
10nm:

SCE
S/D resistance
Direct-tunneling of gate SiO2
0.1m brick wall(various)
Red brick wall (various)
Fundamental?

Transistor Integration Capacity

Transistors (Million)

1000

1 Billion

100
10
1
0.1
0.01
0.001
10

0.5

0.25

0.13

0.07

Technology ( )

On track for 1B transistor integration capacity

INTEL

J.L.Hoyt
MIT

Limits of Moores Law?

Growth expected until 30 nm gate

length (currently: 180 nm)
size halved every 18 mos. - reached
in
2001 + 1.5 log2((180/30)2) = 2009
what then?
Paradigm shift needed in fabrication
process

Technological Background of the Moores Law

To accommodate this change, the size of the silicon

wafers on which the integrated circuits are fabricated
have also increased by a very significant factor from
the 2 and 3 in diameter wafers to the 8 in (200 mm) and
12 in (300 mm) diameter wafers
The latest catch phrase in semiconductor technology (as
well as in other material science) is nanotechnology
usually referring to GaAs devices based on quantum
mechanical phenomena
These devices have feature size (such as film thickness,
line width etc) measured in nanometres or 10-9 metres

Recurring Costs
Variable Cost = {Cost of (Die + Die test + packaging)}/ Final Test Yield

Cost of Die = {Cost of wafer}/[ Dies per wafer x Die Yield]

x [wafer diameter/2] 2

wafer diameter

Die per wafer =---------------------------------- ---------------------------

Die area

1.414 x Die area

Dieyield=[1+(defectsperunitareaxDiearea)/ ]

Yield Example

Example

wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,

= 3 (measure of manufacturing process complexity)
252 dies/wafer (remember, wafers round & dies square)
die yield of 16%
252 x 16% = only 40 dies/wafer die yield !

Die cost is strong function of die area

proportional to the third or fourth power of the die area

PROCESS STEPS

Is Transistor a Good Switch?

I=0

I0

On
I = 1ma/u

I=

I=0

I0

Off
I=0

I0
Sub-threshold Leakage