Figure 1 : (a) SRAM wafer average access time versus L(eff).

(b) L(eff) versus SRAM density logarithmic plot.

Figure 2 : A general schematic of a SRAM memory cell.
Figure 3 : Various configuration of CMOS SRAM cells. (a) Six-transistor full
CMOS. (b) Four transistor with R-load NMOS. (c) Dual-port with double-ended
access (d) Content-addressable memory (CAM).
Figure 4 : (a) A typical SRAM basic organization schematic.
Figure 4 : (b) The storage cell array details.
 (a) (b)
Figure 5 : Six-transistor CMOS SRAM cell. (a) Schematic
diagram.
Figure 6: Various SRAM circuit elements. (a) Static row decoder.
(b) Dynamic row decoder. (c) Simple write circuitry (d) Inverter
amplifier (e) Differential sense amplifier.
 (a) (b)
Figure 7 : (a) Three-transistor (3-T) DRAM cell (b) One
transistor (1-T) DRAM cell.
Figure 8 : (a) Basic one-transistor storage cell with cross-coupled
latch sense amplifier (b) The associated timing diagram (c) A
DRAM differential sense amplifier showing dummy cell structure.
 (a)

(b)

Figure 9 : (a) A 64 kb DRAM sense amplifier circuit showing

combination open and folded bit lines. (b) The associated timing
diagram and operating sequence.
 (a)
Figure 10 : (a)Block diagram of 1 MB DRAM (NEC PD421000).
 (b)

Figure 10 : (b) Chip layout

 (c)

Figure 10 : (c) Cross-section of one-transistor memory cell.

Figure11 : Access timing for a 1 Mb DRAM (NEC PD421000-seriess)
Figure 12 : Block diagram of NEC PD42273 dual-port graphics
buffer.
Figure 13 : ROM cell structure. (a) NOR array (b) NAND array.
Figure 14 : Block diagram of 16Mb CMOS ROM NEC
 (a)

Figure 15 : 1Mb CMOS UV EPROM Fujitsu MBM27C1028 (a)

Block diagram.
 (b)

Figure 15 : 1Mb CMOS UV EPROM Fujitsu MBM27C1028 (b)

Programming waveforms.
 (b)
(a)

(c)
Figure 16: A 1 Mb CMOS EPROM. (a) Sense amplifier circuit structure. (b)
Memory cell array structure. (c) Threshold monitoring program (TMP) circuit.
 Figure 17 : (a) A four-transistor memory cell with read and
program transistors implanted separately. (b) Four-transistor
memory cell with differential sensing scheme.
 (a) (b)

Figure 18 : A +5V only Inmos EAROM. (a) Schematic cross-

section. (b) Functional block diagram.
 (a) (b)

Figure 19 : Flash memory cell structures. (a) NOR EEPROM that

requires one transistor for every contact. (b) NAND EEPROM
with 16 serially connected memory transistors per bit-line contact.
Figure 20: A 256K CMOS flash memory Intel chip block
diagram.
Figure 21: A block diagram of the AMD 4 Mb 5 V-only flash
memory.
Figure 22: Block diagram of Intel 8Mb flash EPROM