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VLSI design UNIT TEST - I DATE: 02.082010 Part-A 5 2=10 1. Draw the design flow for production of mask layout. 2. Explain scaling and its types? 3. Give the final equation of resistive load inverter as VOH,VOL,V1L,V1H. 4. Explain PHL, PLH with its equation? 5. Write about the switching power dissipation in cmos?
VLSI design UNIT TEST - I DATE: 02.082010 Part-A 5 2=10 1. Draw the design flow for production of mask layout. 2. Explain scaling and its types? 3. Give the final equation of resistive load inverter as VOH,VOL,V1L,V1H. 4. Explain PHL, PLH with its equation? 5. Write about the switching power dissipation in cmos?
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VLSI design UNIT TEST - I DATE: 02.082010 Part-A 5 2=10 1. Draw the design flow for production of mask layout. 2. Explain scaling and its types? 3. Give the final equation of resistive load inverter as VOH,VOL,V1L,V1H. 4. Explain PHL, PLH with its equation? 5. Write about the switching power dissipation in cmos?
Copyright:
Attribution Non-Commercial (BY-NC)
Verfügbare Formate
Als DOC, PDF, TXT herunterladen oder online auf Scribd lesen
02.082010 Part-A 5*2=10 1. Draw the design flow for production of mask layout. 2. Explain scaling and its types? 3. Give the final equation of resistive load inverter as VOH,VOL,V1L,V1H. 4. Explain PHL, PLH with its equation? 5. Write about the switching power dissipation in cmos? Part – B 4*10=40 1. Explain the process of LOCOS and multilevel interconnect? 2. Describe the structure and operation of n-channel MOSFET? 3. Explain MOSFET scaling and small geomentry effects? 4. Explain the voltage tranfer characteristics of nMOS inverter? 5. Brifly explain the CMOS inverter? 6. Explain Fabrication process flow?
GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE
SUB: VLSI DESIGN UNIT TEST – I DATE: 02.082010 Part-A 5*2=10 6. Draw the design flow for production of mask layout. 7. Explain scaling and its types? 8. Give the final equation of resistive load inverter as VOH,VOL,V1L,V1H. 9. Explain PHL, PLH with its equation? 10.Write about the switching power dissipation in cmos? Part – B 4*10=40 7. Explain the process of LOCOS and multilevel interconnect? 8. Describe the structure and operation of n-channel MOSFET? 9. Explain MOSFET scaling and small geomentry effects? 10.Explain the voltage tranfer characteristics of nMOS inverter? 11.Brifly explain the CMOS inverter? 12.Explain Fabrication process flow?
GOVERNMENT COLLEGE OF TECHNOLOGY, COIMBATORE
SUB: VLSI DESIGN UNIT TEST – I DATE: 02.082010 Part-A 5*2=10 11.Draw the design flow for production of mask layout. 12.Explain scaling and its types? 13.Give the final equation of resistive load inverter as VOH,VOL,V1L,V1H. 14.Explain PHL, PLH with its equation? 15.Write about the switching power dissipation in cmos? Part – B 4*10=40 13.Explain the process of LOCOS and multilevel interconnect? 14.Describe the structure and operation of n-channel MOSFET? 15.Explain MOSFET scaling and small geomentry effects? 16.Explain the voltage tranfer characteristics of nMOS inverter? 17.Brifly explain the CMOS inverter? 18.Explain Fabrication process flow?