Addition of Unsigned Numbers

2102581 Digital Circuit Design

Chapter 5
Combinational Circuit Design (cont.)

Suree Pumrin, Ph.D.

1
Figure 5.2 (a), (b) Half-adder. 2

Figure 5.2 (c), (d) Half-adder.

Figure 5.4 (a), (b) Full-adder.

3 4
 LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;

ARCHITECTURE LogicFunc OF fulladd IS

BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
Figure 5.4 (c) Full-adder circuit.
Figure 5.22. VHDL code for the full-adder.
5 6

ci s si
s HA c
xi
HA c ci + 1
yi xn –1 yn – 1 x1 y1 x0 y0

(a) Block diagram

c1
cn FA cn ” 1 c2 FA FA c0
ci
si
xi
yi
sn – 1 s1 s0
ci + 1 MSB position LSB position

(b) Detailed diagram Figure 5.6. An n-bit ripple-carry adder.

Figure 5.5. A decomposed implementation of the full-adder circuit.

7 8
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY adder4 IS LIBRARY ieee ;

PORT ( Cin : IN STD LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
USE ieee.std_logic_1164.all ;
y3, y2, y1, y0 : IN STD_LOGIC ;
s3, s2, s1, s0 : OUT STD_OGIC ;
Cout : OUT STD_LOGIC ) ;
PACKAGE fulladd_package IS
END adder4 ; COMPONENT fulladd
ARCHITECTURE Structure OF adder4 IS
PORT ( Cin, x, y : IN STD_LOGIC ;
SIGNAL c1, c2, c3 : STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ;
COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;
END COMPONENT ;
s, Cout : OUT STD_LOGIC ) ; END fulladd_package ;
END COMPONENT ;
BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; Figure 5.24. Declaration of a package.
stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
9 10
Figure 5.23 VHDL code for a four-bit adder.

LIBRARY ieee ; LIBRARY ieee ;

USE ieee.std_logic_1164.all ; USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ; USE work.fulladd_package.all ;

ENTITY adder4 IS ENTITY adder4 IS

PORT ( Cin : IN STD_LOGIC ; PORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y3, y2, y1, y0 : IN STD_LOGIC ; S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;
s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ;
Cout : OUT STD_LOGIC ) ; END adder4 ;
END adder4 ;
ARCHITECTURE Structure OF adder4 IS
ARCHITECTURE Structure OF adder4 IS SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
SIGNAL c1, c2, c3 : STD_LOGIC ; BEGIN
BEGIN stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;
stage3: fulladd PORT MAP ( END Structure ;
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
Figure 5.26. A four-bit adder defined using multibit signals.
11 12
Figure 5.25. A different way of specifying a four-bit adder.
 LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY ieee ; USE ieee.std_logic_signed.all ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ; ENTITY adder16 IS
PORT ( Cin : IN STD_LOGIC ;
ENTITY adder16 IS X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
PORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; Cout, Overflow : OUT STD_LOGIC ) ;
END adder16 ; END adder16 ;

ARCHITECTURE Behavior OF adder16 IS ARCHITECTURE Behavior OF adder16 IS

BEGIN SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;
S <= X + Y ; BEGIN
END Behavior ; Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;
Figure 5.27. VHDL code for a 16-bit adder.
Figure 5.28. The 16-bit adder from Figure 5.27 with carry and
13 overflow signals. 14

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;

ENTITY adder16 IS ENTITY adder16 IS

PORT ( Cin : IN STD_LOGIC ; PORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ;
X, Y : IN SIGNED(15 DOWNTO 0) ; S : OUT INTEGER RANGE -32768 TO 32767 ) ;
S : OUT SIGNED(15 DOWNTO 0) ; END adder16 ;
Cout, Overflow : OUT STD_LOGIC ) ;
END adder16 ; ARCHITECTURE Behavior OF adder16 IS
BEGIN
ARCHITECTURE Behavior OF adder16 IS S <= X + Y ;
SIGNAL Sum : SIGNED(16 DOWNTO 0) ; END Behavior ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ; Figure 5.30. The 16-bit adder from Figure 5.27 using INTEGER signals.

Figure 5.29. Use of the arithmetic package.

15 16
 LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY BCD IS
PORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ;
END BCD ;

ARCHITECTURE Behavior OF BCD IS

SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ;
SIGNAL Adjust : STD_LOGIC ;
BEGIN
Z <= ('0' & X) + Y ;
Adjust <= '1' WHEN Z > 9 ELSE '0' ;
S <= Z WHEN (Adjust = '0') ELSE Z + 6 ;
END Behavior ;

Figure 5.38. Functional simulation of the VHDL code in Figure 5.37.

Figure 5.37. VHDL code for a one-digit BCD adder.

17 18

Multiplexers
LIBRARY ieee ;
s USE ieee.std_logic_1164.all ;
s f
w0 0 w0
f 0 ENTITY mux2to1 IS
w1 1 1 w1 PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
(a) Graphical symbol (b) Truth table END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
w0 w0 WITH s SELECT
f <= w0 WHEN '0',
s f s w1 WHEN OTHERS ;
END Behavior ;
w1 w1 f

(c) Sum-of-products circuit (d) Circuit with transmission gates Figure 6.27. VHDL code for a A 2-to-1 multiplexer.
Figure 6.1. A 2-to-1 multiplexer. 19 20
 s0
s1 s1 s0 f
LIBRARY ieee ;
w0 00 w0
w1
0 0 USE ieee.std_logic_1164.all ;
01 0 1 w1
w2 f
10 w2
1 0
w3 11
1 1 w3 ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
(a) Graphic symbol (b) Truth table s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
s0 END mux4to1 ;
w0
s1 ARCHITECTURE Behavior OF mux4to1 IS
BEGIN
w1
WITH s SELECT
f f <= w0 WHEN "00",
w2 w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
w3
END Behavior ;

(c) Circuit

Figure 6.28. VHDL code for a 4-to-1 multiplexer (Part a).

Figure 6.2. A 4-to-1 multiplexer. 21 22

s0
s1

LIBRARY ieee ; w0
USE ieee.std_logic_1164.all ;
PACKAGE mux4to1_package IS w3
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; w4 s2
s3
f : OUT STD_LOGIC ) ;
w7
END COMPONENT ;
END mux4to1_package ; f

w8
• Figure 6.4 shows how a 16-to-1
w11
multiplexer is constructed with five 4-to-1
multiplexers.
w12 • Figure 6.29 presents VHDL code for this
circuit, using the mux4to1 component.
Figure 6.28. VHDL code for a 4-to-1 multiplexer (Part b). w15

23
Figure 6.4. A 16-to-1 multiplexer. 24
1 LIBRARY ieee ; Decoders
2 USE ieee.std_logic_1164.all ;
2 LIBRARY work ;
4 USE work.mux4to1_package.all ; w0
En w1 w0 y0 y1 y2 y3
y0
1 0 0 1 0 0 0 w1
5 ENTITY mux16to1 IS
1 0 1 0 1 0 0
6 PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; 1 1 0 0 0 1 0
7 s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; 1 1 1 0 0 0 1 y1
8 f : OUT STD_LOGIC ) ; 0 x x 0 0 0 0
9 END mux16to1 ; (a) Truth table
y2
10 ARCHITECTURE Structure OF mux16to1 IS
11 SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
12 BEGIN w0 y0
w1 y1 y3
13 Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;
y2 En
14 Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;
En y3
15 Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; (c) Logic circuit
16 Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;
17 Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; (b) Graphical symbol
18 END Structure ;

Figure 6.16. A 2-to-4 decoder.

Figure 6.29. Hierarchical code for a 16-to-1 multiplexer.
25 26

LIBRARY ieee ; Encoders

USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; w3 w2 w1 w0 y1 y0 z
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; 0 0 0 0 d d 0
END dec2to4 ; 0 0 0 1 0 0 1
0 0 1 x 0 1 1
ARCHITECTURE Behavior OF dec2to4 IS 0 1 x x 1 0 1
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; 1 x x x 1 1 1
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111", Figure 6.24. Truth table for a 4-to-2 priority encoder.
"0000" WHEN OTHERS ;
END Behavior ;

Figure 6.30. VHDL code for a 2-to-4 binary decoder. 27 28

 LIBRARY ieee ;
USE ieee.std_logic_1164.all ; LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS USE ieee.std_logic_unsigned.all ;
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; ENTITY compare IS
z : OUT STD_LOGIC ) ; PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END priority ;
END compare ;

ARCHITECTURE Behavior OF priority IS ARCHITECTURE Behavior OF compare IS

BEGIN BEGIN
y <= "11" WHEN w(3) = '1' ELSE AeqB <= '1' WHEN A = B ELSE '0' ;
"10" WHEN w(2) = '1' ELSE AgtB <= '1' WHEN A > B ELSE '0' ;
"01" WHEN w(1) = '1' ELSE AltB <= '1' WHEN A < B ELSE '0' ;
"00" ; END Behavior ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END Behavior ;
Figure 6.34. VHDL code for a four-bit comparator.
Figure 6.32. VHDL code for a priority encoder.
29 30

LIBRARY ieee ;
• In addition to the FOR GENERATE statement, VHDL provides another
USE ieee.std_logic_1164.all ;
type of generate statement called IF GENERATE.
USE work.mux4to1_package.all ;
• Figure 6.37 illustrates the use of both types of generate statements.
ENTITY mux16to1 IS
• The code shown is a hierarchical description of the 4-to-16 decoder given
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
in Figure 6.18, using five instances of the dec2to4 component defined in
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Figure 6.30.
f : OUT STD_LOGIC ) ;
END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 IS

SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;
END GENERATE ; Figure 6.18. A 4-to-16 decoder
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; built using a decoder tree.
END Structure ;

Figure 6.36. Code for a 16-to-1 multiplexer using a generate statement.

31 32
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec4to16 IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; ENTITY mux2to1 IS
En : IN STD_LOGIC ; PORT ( w0, w1, s : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ; f : OUT STD_LOGIC ) ;
END dec4to16 ; END mux2to1 ;
ARCHITECTURE Structure OF dec4to16 IS
ARCHITECTURE Behavior OF mux2to1 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; BEGIN
En : IN STD_LOGIC ; PROCESS ( w0, w1, s )
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; BEGIN
END COMPONENT ; IF s = '0' THEN
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; f <= w0 ;
BEGIN ELSE
G1: FOR i IN 0 TO 3 GENERATE f <= w1 ;
Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) );
END IF ;
G2: IF i=3 GENERATE
Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ; END PROCESS ;
END GENERATE ; END Behavior ;
END GENERATE ;
END Structure ;
Figure 6.38. A 2-to-1 multiplexer specified using an if-then-else statement
Figure 6.37. Hierarchical code for a 4-to-16 binary decoder. 33 34

LIBRARY ieee ;
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_1164.all ; ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
ENTITY mux2to1 IS y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
PORT ( w0, w1, s : IN STD_LOGIC ; z : OUT STD_LOGIC ) ;
f : OUT STD_LOGIC ) ; END priority ;
END mux2to1 ;
ARCHITECTURE Behavior OF priority IS
BEGIN
ARCHITECTURE Behavior OF mux2to1 IS
PROCESS ( w )
BEGIN BEGIN
PROCESS ( w0, w1, s ) IF w(3) = '1' THEN
BEGIN y <= "11" ;
f <= w0 ; ELSIF w(2) = '1' THEN
IF s = '1' THEN y <= "10" ;
f <= w1 ; ELSIF w(1) = '1' THEN
END IF ; y <= "01" ;
ELSE
END PROCESS ;
y <= "00" ;
END Behavior ; END IF ;
END PROCESS ;
z <= '0' WHEN w = "0000" ELSE '1' ;
Figure 6.39. Alternative code for a 2-to-1 multiplexer END Behavior ;
using an if-then-else statement. 35 Figure 6.40. A priority encoder specified using the if-then-else statement. 36
 LIBRARY ieee ; LIBRARY ieee ;
USE ieee.std_logic_1164.all ; USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
ENTITY mux2to1 IS
En : IN STD_LOGIC ;
PORT ( w0, w1, s : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
f : OUT STD_LOGIC ) ; END dec2to4 ;
END mux2to1 ;
ARCHITECTURE Behavior OF dec2to4 IS
ARCHITECTURE Behavior OF mux2to1 IS BEGIN
BEGIN PROCESS ( w, En )
PROCESS ( w0, w1, s ) BEGIN
IF En = '1' THEN
BEGIN
CASE w IS
CASE s IS WHEN "00" => y <= "1000" ;
WHEN '0' => WHEN "01" => y <= "0100" ;
f <= w0 ; WHEN "10" => y <= "0010" ;
WHEN OTHERS => WHEN OTHERS => y <= "0001" ;
f <= w1 ; END CASE ;
END CASE ; ELSE
END PROCESS ; y <= "0000" ;
END IF ;
END Behavior ;
END PROCESS ;
END Behavior ;
Figure 6.45. A case statement that represents a 2-to-1 multiplexer. 37 Figure 6.46. A process statement that describes a 2-to-4 binary decoder. 38

Table 6.1. The functionality of the 74381 ALU. ARCHITECTURE Behavior OF alu IS
BEGIN
PROCESS ( s, A, B )
BEGIN
CASE s IS
WHEN "000" =>
F <= "0000" ;
WHEN "001" =>
F <= B - A ;
WHEN "010" =>
F <= A - B ;
WHEN "011" =>
F <= A + B ;
WHEN "100" =>
LIBRARY ieee ; F <= A XOR B ;
USE ieee.std_logic_1164.all ; WHEN "101" =>
USE ieee.std_logic_unsigned.all ; F <= A OR B ;
ENTITY alu IS WHEN "110" =>
PORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ; F <= A AND B ;
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; WHEN OTHERS =>
F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; F <= "1111" ;
END alu ; END CASE ;
END PROCESS ;
END Behavior ;
Figure 6.48. Code that represents the functionality of the 74381 ALU chip (Part a).
39 Figure 6.48. Code that represents the functionality of the 74381 ALU chip (Part b). 40