This thesis presents the analysis and simulation of variable gain bandwidth product (GBP) amplifiers. It was previously explored that current feedback amplifier can provide variable GBP. This does not apply to the all encountered feedback configurations. There are six possible combinations of the amplifying elements and the feedback configurations where we can find constant bandwidth (“Novel Design Approaches for Low Voltage CMOS Current Feedback and Transconductance Feedback Amplifier” -by Md. Ataur Rahman Sarker). We carried on our research on those configurations to design practical amplifiers with variable GBP.
In this thesis paper firstly we discussed on the recent developments on the field of our interest. Then we overviewed the theories concerning amplifiers that followed by our works where we explored to the way of our interest.
Then we tried to simulate the circuits which were built by the theories we derived. After that we discussed the results obtained form the simulation. Then finally we concluded with the suggestions for the future works based on our research.

Attribution Non-Commercial (BY-NC)

Als PDF, TXT **herunterladen** oder online auf Scribd lesen

463 Aufrufe

This thesis presents the analysis and simulation of variable gain bandwidth product (GBP) amplifiers. It was previously explored that current feedback amplifier can provide variable GBP. This does not apply to the all encountered feedback configurations. There are six possible combinations of the amplifying elements and the feedback configurations where we can find constant bandwidth (“Novel Design Approaches for Low Voltage CMOS Current Feedback and Transconductance Feedback Amplifier” -by Md. Ataur Rahman Sarker). We carried on our research on those configurations to design practical amplifiers with variable GBP.
In this thesis paper firstly we discussed on the recent developments on the field of our interest. Then we overviewed the theories concerning amplifiers that followed by our works where we explored to the way of our interest.
Then we tried to simulate the circuits which were built by the theories we derived. After that we discussed the results obtained form the simulation. Then finally we concluded with the suggestions for the future works based on our research.

Attribution Non-Commercial (BY-NC)

Als PDF, TXT **herunterladen** oder online auf Scribd lesen

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Gain Bandwidth Product Amplifiers

By

M. Maidul Islam

Tasmia Tahmid

Sayeda Salma Nahar

A THESIS

SUBMITTED TO

MILITARY INSTITUTE OF SCIENCE AND TECHNOLOGY

THE DEGREE OF BACHELOR OF SCIENCE

AND COMMUNICATION ENGINEERING

MIST, DHAKA

DECEMBER, 2006

ii

Declaration

We declare that this thesis entitled “Analysis and Simulation of

Variable Gain Bandwidth product Amplifiers” is a piece of original research

work. This work has not been presented any where before for the award of

any degree or diploma.

………………………….

M. Maidul Islam

………………………. St. No - 200316029

Assistant professor Hamidur Rahman

.......................................

Tasmia Tahmid

St. No – 200316037

.......................................

Sayeda Salma Nahar

St. No – 200316021

iii

Abstract

This thesis presents the analysis and simulation of variable gain

bandwidth product (GBP) amplifiers. It was previously explored that current

feedback amplifier can provide variable GBP. This does not apply to the all

encountered feedback configurations. In the thesis paper “Novel Design

Approaches for Low–Voltage CMOS Current Feedback and

Transconductance Feedback Amplifier” (-by Md. Ataur Rahman Sarker) we

found some tables (chapter – 2, page - 25) that directed to the way of our

exploration. There we found that there are six possible combinations of the

amplifying elements and the feedback configurations where we can find

constant bandwidth. Then we carried on our research on those configurations

to design practical amplifiers with variable GBP.

the field of our interest. Then we overviewed the theories concerning

amplifiers that followed by our works where we explored to the way of our

interest.

Then we tried to simulate the circuits which were built by the theories

we derived. After that we discussed the results obtained form the simulation.

Then finally we concluded with the suggestions for the future works

based on our research.

iv

Acknowledgement

professor Hamidur Rahman and assistant professor Md. Ataur Rahman

Sarkar for giving us the opportunity to successfully complete the thesis and

proper guidance throughout our research works.

for giving us all academic supports during our thesis.

was highly essential to pursue our thesis.

Lastly but not the least we would like to thank our parents for their

moral support and encouragement.

v

Contents

Declaration …………………………………………………………… ii

Abstract …………………………………………………………… iii

Acknowledgement ............................................................................................ iv

Contents ............................................................................................ v

1 Introduction

1.1 Brief history …………………………….. 1

1.2 Recent development in this field .............................................. 4

1.3 Why are we concerned with our work ……………………………. 11

1.4 Outline of the thesis ……………………………. 11

2.1 Introduction ………….…….… 13

2.2 Amplifier and its uses ………..............….. 14

2.3 Amplifier classification …………………... 15

2.4 Concept of VFA and CFA ………………….. 23

2.5 Gain Bandwidth Behavior in Feedback Amplifiers ………………….. 29

2.6 Conclusion ………………….. 34

3 Our works

3.2 Our Proposed topologies to design

constant bandwidth amplifiers ………………... 36

3.3 Topology – 1 ………………… 37

3.4 Topology – 2 ……………… 41

3.5 Topology – 3 ……………... 46

3.6 Topology – 4 ……………... 50

3.7 Bode plots of the gain equations

of the proposed topologies (with the help of MATLAB) ………… 54

vi

4.2 Tools …………... 71

4.3 Simulation of the small signal model ………….. 71

4.4 Simulation of the CMOS design of proposed topology – 1 ……….. 84

4.5 Conclusion ………….. 104

5.2 Conclusion ………………………………… 107

1

Chapter – 1

Introduction

The process of raising the strength of a weak signal is known

as amplification and the device which accomplishes this job is

called an amplifier. According to the ability of an amplifier to

amplify the voltage level of the input signal or the ability to

amplify the power level of the input signal amplifier can be either

voltage amplifier or power amplifier.

amplifier is most probably the best known device because of its

widespread use and importance. The most common type of the

device is the Voltage Feedback Amplifier (VFA) which represents

the historical dominance of the voltage mode analog design in

electronic industry. Though it is less explored, other types of

feedback amplifiers exist both in industry and academia. Among

these, the Current Feedback Amplifier (CFA) are another

important member in amplifier group and employs the current

mode design approach.

2

form in the previous stage. With the invention of the phototube, the

history of signal amplification began in 1875, which was invented

by American G.R.Carey. Day by day, the rapid inventions of X-ray

Tube by Wilhelm Roentgen in 1895, Cathode Ray Oscilloscope by

Karl Braun in 1897, Magnetron Tube by Albert Hull in 1921 and

Klystron Tube by Russell and Sigurd Varian in 1938 became part

of history. With the development of technological advancement,

the vacuum tube has been described as the most important single

piece of equipment introduced into electrical engineering. Its

development has produced a new branch of engineering called

electronics. The applications of vacuum tubes are so varied that

this “miracle tool” has won a place in the industrial and

commercial fields. These tubes have been finding wide

applications in radio, long distance telephones, sound motion

pictures, television, radar, electronic computers and industrial

automation.

dominated by the vacuum tube. The major breakthrough in this

trend was experienced in 1947, when the invention of transistors

created a very dramatic change in electronic industry, which was

invented by William B.Shockley, Walter H. Bratt-ain and John

Bardeen of Bell Telephone Laboratories.

was invented which arrangement is a two stage, directly coupled

AC voltage amplifier.

emitter configuration. Isolated Input Data Acquisition Amplifier

also took place in modern technical industry in 1960s.

Adjustable Under frequency over frequency Limiting Circuit, and

3

invention of several other scientists. The small signal current to

voltage amplifier is such a circuit which has application as a

differentiator. In adjustable under frequency over frequency

limiting circuit, the output of the voltage amplifier is, in turn,

applied to the voltage control oscillator over a certain connecting

path. The active bias high voltage amplifier is a cascade amplifier

with an active base biasing circuit which is used to overcome the

classical limitation of using transistors in a high voltage amplifier.

Low Drift AC Coupled Photodiode Amplifier, Voltage Reference

Buffer, Differential Automatic Zero Correction Amplifier,

Automatic Zero Correction Amplifier, Modified ‘H’ Driver Power

Amplifier also became the part of the history.

invented. In 1990s Dual Amplifier designs behave like a traditional

voltage amplifier and increases the accuracy of current feedback

amplifier. There was also a use of MEDINA FIRM’S AMPLIFIER

IN EXPERIMENTS ABROAD SPACE SHUTTLE; the high-

voltage amplifier was used in several experiments with NASA and

the European Space Agency.

that means the time from 2002 to 2006, High-voltage amplifier

driving piezo tubes, and Wideband Amplifier which offers

dynamic range up to 80 dB, are the latest inventions of scientists

FEMTO. GmbH has introduced this new logarithmic wideband

voltage amplifier HLVA-100.This FEMTO device has a wide

dynamic range of up to 80 db.

4

feedback amplifiers and voltage feedback amplifiers, are central to

the design of many modern high-speed electronic systems. As

voltage feedback amplifiers, when utilized, have faced a number of

problems as they exhibit a constant gain bandwidth product,

resulting in a bandwidth which reduces in inverse proportion to

gain level. In contrast, the new generation of current feedback

amplifier (CFA) circuits promises improved performance in the

respect of bandwidth remaining constant even at higher levels of

gain. Its topology enables amplifiers to offer unique performance

advantages over traditional voltage feedback amplifiers (VFA).

These advantages are the reason more and more engineers are

designing with CFA designs based on CFA principles have

emerged as the preferred solution for constant bandwidth amplifier

circuits in favor of a current conveyor approaches.

when A. S. Sedra was doing research while pursuing his master’s

degree at the University of Toronto. Since then, this device has

been improved and after the first generation, which was totally

based on bipolar technology, it entered into the second generation.

The CCII is a three terminal device represented symbolically in

Figure 2.14. As the name implies, a current conveyor is also called

a current copier. Among the three terminals, X and Z are the

current copying terminals where the current into the terminal X is

copied to the terminal Z.

5

In this section, two different CFA design topologies are

presented which are proposed in the thesis paper “Novel Design

Approaches for Low–Voltage CMOS Current Feedback and

Transconductance Feedback Amplifier” (-by Md. Ataur Rahman Sarker).

These topologies use an opamp to achieve gain by moving the

transimpedance away from the Z node of the CCs. One point to

note here is that, for conventional designs, the high transimpedance

is provided by the resistance and the parasitic capacitance at the Z

node of the CCs. In the proposed designs, since the operational

amplifier accounts for the gain, CFAs designed this way do not

require a high transimpedance. In general, both topologies replace

the buffer with an opamp. In the sections that follow, the design

methods are presented with due explanation.

Topology 1

Firstly, a CFA design is proposed in which a second

generation positive current conveyor (CCII+) is followed by an

opamp. The opamp is operated in open-loop configuration and the

current feedback is provided by means of a single feedback resistor.

The proposed architecture is shown in Figure 3.1. Comparison of

Figure 3.1 with conventional CFA architecture reveals the

following distinct differences: i. the buffer is replaced by the

opamp, ii. The high impedance node is converted to low

impedance node and iii. The opamp in the proposed topology is

operated in open-loop mode. The proposed CFA circuit in

inverting configuration is represented in Figure 3.2. Note that Cz is

the internal capacitance at the Z node of the CCII+. A load

resistance R1 is inserted at the Z node of the CCII+, which results

in a parallel combination with Rz, the resistance at the Z node of

the CCII+, and R1. Since, R1 is very low as compared to Rz (i.e.Rz

_ R1), their parallel combination is effectively R1. Thus the

impedance of the Z node is reduced to _sCz//R1_from _ 1sCz//Rz_.

However, the requirement of high transimpedance is now

compensated by means of the opamp open loop gain, which is

typically very high (>50 dB). The advantage of -

6

generation of the high transimpedance in the conventional design.

In order to generate high transimpedance, it needs sufficient

number of cascade transistors between supply rails, which is

problematic for low voltage applications. This is due to the DC

biasing problem of the cascade transistors with low-voltage supply

and eventually some of the transistors might operate out of

saturation. On the other hand, keeping the Z node as a low

impedance point (by using minimum number of cascade transistors

between supply rails) and boosting the low gain by the opamp is an

interesting alternative to compensate the requirement of high

transimpedance.

7

through the load resistor R1, which is connected to the non

inverting input of the opamp. The voltage across R1 is then

amplified by the opamp’s high open-loop gain. The design is

purposely carried out so that the CCII+ bandwidth is a lot higher

than that of the opamp and hence, the opamp defines the overall

bandwidth of the proposed CFA. Analysis shows that this

arrangement results in a closed-loop bandwidth fixed by the

feedback resistor Rf and load resistance R1. Therefore, the gain in

voltage amplifying configuration can be adjusted without altering

the bandwidth.

Topology 2

generation negative current conveyor (CCII-) followed by an

opamp. The design architecture is shown in Figure 3.4. In this case,

the opamp is operated in closed-loop mode and feedback is

arranged only across the opamp, leaving the CCII- out of the

feedback loop. The circuit in Figure 3.5 represents the proposed

CFA in inverting configuration. Note that Cz and Rz are the

8

respectively. In this case, the impedance of the CCII- Z node is

defined by Rz and Cz. Figure 3.6, an extension of the design in

Figure 3.5, incorporates an extra opamp (A2) to reduce the input

resistance at the X terminal of the current conveyor.

9

setting feedback resistor around the entire CFA, the proposed

topology uses an opamp instead of buffer and negative feedback is

provided only across the opamp A1.

10

The main purpose for initiating research into TFAs is to

realize a low-voltage CMOS version of the device. Keeping this in

mind, a CMOS Wilson TFA was developed. Then the Wilson TFA

is modified by replacing the single-output transconductance block

with a dual-output transconductance block. The proposed design

architecture is presented in Figure 4.1 alongside the Wilson

topology for comparison purpose. A comparison of Figure 4.1 with

Figure 4.2 reveals two clear modifications performed on the

Wilson TFA, namely

• The single-output transconductance cell has been replaced by a

dual-output transconductance cell and

• The unity feedback is provided between one output of the dual-

output transconductance cell and the input of the opamp.

an exact copy of each other so that they provide exactly the same

11

shown in Figure 4.3, which is in inverting configuration. It is noted

that the opamp output feeds the positive input of the dual-output

transconductance cell and the opamp is operated in open-loop

configuration. The negative input of the gm cell is always

grounded. Note that co is the parasitic capacitance and ro is the

resistance at the outputs of the dual-output transconductance cell.

By using these topologies the analysis of the behavior of fixed

bandwidth amplifiers was attempted.

having similar gain configuration i.e. for voltage amplifier the gain

configuration used is also a voltage. So we are interested in

analyzing the amplifiers having dissimilar input and gain

configuration. Normally we know that, the gain bandwidth product

is constant. In that case if we want to increase the gain the

bandwidth is reduced, which is not desirable.

bandwidth is always constant. So that we can utilizes the benefits

of large bandwidth.

This thesis is organized in chapters and appendices as mentioned

below:

12

work and the associated research interests.” Brief History”

represents a brief description of how the amplifier we use today

arrives at this present form. From the inventions of phototubes, the

journey of the amplification of signal began and up to the

inventions of high voltage amplifier driving piezo tubes, wideband

amplifier and many other research works of the scientists have

occupied the place in the “Brief History”.” Recent Development in

This Field” is an overview of the ongoing research in our field of

interest. In this topic we mainly focuses On the conventional CFA

design topology and two new topology named “Topology 1” and

“Topology 2” which was developed to overcome the demerits of

using conventional design topology. We also give a description

about the “Wilson TFA design topology” and a “new TFA design

topology” which was proposed to realize a CMOS TFA with

special considerations for low-voltage applications.

bandwidth product (GBP) for four combinations of amplifiers,

where the main amplifying elements and the total feedback

amplifiers are of different types. Here we derived gain equations

for the four combinations of amplifiers. Latter in this chapter we

evaluated derived gain equations with the help of Matlab.

obtained from the schematic simulations by using the software

Matlab, PSpice and Orcad. The corresponding circuit schematics

are presented and the results generated are discussed.

chapter 5 with presenting the future works to be done.

13

Chapter - 2

2.1 Introduction

things in that area is very important and it indicates the starting

point of the chronological development on that field. Confirming

the same aim, this chapter presents the basics of voltage amplifiers

along with feedback amplifiers classification and gain-bandwidth

behavior of different amplifiers.

14

signal and gives an amplified output. Fig.2.1 shows a simple block

diagram of an amplifier. Where Si is the input signal and S0 is the

output signal and A is the amplification factor.

signals can be voltage or current. Table 2.1 represents the different

combination of Si and S0 and the corresponding nature of the

amplification factor A as determined by various amplifier types

Av,Ai,Az,Ag represents voltage gain, current gain, transimpedance,

transconductance respectively.

15

(Unit) (Unit)

Voltage Voltage Voltage Av (V/V)

(V) (V)

Current Current Current Ai (A/A)

(A) (A)

Transimpedance Voltage Current Az (V/A)

(V) (A)

Transconductance Current Voltage Ag (A/V)

(A) (V)

speaker to boost up the weak voice signals. There are actually

amplifiers all around us such as in televisions, computers, portable

compact discs (CD) players and many other devices that may use a

speaker to produce sound.

Amplifiers can be broadly classified into two categories:

1. Voltage amplifier

2. Power amplifier

signal. The voltage amplifiers are designed such that maximum

voltage gain can be achieved. A power amplifier amplifies the

power level of the input signal. A power amplifier can feed a large

power to the load. In order to get a large output power from this

amplifier, the input signal must be large. That is why a power

amplifier is called a large signal amplifier.

16

directly. It first takes power from the DC power sources connected

to the output circuit and then converts it into useful AC signal

power.

Since our thesis is not related with power amplifiers, only the

voltage amplifiers are discussed here elaborately.

1. Voltage amplifiers without feedback

2. Voltage amplifiers with feedback

happening at the output. If for some reason output changes the

input remains unaffected. It is also known as open loop system.

the input through the feedback network. It is also known as closed

loop system.

17

A0 = V0/Vi …………………..………………..(2.1)

the output voltage, A0 is open loop gain, Af is closed loop gain, β is

the feedback factor.

18

relative polarity of the signal being feedback into a circuit. In this

thesis, by feedback we will always mean negative feedback and the

classification henceforth presented is also for negative feedback

amplifier. Negative feedback results in decreased voltage gain. If

feedback signal is opposite polarity to the input signal as shown in

fig 2.3, negative feedback results. While negative feedback results

in reduced overall voltage gain, a number of improvements are

obtained, among them being

1. Higher input impedance

2. Better stabilized voltage gain

3. Improved frequency response

4. Lower output impedance

5. Reduced noise

6. more linear operation

According to the feedback configuration, there are four types

of feedback amplifiers, as follows.

feedback

amplifier. The feedback connection takes a part of the output

19

voltage fed back in series with the input signal, resulting in an over

all gain reduction.

is

Av = V0/Vs = V0/Vi ……………………(2.3)

If a feedback signal is connected in series with the input, then

Vf = βV0 ………………………….(2.4)

V i = V s – Vf ………………….………(2.5)

20

The main amplifying element here is a current amplifier. The

feedback network feeds back a part of the output current to the

input.

If = βI0 …………………………………(2.8)

21

Ii = Is – If ………………………………………….(2.9)

I0 = Ai Ii ………………………………………...(2.10)

shunt feedback

i.e. with current input it produces a voltage output. A portion of

output voltage is feedback to the input in the form of current.

22

If = βV0 …………………………………….. (2.12)

Ii = Is – If …………………………………… (2.13)

current series feedback

voltage feedback.

23

Vi = V s …………………………... (2.17)

provided for reference in table 2.2 below.

series series shunt series

Output Voltage Current Voltage Current

Feedback Voltage Current Current Voltage

Gain, A Av Ai Az Ag

Feedback Vf/V0 If/I0 If/V0 Vf/I0

factor, β

The VFA (voltage feedback amplifier) is that, in which the

feedback signal is proportional to the output voltage irrespective of

the load impedance.

On the other hand, in CFA, the feedback signal is

proportional to the output current irrespective of load impedance.

24

solution for constant bandwidth amplifier circuits in favor of a

current conveyor approach [ref]. A CFA effectively displays the

function of a unity gain voltage buffer between its two input

terminals. One terminal presents high input impedance, while the

second terminal exhibits a very low (ideally zero) input impedance

and constitutes a current feedback terminal. CFAs have

conventionally been designed with a second generation current

conveyor (CCII) followed by a buffer. As the name implies, a

current conveyor is also called a current copier. Among the three

terminals, X and Z are current copying terminals where the current

into the terminal X is copied to the terminal Z. Ideally the current

copying ratio should be unity, but practically it falls below unity as

the frequency is increased. Between terminals Y and X, the device

has a voltage following action. Ideally, whatever voltage appears at

Y is copied to X terminal.

engineers, which topology has better performance. Many engineers

still refuse to design with CFAs. This is due to a few

misunderstandings which can be easily clarified.

25

system that implements classical control theory analysis. It is

comfortable to design analog circuits using VFA in a closed loop

system. Most circuits commonly built with VFAs can utilize CFAs,

yielding better results at high frequencies. CFAs have sacrificed

the DC precision of VFA in a trade off for increased slew rate and

a bandwidth that is relatively independent of closed loop gain.

Although CFAs do not have the DC precision of their VFA counter

parts, they are good enough to be DC coupled in video applications

without sacrificing too much dynamic range. The days when high

frequency amplifiers had to be AC coupled are gone forever,

because some CFAs are approaching GH gain bandwidth region.

The slew rate of CFAs is not limited by the linear rate of rise that

is seen in VFAs, so it is much faster and leads to faster rise or fall

times and less intermodulation distortion.

VFA CFA

1. Lower noise 1. Lower distortion

2. Better DC performance 2. Better linear phase

performance

3. Feedback freedom 3. Feedback restriction

4. Constant GBP 4. BW almost independent of

closed loop gain

5. Relatively lower BW 5. Higher potential BW than

VFA

6. Lower slew rate 6. Higher slew rate

7. Low input offset voltage 7. Nonzero input offset voltage

8. High input impedance 8.Unequal input stage

impedance

9. Matched input bias current 9. Unmatched input bias current

10. Low output impedance 10. High output impedance

26

CFA has a far better result than VFA. Since our thesis is base on

variable GBP amplifiers we have preferred CFA for our further

theoretical analysis.

compared in the following figures. The term ‘loop gain’ in an

electrical circuit is defined as the product of the forward gain and

the feedback factor. For example, in Figure 2.3 loop gain is given

by Ao. Hence, it is clear that loop gain is always associated with a

feedback system.

27

VFA. Here BW1 and BW2 are the bandwidths corresponding to

the demanded gains A1 and A2, respectively. It is clear that when

gain is increased from A1 to A2, bandwidth reduces from BW1 to

BW2. This is because

Or

GBP1 = GBP2 ………………………………………………...(2.20)

variable loop gain in VFAs. As shown in Figure 2.8, loop gain

(Ao−Ai) {i = 1, 2}, where Ao is the open loop gain, varies with the

28

demanded gain and varies in inverse proportion of the gain.

However, CFAs behave in a totally opposite way as shown in

Figure 2.9.

cope with the increasing demanded gain and vice versa. Thus, it

maintains a constant loop gain. The advantage of this phenomenon

is that the gain curve is adjusted automatically In this case, the

forward path gain automatically increases to cope with the

increasing demanded gain and vice versa. Thus, it maintains a

constant loop gain. The advantage of this phenomenon is that the

gain curve is adjusted automatically to accommodate the new level

of demanded gain keeping the closed-loop bandwidth constant. So,

29

noticed in Figure 2.9, though the gain is increased from A1 to A2

bandwidth remains constant at BW i.e.

And this is due to the constant loop gain TL. In conclusion, the

CFA has a variable GBP and the bandwidth ideally remains

constant irrespective of the demanded closed loop gain.

Amplifiers

constant bandwidth behavior is the most prevalent case. However,

this does not simply apply to the four most commonly encountered

feedback configurations, where the amplifier and the feedback

arrangement are of the same type, namely, voltage series, current

shunt, voltage shunt and current as shown in Table 2.2 VFAs are

used in general purpose electronic system where constant GBP is

required and the resulting bandwidth is inversely proportion to the

demanded gain level. On the other hand, the current feedback

amplifiers (CFAs) provide better performance with respect to

bandwidth and gain level. The ICs designed using the current

feedback topology realizes constant bandwidth even at higher gain

levels than those in VFAs series. The CFA principle has a greater

benefit that it can be used to achieve constant BW amplifiers.

Constant bandwidth behavior can be achieved by using different

gain configurations as shown in table 2.3, 2.4, 2.5, 2.6. One thing

is to mention here that the type of feedback applied and the type of

30

independent choices. So we can have a variety of combinations

with respect to the feedback and the amplifying element types as

clarified in Tables 2.3 to 2.6. When amplifier type and the

feedback used are dissimilar the constant bandwidth behavior is

potentially available.

current gain, transimpedance and transconductance, along with the

four possible amplifying element types resulting sixteen possible

combinations of the amplifying elements and the feedback

configurations. The type of feedback used will define the stability

of the overall transfer function and the amplifying element type

will govern the input and output impedances as well as the

bandwidth dependency on the demanded gain. For example,

voltage series feedback stabilizes the voltage gain, whereas the

voltage shunt feedback stabilizes the transimpedance, and so on.

The performance of the combined amplifier and feedback network

can be determined by evaluating the closed-loop gain and the loop

gain. If the loop gain varies according to the inverse proportion of

the closed-loop gain, the combined structure will result in constant

GBP. A constant loop gain will produce variable GBP or constant

bandwidth.

31

feedback combinations are summarized in the following Tables.

2. Current Amplifier BW always constant

3.Transimpedance BW potentially

Amplifier constant

4.Transconductance BW potentially

Amplifier constant

voltage gain configuration

2.Current Amplifier GBP constant

3. Transimpedance BW potentially

Amplifier constant

4. Transconductance BW potentially

Amplifier constant

current gain configuration

32

2. Current Amplifier BW always constant

3. Transimpedance GBP constant

Amplifier

4. Transconductance BW potentially

Amplifier constant

transimpedance configuration

2. Current Amplifier BW always constant

3. Transimpedance BW potentially

Amplifier constant

4. Transconductance GBP constant

Amplifier

transconductance con-figuration

It can be observed from the previous Tables that all the four

cases where the amplifying element and the feedback type are

similar, produces constant GBP. These are the cases most

commonly discussed with feedback amplifiers as summarized in

Table 2.2. For example, a current amplifier designed applying

current shunt feedback around a current amplifying element will

always give constant GBP. Similarly, when voltage,

transimpedance and transconductance amplifying elements are

33

feedback networks, respectively, will result in constant GBP. In the

remainder of the cases where dissimilarity is maintained between

the amplifying elements and the feedback types, variable GBP

results, which in turn produces constant bandwidth.

all the cases using voltage and current amplifying elements, except

for the cases when the feedbacks are voltage series (Figure 2.4)

and current shunt (Figure 2.5), respectively, display constant loop

gain (TL). Thus, these configurations will provide gain-

independent bandwidth. On the other hand, Tables 2.3 to 2.6 also

clarify that transimpedance and transconductance amplifying

elements produce potentially constant bandwidth, except for the

cases when the feedback arrangements are voltage shunt (Figure

2.6) and current series (Figure 2.7), respectively. The term

‘potentially constant bandwidth’ means that the bandwidth is

constant only under certain specific conditions. This is because

when the main amplifying element is either transimpedance or

transconductance, the loop gain TL depends on one of the elements

that define the closed loop gain. Hence, constant bandwidth

behavior can be experienced only when one of the gain defining

elements is kept constant. CFAs and TFAs fall under these

conditions.

This topic is highly important because the main focus of

our thesis is to analyze and simulate constant BW amplifiers.

34

2.6 Conclusion

basic ideas of our thesis related topics. The key point of this

chapter is that gain-independent BW can be achieved from many

different alternatives where the main amplifying element and the

feedback connections are of different type. For same type of

amplifier and the feedback arrangement GBP is always constant.

The main focus of our thesis is the simulation and theoretical

analysis of sixteen possible combinations [table] of the amplifying

elements and the feedback configuration.

35

Chapter – 3

Our works

3.1 Introduction

In the previous chapter we saw that current feedback

amplifier has a variable gain bandwidth product and ideally the

bandwidth remains constant irrespective of the closed loop gain it

is providing. The ICs which are designed employing current

feedback topology can provide constant bandwidth even at higher

gain levels than those in the voltage feedback amplifier. But this

phenomenon does not apply to the four most commonly used

feedback configurations, where the amplifier and the feedback

arrangement are of the same type which we observed in the

previous chapter. In the previous chapter we saw that the constant

bandwidth behavior is potentially obtainable whenever the

amplifier type and the feedback used are not similar. There we saw

in the tables under the topic “Gain bandwidth behavior in feedback

amplifier” that in every case (except for the cases where the

feedback is voltage series in voltage amplifier and current shunt in

current amplifier) using voltage and current amplifying elements

provide constant loop gain. This is how these configurations will

provide gain independent band width without having any effect of

the gain defining elements. Constant bandwidth behavior can be

experienced only when one of the gain defining elements is kept

constant.

36

bandwidth amplifiers

feedback amplifier” of the previous chapter we can note that there

are six possible amplifiers and feedback combinations where

constant bandwidth is obtained. Our proposed topologies are based

on those combinations. First we worked at the block diagram level

to develop our topology. Then we went to the small signal analysis

from the block diagram level. From the small signal analysis we

deduced the gain equation and the 3dB bandwidth equation for our

proposed topologies. But for the last two combinations which were

– voltage amplifier and current amplifier with such a feed back that

the gain bandwidth behavior of the feedback amplifier is in

transconductance configuration; we obtained the gain equation and

the 3dB bandwidth equation in cumbersome and complicated. We

judged that derived equations of the last two combinations will fail

to provide constant band width behavior. So we did not propose

any topology based on the last two combinations. We proposed

four topologies in total. These four topologies are described one

after another in the following.

37

3.3 Topology – 1

amplifying element with such a feedback structure that total

combination works with the gain band width behavior in voltage

gain configuration. In this topology we used a positive second

generation current conveyor (CCII+), current amplifier,

transimpedance block and a feedback network. A current

proportional to input voltage signal appears to the input of the

CCII+, which copies the input current to its output. Output current

of the CCII+ will be amplified by the current amplifier. The output

current of the current amplifier is then used to produce a voltage

proportional to the current itself. This is performed by a

transimpedance block. Finally the feedback network provides

current feedback proportional to the output voltage to the input

terminal of the CCII+. The block diagram is shown below.

element: current amplifier and total feedback amplifier is in

voltage gain configuration to obtain Variable GBP(constant

bandwidth).

38

proposed topology – 1 in inverting configuration. Following figure

shows the small signal model of our proposed topology – 1 in

inverting configuration.

configuration.

buffer at the input side of CCII+ is zero and it copies its input

voltage at node –X. We assumed that the input resistance rx of the

CCII+ is very small and close to zero, so we neglected its effect.

The internal capacitance at the Z node of the CCII+ is Cz and the

resistance at the Z node is Rz. The value of Cz is in pico farad

range and the value of Rz is in several kilo ohm range.

39

we assumed input resistance (RiA) of the current amplifier is small

and output resistance (Rio) tends to infinity. So we considered that

a negligible amount of current passes through output resistance

(Rio).

One portion of the output current passes through it, as a result we

obtain a output voltage Vo proportional to the current io which

passes through Ro. We can use a buffer at the output or for a fixed

load we can set Ro = Rload (Load resistance).

The feedback current if is proportional to output voltage Vo.

Feedback current, if = Vo ;

Rf

Input current to current conveyor, iin = Vin ;

Ri

The voltage gain of the total combination of the proposed topology

– 1 is given as follows -

Gv = Vo = − AiωtRoRf ………………………………..(3.1)

Vin Ri{(S + ωt )( Rf + Ro) + AiωtRo}

topology-1 is given by [appendix A.1] –

f = ft{1+ Ai ⋅ Ro } ...................................................................(3.2)

Rf + Ro

40

topology -1) we can note that feedback resistance Rf, output

resistance Ro and the input resistance Ri are the gain defining

elements which we can vary. But from the equation 2.2 (3dB

bandwidth equation) it is evident that feedback resistance Rf and

output resistance Ro also determines the 3dB bandwidth of our

proposed topology – 1. Input resistance Ri is the only gain defining

element which does not effect 3dB bandwidth. We can conclude

that here we have obtained variable GBP (constant bandwidth), if

the voltage gain is varied by the input resistance Ri.

configuration is shown below.

configuration.

Gv = Vo = AiωtRoRf …………………………………(3.3)

Vin Ri{(S + ωt )( Rf + Ro) + AiωtRo}

41

same as the inverting configuration, that is-

f = ft{1+ Ai ⋅ Ro }

Rf + Ro

3.4 Topology – 2

amplifying element with such a feedback structure that total

combination works with the gain band width behavior in current

gain configuration. In this topology we used a positive second

generation current conveyor (CCII+), voltage amplifier,

transconductance block and a feedback network. Input current

signal is applied to the input of the CCII+, which copies the input

current to its output. Output current of the CCII+ will be used to

produce a voltage proportional to the current itself. This is done by

the impedance at the node Z of the CCII+. As ideally input

impedance of the voltage amplifier is infinity, the output current of

the CCII+ will flow through the impedance of the Z node. This

will produce the required input voltage of the voltage amplifier.

This voltage is than amplified by a voltage amplifier. The output

voltage of the voltage amplifier is then used to produce a current

proportional to the voltage itself. This is performed by a

transconductance block. Finally the feedback network provides

current feedback proportional to the output current to the input

42

proposed topology - 2.

element: voltage amplifier and total feedback amplifier is in

current gain configuration to obtain Variable GBP(constant

bandwidth).

proposed topology – 2 in inverting configuration. Following figure

shows the small signal model of our proposed topology – 2 in

inverting configuration.

configuration.

43

buffer at the input side of CCII+ is zero and it copies its input

voltage at node –X. We assumed that the input resistance rx of the

CCII+ is very small and close to zero, so we neglected its effect.

The internal capacitance at the Z node of the CCII+ is Cz and the

resistance at the Z node is Rz. The value of Cz is in pico farad

range and the value of Rz is in several kilo ohm range.

- we assumed input resistance (RiA) of the voltage amplifier tends

to infinity and output resistance (RoA) tends to zero. So we

considered that a negligible amount of current passes through input

resistance (RiA) and the voltage drop across the output resistance

(RoA) is also negligible.

is - we assumed input resistance (Rig) and output resistance (Rog) of

the transconductance block tends to infinity. So we considered that

a negligible amount of current passes through both the input

resistance (Rig) and the output resistance (Rog).

The feedback current if is proportional to output current io.

Rf

44

– 2 is given as follows –

Gi = io

iin

=− RfRzAoωtgm

RoRzAoωtgm + ωt ( Rf + Ro) + S (1+ ωtCzRz)( Rf + Ro) + S 2CzRz( Rf + Ro)

………………………………..(3.4)

topology-2 is given by [appendix A.2] –

( Rf + Ro)

⇒f=

4π CzRz

........................................................(3.5)

topology -2) we can note that feedback resistance Rf and out

resistance Ro are the gain defining elements which we can vary.

But from the equation 2.5 (3dB bandwidth equation) it is evident

that feedback resistance Rf and output resistance Ro also

determines the 3dB bandwidth of our proposed topology – 2. From

the 3dB bandwidth equation we can see that we have a chance to

have negligible effect on the 3dB bandwidth for variation of Rf , if

Ro is very much greater than Rf . In this case we can neglect the

RoRzAogm

term 8π ftCzRz ×{1+ } . With the help of MATLAB we will

( Rf + Ro)

45

3dB bandwidth by the equation we have obtained.

configuration is shown below.

configuration.

Gi = RfRzAoωtgm

RoRzAoωtgm + ωt ( Rf + Ro) + S (1+ ωtCzRz)( Rf + Ro) + S 2CzRz( Rf + Ro)

…………………………………(3.6)

same as the inverting configuration, that is-

( Rf + Ro)

⇒f=

4π CzRz

46

3.5 Topology – 3

amplifying element with such a feedback structure that total

combination works with the gain band width behavior in

transimpedance gain configuration. In this topology we used a

positive second generation current conveyor (CCII+), voltage

amplifier and a feedback network. Input current signal is applied to

the input of the CCII+, which copies the input current to its output.

Output current of the CCII+ will be used to produce a voltage

proportional to the current itself. This is done by the impedance at

the node Z of the CCII+. As ideally input impedance of the voltage

amplifier is infinity, the output current of the CCII+ will flow

through the impedance of the Z node. This will produce the

required input voltage of the voltage amplifier. This voltage is than

amplified by a voltage amplifier. Finally the feedback network

provides current feedback proportional to the output voltage to the

input terminal of the CCII+. The block diagram is shown below.

element: voltage amplifier and total feedback amplifier is in

transimpedance configuration to obtain Variable GBP(constant

bandwidth).

47

proposed topology – 3 in inverting configuration. Following figure

shows the small signal model of our proposed topology – 3 in

inverting configuration.

configuration.

buffer at the input side of CCII+ is zero and it copies its input

voltage at node –X. We assumed that the input resistance rx of the

CCII+ is very small and close to zero, so we neglected its effect.

The internal capacitance at the Z node of the CCII+ is Cz and the

resistance at the Z node is Rz. The value of Cz is in pico farad

range and the value of Rz is in several kilo ohm range.

48

- we assumed input resistance (RiA) of the voltage amplifier tends

to infinity and output resistance (RoA) tends to zero. So we

considered that a negligible amount of current passes through input

resistance (RiA) and the voltage drop across the output resistance

(RoA) is also negligible.

The feedback current if is proportional to output voltage Vo.

Input current to current conveyor is iin. Feedback current, if = Vo ;

Rf

The gain of the total combination of the proposed topology – 3 is

given as follows -

⇒ Rm = Vo = − RfRzAoωt

iin Rf ωt + RzAoωt + S 2 RfCzRz + SRf (1+ ωtCzRz)

………………………..(3.7)

topology-3 is given by [appendix A.3] –

⇒f=

4π CzRzRf

......................(3.8)

topology -3) we can note that feedback resistance Rf is the only

gain defining elements which we can vary. But from the equation

2.8 (3dB bandwidth equation) it is evident that feedback resistance

Rf also determines the 3dB bandwidth of our proposed topology –

3. From the 3dB bandwidth equation we can see that we have a

49

variation of Rf, if 8π ftCzRzRf ( Rf + RzAo) can be neglected from

3dB bandwidth equation. With the help of MATLAB we will

observe the effect of variation of the external resistance Rf on 3dB

bandwidth by the equation we have obtained.

configuration is shown below.

configuration.

will be –

Rf ωt + RzAoωt + S 2 RfCzRz + SRf (1+ ωtCzRz)

same as the inverting configuration, that is-

− Rf (1+ 2π ftCzRz ) ± Rf 2 (1+ 2π ftCzRz)2 + 8π ftCzRzRf ( Rf + RzAo)

f=

4π CzRzRf

50

3.6 Topology – 4

amplifying element with such a feedback structure that total

combination works with the gain band width behavior in

transimpedance gain configuration. In this topology we used a

positive second generation current conveyor (CCII+), current

amplifier, transimpedance block and a feedback network. Input

current signal is applied to the input of the CCII+, which copies the

input current to its output. Output current of the CCII+ will be

amplified by the current amplifier. The output current of the

current amplifier is then used to produce a voltage proportional to

the current itself. This is performed by a transimpedance block.

Finally the feedback network provides current feedback

proportional to the output voltage to the input terminal of the

CCII+. The block diagram is shown below.

element: current amplifier and total feedback amplifier is in

transimpedance configuration to obtain Variable GBP(constant

bandwidth).

51

proposed topology – 4 in inverting configuration. Following figure

shows the small signal model of our proposed topology – 4 in

inverting configuration.

configuration.

buffer at the input side of CCII+ is zero and it copies its input

voltage at node –X. We assumed that the input resistance rx of the

CCII+ is very small and close to zero, so we neglected its effect.

The internal capacitance at the Z node of the CCII+ is Cz and the

resistance at the Z node is Rz. The value of Cz is in pico farad

range and the value of Rz is in several kilo ohm range.

we assumed input resistance (RiA) of the current amplifier is small

and output resistance (Rio) tends to infinity. So we considered that

a negligible amount of current passes through output resistance

(Rio).

52

- we assumed input resistance (RiA’) and output resistance (RoA’) of

the transimpedance block tends to Zero. So we considered that

voltage drop across the output resistance (RoA’) is negligible. Let

the gain of the transimpedance block is Rm(S).

The feedback current if is proportional to output voltage Vo.

Rf

The transimpedance gain of the total combination of the proposed

topology – 4 is given as follows -

Rm = Vo = − RfRmAiωt ………..(3.10)

iin Rf ωt + RmAiωt + S 2CzRiARf + SRf (1+ CzRiAωt )

topology-4 is given by [appendix A.4] –

f=

4π CzRiARf

.....................(3.11)

-4) we can note that feedback resistance Rf is the only gain

defining elements which we can vary. But from the equation 2.11

(3dB bandwidth equation) it is evident that feedback resistance Rf

also determines the 3dB bandwidth of our proposed topology – 4.

From the 3dB bandwidth equation we can see that we have a

chance to have negligible effect on the 3dB bandwidth for

53

3dB bandwidth equation. With the help of MATLAB we will

observe the effect of variation of the external resistance Rf on 3dB

bandwidth by the equation we have obtained.

configuration is shown below.

inverting configuration.

will be –

Rm = RfRmAiωt …………………(3.12)

Rf ωt + RmAiωt + S CzRiARf + SRf (1+ CzRiAωt )

2

same as the inverting configuration, that is-

⇒f=

4π CzRiARf

54

proposed topologies (with the help of MATLAB)

topology -1 is –

Gv = Vo = − AiωtRoRf

Vin Ri{(S + ωt )( Rf + Ro) + AiωtRo}

topology – 1 with their values which are used as the initial input of

the MATLAB program to obtain bode plot.

Bandwidth of the current amplifier, ωt=1000 Hz

Output resistance, Ro=100 Ω

Feedback resistance Rf =1000 Ω

Input resistance Ri =100 Ω

55

obtained the bode plot shown below.

Now we will vary the input resistance Ri. The bode plot

below shows the variation of Ri with the other parameters remain

unchanged as defined initially. Used values of the input resistance

Ri in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

56

Now we will vary the feedback resistance Rf. The bode plot

below shows the variation of Rf with the other parameters remain

unchanged as defined initially. Used values of the feedback

resistance Rf in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

57

Now we will vary the output resistance Ro. The bode plot

below shows the variation of Ro with the other parameters remain

unchanged as defined initially. Used values of the output resistance

Ro in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

58

Our observation on the above bode plots found that for the

variation of input resistance Ri there is no variation in the 3dB

bandwidth. But constant bandwidth is not available for the

variation the other external resistances. This supports our previous

comments on the gain bandwidth behavior of the toplogy-1, which

we did by observing the gain equation.

The MATLAB code for the above bode plots is provided in

the appendix – B.1.

59

topology -2 is –

Gi = − RfRzAoωtgm

RoRzAoωtgm + ωt ( Rf + Ro) + S (1+ ωtCzRz)( Rf + Ro) + S 2CzRz( Rf + Ro)

topology – 2 with their values which are used as the initial input of

the MATLAB program to obtain bode plot.

Gain of the transconductance block, Gm =5

Bandwidth of the voltage amplifier, ωt=1000 Hz

Output resistance, Ro=100 Ω

Feedback resistance, Rf =1000 Ω

Resistance at node Z, Rz =10KΩ

Capacitance at node Z, Cz =1pF

60

obtained the bode plot shown below.

Now we will vary the feedback resistance Rf. The bode plot

below shows the variation of Rf with the other parameters remain

unchanged as defined initially. Used values of the feedback

resistance Rf in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

61

Now we will vary the output resistance Ro. The bode plot

below shows the variation of Ro with the other parameters remain

unchanged as defined initially. Used values of the output resistance

Ro in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

62

bandwidth is not available for the variation of any external

resistances. This supports our previous comments on the gain

bandwidth behavior of the toplogy-2, which we did by observing

the gain equation.

The MATLAB code for the above bode plots is provided in

the appendix – B.2.

63

topology -3 is –

Rm = − RfRzAoωt

Rf ωt + RzAoωt + S 2 RfCzRz + SRf (1+ ωtCzRz)

topology – 3 with their values which are used as the initial input of

the MATLAB program to obtain bode plot.

Bandwidth of the voltage amplifier, ωt=1000 Hz

Feedback resistance, Rf =1000 Ω

Resistance at node Z, Rz =1KΩ

Capacitance at node Z, Cz =1pF

64

obtained the bode plot shown below.

Now we will vary the feedback resistance Rf. The bode plot

below shows the variation of Rf with the other parameters remain

unchanged as defined initially. Used values of the feedback

resistance Rf in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

65

bandwidth is not available for the variation of any external

resistances. This supports our previous comments on the gain

bandwidth behavior of the toplogy-3, which we did by observing

the gain equation.

The MATLAB code for the above bode plots is provided in

the appendix – B.3.

66

topology -4 is –

Rm = − RfRmAiωt

Rf ωt + RmAiωt + S CzRiARf + SRf (1+ CzRiAωt )

2

topology – 4 with their values which are used as the initial input of

the MATLAB program to obtain bode plot.

Gain of the transimpedance block, Gm =5

Bandwidth of the current amplifier, ωt=1000 Hz

Feedback resistance, Rf =1000 Ω

Input resistance of the current amplifier, RiA =10Ω

Capacitance at node Z, Cz =1pF

67

obtained the bode plot shown below.

Now we will vary the feedback resistance Rf. The bode plot

below shows the variation of Rf with the other parameters remain

unchanged as defined initially. Used values of the feedback

resistance Rf in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

68

bandwidth is not available for the variation of any external

resistances. This supports our previous comments on the gain

bandwidth behavior of the toplogy-4, which we did by observing

the gain equation.

The MATLAB code for the above bode plots is provided in

the appendix – B.4.

69

3.8 Conclusion

that only for topology – 1 we can find a gain defining element

which has no effect on the 3dB bandwidth. The gain defining

element is the input resistance Ri. For the other topologies we

could not obtain any gain defining element which has no effect on

the 3dB bandwidth. But after numerous attempts with different sets

of values of gain defining element to obtain minimum effect on the

3dB bandwidth may result to a considerable point. But still that

may be quite large in comparison with proposed topology – 1.

70

Chapter – 4

4.1 Introduction

1 provides the best gain equation to obtain constant bandwidth. It

has only two main circuit components – one is positive second

generation current conveyor (CCII+) and other one is current

amplifier. The transimpedance component can be implemented

with only one resistance. So it will require lesser MOS devices for

CMOS design. Proposed topology – 2 has also two main circuit

components, but its gain equation is not as perfect as the proposed

topology – 1 for obtaining variable GBP. So we thought that it will

be wiser to concentrate on the topology – 1 to obtain any

successful result within a limited time. Accordingly we further

analyzed and simulated only the topology – 1.

71

4.2 Tools

We used PSpice student version and orcad 9.1 (Evolution

Version) to simulate the circuits under our research. But PSpice

student version can not simulate the schematics having larger

circuits. But it can generate schematics netlist of larger circuits. All

the CMOS designs of our concern for this thesis fall in larger

circuit category. So, we used PSpice student version to obtain

schematic netlist. Because writing schematic netlist is cumbersome

to us for the larger circuits. Ultimately the obtained netlists are

simulated in the orcad 9.1. Actually we tried to use the resources

available to us.

model. First we simulated the small signal model of the proposed

topology – 1 in inverting configuration which is shown in the

figure below.

inverting configuration.

72

library. So, we used an ideal opamp in voltage follower mode to

serve the purpose of a buffer. The PSpice Schematic is shown

bellow.

inverting configuration. Here the purpose of the buffer is done by

an ideal opamp.

the proposed topology – 1 in inverting configuration are shown in

the following.

resistance and output resistance. I(R1) is the current flowing

through the input resistance and I(R8) is the current flowing

through the output resistance.

73

Fig 4.3: I(R1) is the current flowing through the input resistance

and I(R8) is the current flowing through the output resistance.

of the topology – 1 for inverting configuration. V(vin) is the input

voltage and V(vout) is the output voltage.

Fig 4.4: V(vin) is the input voltage and V(vout) is the output

voltage.

74

topology – 1 in non-inverting configuration.

inverting configuration.

library, we used the following circuit for the small signal analysis

of the proposed topology – 1 for non-inverting configuration.

inverting configuration. Here the purpose of the buffer is done by

an ideal opamp.

75

the proposed topology – 1 in non-inverting configuration are

shown in the following.

resistance and output resistance. I(R7) is the current flowing

through the input resistance and I(R6) is the current flowing

through the output resistance.

Fig 4.7: I(R7) is the current flowing through the input resistance

and I(R6) is the current flowing through the output resistance.

of the topology – 1 for non-inverting configuration. V(vin) is the

input voltage and V(vout) is the output voltage.

76

Fig 4.8: V(vin) is the input voltage and V(vout) is the output

voltage.

obtained a considerable gain for both for inverting and non-

inverting configurations of our proposed topology – 1.

AC analyses shown are for inverting configuration. Her we will

not show AC analysis for non-inverting configuration because both

will result the same.

topology – 1 with there values which are used as the initial values

for the AC analysis.

Bandwidth of the current amplifier, ωt=1000 Hz

Output resistance, Ro=100 Ω

Feedback resistance Rf =1000 Ω

Input resistance Ri =100 Ω

77

obtained the frequency response curve shown below.

initially.

point.

frequency response curves show the variation of Ri with the other

parameters remain unchanged as defined initially. Used values of

the input resistance Ri in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

78

10Ω.

100Ω.

79

1kΩ.

10k Ω.All the above bode plots showed the effect of variation of Ri.

80

Now we will vary the feedback resistance Rf. The bode plot

below shows the variation of Rf with the other parameters remain

unchanged as defined initially. Used values of the feedback

resistance Rf in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

100Ω.

1kΩ.

81

10kΩ . All the above bode plots showed the effect of variation of Rf.

Now we will vary the output resistance Ro. The bode plot

below shows the variation of Ro with the other parameters remain

unchanged as defined initially. Used values of the output resistance

Ro in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

10Ω.

82

100Ω.

1kΩ.

83

10kΩ . All the above bode plots showed the effect of variation of Ro.

found that for the variation of input resistance Ri there is a very

little variation in the 3dB bandwidth. But constant bandwidth is not

available for the variation of the other external resistances. This

supports our previous comments on the gain bandwidth behavior

of the toplogy-1, which we did by observing the gain equation and

there corresponding bode plots.

84

proposed topology – 1

are positive second generation current conveyor (CCII+) and

current amplifier. Initially we will concentrate on the positive

second generation current conveyor (CCII+) and the current

amplifier separately.

Conveyor (CCII+)

85

devices used in the CCII+.

W/L (μm/μm)

M1, M2 100/1

M3, M4 40/1

M5, M11, M13 20/1

M6 45/1

M7 10/1

M10, M12 60/1

M8 2.7/1

M9 5/1

CCII+ of fig-4.13.

Fig 4.14: I(I_I1) is the input current and I(R_R1) is the output

current.

From the above figure we found that the CCII+ provides zero

current for the negative half cycle of the input current and gain is

also less than zero. It may happen for improper biasing.

The schematics netlist of the circuit of the fig-4.13 is

provided in the appendix C.1.

86

current amplifier.

aspect ratio of M5 (M8) and M7 (M10) –

A = iout = =

iin (W / L)5 (W / L)8

87

devices used in the above current amplifier.

W/L (μm/μm)

M1 20/1

M2 20/1

M3 20/1

M4 20/1

M5 20/1

M6 20/1

M7 80/1

M8 20/1

M9 20/1

M10 80/1

amplifier.

current amplifier of fig-4.15.

Fig 4.16: I(I1) is the input current and I(R1) is the output current.

provided in the appendix C.2.

88

proposed topology – 1

circuit to form the inverting configuration our proposed topology –

1. The circuit diagram is shown bellow.

inverting configuration.

89

forms of the circuit of the fir-4.17.

output voltage of the circuit of the fig – 4.17.

attenuated from the input voltage signal. So here the gain is less

than one. But our main objective is to obtain variable GBP. So, for

the time being we will not be bothered by the attenuated output

voltage of the circuit of the fig – 4.17.

Another thing here we can note that our output is not inverted

though it is in the inverting configuration. The reason of this

phenomenon can be realized if we compare carefully the direction

of the output current of current amplifier in both small signal

model and in the CMOS design. The comparison says that output

current of the CMOS current amplifier is in opposite direction to

that of the small signal model of the current amplifier.

90

the input resistance R_Rgncntrl and observe the effects of its

variation on the 3dB bandwidth. Following three figures will show

the effects of the variation of R_Rgncntrl on the 3dB bandwidth. In

these figures we kept the value of the other external resistances

constant (R_Rload = 5kΩ and R_Rfeedback = 1kΩ).

100Ω.

91

the circuit of the fig – 4.17 is inversely proportional to the input

resistance which is also supported by our derived gain equation.

Here we have also found an infinitely wide flat bandwidth.

in the 3dB bandwidth. Following figure shows the AC analysis of

the circuit of the fig - 4.17 with output resistance R_Rload =

500kΩ, feedback resistance R_Rfeedback = 1kΩ and input

resistance R_Rgnctrl = 10.

92

500kΩ.

Surprisingly here we have also found an infinitely wide flat

bandwidth which is obviously not expected.

variation in the 3dB bandwidth. Following figure shows the AC

analysis of the circuit of the fig - 4.17 with output resistance

R_Rload = 5kΩ, feedback resistance R_Rfeedback = 10Ω and

input resistance R_Rgnctrl = 10.

= 10Ω.

93

bandwidth which is obviously not expected.

observe the individual AC analysis of the CCII+ circuit and the

current amplifier circuit.

amplifier.

94

CCII+ and current amplifier circuit that as both of their frequency

response are infinitely wide and flat, the circuit built by cascading

them will also have an infinitely wide and flat frequency response

curve. But this phenomenon is completely impractical.

design may result from the fact that the MOS devices we used in

simulation were generalized and ideal in nature.

MOS devices having parameters as following -

*model specification:

*MCE 3 Micron CMOS processes parameters-process 2

*N channel type

.model nenh nmos level=2 vto=0.85 kp=30e-6 tox=470e-10 nsub=38e14

+ld=0.6e-6 uo=624 uexp=0.055 vmax=20e4 neff=9.8 delta=2.0 cj=160e-6

cjsw=430e-12 mj=0.5 mjsw=0.33 pb=0.81

*p channel typ

.model penh pmos level=2 vto=-0.85 kp=12e-6 tox=470e-10 nsub=8.7e14

+ld=0.5e-6 uo=200 uexp=0.18 vmax=12e4 neff=4.0 delta=2.0

+cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 pb=0.7

.ac DEC 10000 10 10000GHz

design of the topology – 1 in inverting configuration. First we will

vary the input resistance R_Rgncntrl and observe the effects of its

variation on the 3dB bandwidth. Following two figures will show

the effects of the variation of R_Rgncntrl on the 3dB bandwidth. In

these figures we kept the value of the other external resistances

constant.

95

the circuit of the fig – 4.17 is inversely proportional to the input

resistance which is also supported by our derived gain equation.

But here 3dB bandwidth also varies with the variation of input

resistance, which is not expected.

in the 3dB bandwidth. Following figures show the AC analysis of

96

the circuit of the fig - 4.17 with other external resistances kept

constant.

0.5kΩ.

5kΩ.

Observing the above frequency response curves, we found

that variation of the output resistance has a little effect on the 3dB

bandwidth.

97

variation in the 3dB bandwidth. Following figures show the AC

analysis of the circuit of the fig - 4.17 with other external

resistances kept constant.

= 10Ω.

= 100Ω.

98

= 1kΩ.

= 1kΩ.

inverting configuration using the latter MOS device parameters is

provided in the appendix – C.3. Observing the above frequency

response curves, we surprisingly discovered that variation of

99

feedback resistance does not have any effect on the 3dB bandwidth.

But our gain equation and simulation of the small signal model

says that we should have obtain constant bandwidth for the

variation of input resistance to control gain.

gain equation of the topology -1 for inverting configuration. But

we could not detect any errors there. There we neglected some

parameters for their very small values. We thought that those

parameters are too small to make any noticeable effect in the gain

equation. Even though now we will reconsider the neglected

parameters again. By reconsidering the previously neglected

parameters we obtained the gain equation as following –

Gv = − AiωtRoRf

Ri{S 2CzRiA + S ( Rf + Ro + RiA + CzRiA) + [ωt ( Rf + Ro) + AiωtRo + ωt ( RiA )]}

Rz Rz

………………………(4.2)

equation 4.2 has second order terms which equation 2.1 does not

have. Other than that equation 4.2 provides more or less same

characteristics of equation 2.1.

resistances on the gain equation 4.2. To do this again we will take

help of MATLAB.

topology – 1 with their values which are used as the initial input of

the MATLAB program to obtain bode plot.

Bandwidth of the current amplifier, ωt=1000 Hz

100

Feedback resistance Rf =100 Ω

Input resistance Ri =20Ω

Resistance at node Z, Rz =50KΩ

Capacitance at node Z, Cz =1pF

Input resistance of the current amplifier, RiA =5Ω

obtained the bode plot shown below.

Now we will vary the input resistance Ri. The bode plot

below shows the variation of Ri with the other parameters remain

unchanged as defined initially. Used values of the input resistance

Ri in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

101

Now we will vary the feedback resistance Rf. The bode plot

below shows the variation of Rf with the other parameters remain

unchanged as defined initially. Used values of the feedback

resistance Rf in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

102

Now we will vary the output resistance Ro. The bode plot

below shows the variation of Ro with the other parameters remain

unchanged as defined initially. Used values of the output resistance

Ro in the bode plot are 10Ω, 100Ω, 1kΩ, 10kΩ.

103

Our observation on the above bode plots found that for the

variation of input resistance Ri there is no variation in the 3dB

bandwidth. But constant bandwidth is not available for the

variation the other external resistances. This supports our previous

comments on the gain bandwidth behavior of the toplogy-1, which

we did by observing the gain equation.

the appendix – B.5.

104

4.5 Conclusion

design are provided in the appendix – 3. The simulation of larger

circuits may not always converge to the end point. The simulator

of the PSpice uses some iterative numerical methods. These

iterations may not converge all the times. In this case we may

converge to the end point if we reduce the analysis time for

transient analysis or change other different parameters of the

circuit. Use of “.OPTION STEPGMIN” is also a good ploy.

105

Chapter – 5

bandwidth behavior in four possible configurations these are as

following -

in voltage amplifier configuration.

*Amplifying element is voltage amplifier and feedback amplifier is

in current gain configuration.

*Amplifying elements are voltage and current amplifier and

feedback amplifier is in transimpedance configuration.

bandwidth product in the case of the voltage gain configuration

when the amplifying element is current amplifier by theoretical

analysis and the results achieved by software simulation. Further

exploration is required for the CMOS design of this topology to

obtain accurate result.

106

found a term (not equal for each topology) is present in each

topology affecting the 3dB bandwidth. The effect of these terms

can be minimized by using a special set of values of the parameters

concerning the topology. The software simulation can also be done

in the similar manner as described for the first case. That means

further exploration can be carried on for the last three topologies.

to prove the gain independent bandwidth in these four cases by

hardware implementation. In future hardware implementation can

be accomplished basing on the theories we derived in this paper,

which was our desired goal.

experimentally, based on the variable gain bandwidth properties

and constant bandwidth when the transconductance configuration

acts as the feedback amplifier and the current and voltage amplifier

as the amplifying element.

107

5.2 Conclusion

proposed topology – 1 practically with MOS devices. But

collection of all the MOS devices having our desired aspect ratio

from the market is quite difficult. Then we tried to collect the

CCII+ IC from the market. But we also failed to collect it. We

believe that more study and research on the way we tried to obtain

constant band width will lead to the desired success. Then the

design can also be implemented in a single IC by CMOS

technology.

108

Bibliography

[1] Sharker,Md. Ataur Rahman, “Nobel Design Approaches for

Low voltage CMOS Current Feedback and Transconductance

Feedback Amplifiers, August 2004.

Linear Integrated Circuits”, 6th ed. Prentice Hall, New Jersey,

2001.

Prentice Hall,

New Delhi, 1999.

and Digital Circuits and Systems”, fourth reprint ed. McGraw Hill,

India, 1992.

and Circuit Theory”, sixth edition, Prentice Hall of India,1997.

fifth edition,oxford university press, 2005-2006.

“Analysis and Design of Analog Integrated circuits”, fourth edition.

Jhon Wiely & sons Ltd

topology for low voltage CMOS current feedback amplifiers,”

IEEE Transactions on Circuits and

Systems II: Analog and Digital Signal Processing, (in press), 2004.

109

the transconductance feedback amplifiers,” IEEE Transactions on

Circuits and

Systems II: Analog and Digital Signal Processing.

Application Note 9420.1, Intersil Corporation, April 1995.

Integrated Circuits, 3rd ed. McGraw Hill, Boston, 2002.

amplifier design,”

International Journal of Electronics, vol. 73, pp. 573–583,

September 1992.

independence in feedback amplifiers,” International Journal of

Electrical Engineering Education, vol. 39, pp. 20–30, January 2002.

dominant pole

compensation,” International Journal of Electrical Engineering

Education,

vol. 36, pp. 91–101, April 1999.

implementation,” Electronics

Letters, vol. 20, pp. 990–991, 1984.

Pennisi,”Cmos Current Amplifiers”.

110

Appendix A

Formula Derivations

Inverting Configuration:

configuration.

Ri

Feedback current, if = Vo ;…………………...…………………………………...(2)

Rf

111

iin + if + ix = 0

⇒ ix = −(iin + if )

⇒ ix = −(Vin + Vo )

Ri Rf

…………………………………………(3)

iiA = ((1/ SCz)|| Rz) × ix

RiA + ((1/ SCz)|| Rz)

Rz

= 1+ SCzRz × ix

RiA + Rz

1+ SCzRz

= Rz × ix

( RiA + Rz) + SCzRzRiA

= 1 × ix

R

(1+ ) + SCzRiA

iA

Rz

……………….....………………………………….(4)

that RiA << Rz. So we can neglect (RiA / Rz) from equation – 4.

∴From equation – 2 :

iiA ≈ 1 × ix ………………………………(5)

1+ SCzRiA

The output resistance (Rio) of the current amplifier is very high, so

considered it as an open circuit.

∴Output current,

iout ≈ Ai(S )iiA

………………………………………………………(6)

= Ai(S )ix

1+ SCzRiA

112

And,

iout = io + if

⇒ io = iout − if

………………………………………………………………….(7)

Vo = Ro × io

= Ro(iout − if )

[From equation - 7]

1+ SCzRiA

Ai(S )

= Ro ×[ {−(Vin + Vo )} − Vo ]

1+ SCzRiA Ri Rf Rf

[From equation–3 & 2]

Ai(S ) Ro Ai(S ) Ro

⇒ Vo ×[1+ + Ro ] = −Vin ×

Rf (1+ SCzRiA) Rf Ri(1+ SCzRiA)

Ai(S ) Ro

⇒ Vo = − Ri(1+ SCzRiA)

Vin [ Rf (1+ SCzRiA) + Ai(S ) Ro + Ro(1+ SCzRiA) ]

Rf (1+ SCzRiA)

Ai(S ) RoRf

=−

Ri{Rf (1+ SCzRiA) + Ai(S ) Ro + Ro(1+ SCzRiA)}

Ai(S ) RoRf

=− ………………(8)

Ri{( Rf + Ro) + Ai(S ) Ro + ( Rf + Ro)(1+ SCzRiA)}

113

consider SCzRiA is close to zero and negligible. Then equation –

(8) becomes –

Vo ≈ − Ai(S ) RoRf ……………………………….(9)

Vin Ri{( Rf + Ro) + Ai(S ) Ro}

off model, given by –

Ai(S ) = Aiωt …………………………………………………...….(10)

S + ωt

Aiωt × RoRf

Gv = Vo = − S + ωt

Vin Ri{( Rf + Ro) + Aiωt × Ro}

S + ωt

=− AiωtRoRf

Ri{(S + ωt )( Rf + Ro) + AiωtRo}

…………….…………………….(11)

We know that at the 3dB point the real part and the imaginary part

of the gain equation will become equal.

⇒ ω ( Rf + Ro) = ωt ( Rf + Ro) + AiωtRo [Putting S=jω]

⇒ f ( Rf + Ro) = ft ( Rf + Ro) + Ai ⋅ ft ⋅ Ro

⇒ f = ft + Ai ⋅ ft ⋅ Ro

( Rf + Ro)

∴For the inverting configuration the 3dB bandwidth is -

f = ft{1+ Ai ⋅ Ro } ………………………………………………………..(12)

Rf + Ro

114

Inverting Configuration:

configuration.

Rf

∴Using KCL at node –X ,

iin + if + ix = 0

⇒ ix = −(iin + if )

⇒ ix = −(iin + Vo )

Rf

…………………………………………(14)

that is - we assumed input resistance (RiA) of the voltage

amplifier tends to infinity and output resistance (RoA) tends to

zero. So we considered that a negligible amount of current

passes through input resistance (RiA) and the voltage drop

across the output resistance (R oA ) is also negligible.

115

voltage across ((1/ SCz ) || Rz ) .

negligible –

= −(iin + Vo ) × Rz ………………………………………..(15)

Rf 1+ SCzRz

Let the gain of the voltage amplifier is Ao(S).

output voltage (VAo) can be given as –

RzAo(S )

= −(iin + Vo ) × ………………………………………….(16)

Rf 1+ SCzRz

is - we assumed input resistance (Rig) and output resistance (Rog) of

the transconductance block tends to infinity. So we considered that

a negligible amount of current passes through both the input

resistance (RiA) and the output resistance (RoA). Let the gain of the

transconductance block is gm(S).

RzAo(S ) gm(S )

= −(iin + Vo ) × ………………………………………………..(17)

Rf 1+ SCzRz

116

negligible, we can write KCL at the output node as following

igo = io + if

⇒ io = igo − if

RzAo(S ) gm(S ) Vo Ro

⇒ io = −(iin + Vo Ro ) × ( )− [From equation (17) & (13)]

Ro Rf 1+ SCzRz Ro Rf

RzAo(S ) gm(S )

⇒ io = −(iin + io × Ro ) × ( ) − io × Ro [∵io = Vo ]

Rf 1+ SCzRz Rf Ro

RzAo(S ) gm(S ) Ro RzAo(S ) gm(S )

⇒ io{1+ Ro × + } = −iin × ( )

Rf 1+ SCzRz Rf 1+ SCzRz

RzAo(S ) gm(S )

i

⇒ =−

o 1+ SCzRz

iin Rf (1+ SCzRz) + RoRzAo(S ) gm(S ) + Ro(1+ SCzRz)

Rf (1+ SCzRz)

RfRzAo(S ) gm(S )

⇒ io = − ……………(18)

iin Rf (1+ SCzRz) + RoRzAo(S ) gm(S ) + Ro(1+ SCzRz)

roll-off model, given by –

S + ωt

larger than the transconductance block. For the transconductance

block we can take gm(S) = gm.

117

Gi = io = − RfRzAoωtgm

iin Rf (1+ SCzRz)(S + ωt ) + RoRzAoωtgm + Ro(1+ SCzRz)(S + ωt )

=− RfRzAoωtgm

RoRzAoωtgm + ωt ( Rf + Ro) + S (1+ ωtCzRz)( Rf + Ro) + S 2CzRz ( Rf + Ro)

………………………...(20)

Gi = − RfRzAoωtgm

RoRzAoωtgm + ωt ( Rf + Ro) + jω (1+ ωtCzRz)( Rf + Ro) − ω 2CzRz( Rf + Ro)

..............................……(21)

We know that at the 3dB point the real part and the

imaginary part of the gain equation will become equal.

( Rf + Ro)

−(1+ ωtCzRz) ± (1+ ωtCzRz)2 + 4CzRz ×{ωt + RoRzAoωtgm}

( Rf + Ro)

⇒ω =

2CzRz

118

( Rf + Ro)

⇒f=

4π CzRz

………………………………(22)

Inverting Configuration:

configuration.

Feedback current,

if = Vo ; ……………………………………………...(23)

Rf

119

iin + if + ix = 0

⇒ ix = −(iin + if )

⇒ ix = −(iin + Vo )

Rf

…………………………..……………………(24)

Cz and the resistance at the Z node is Rz.

that is - we assumed input resistance (RiA) of the voltage

amplifier tends to infinity and output resistance (RoA) tends to

zero. So we considered that a negligible amount of current

passes through input resistance (RiA) and the voltage drop

across the output resistance (RoA) is also negligible.

voltage across ((1/ SCz )|| Rz) .

negligible –

VA = ((1/ SCz)|| Rz) × ix

= −(iin + Vo ) × Rz …………………………………………..(25)

Rf 1+ SCzRz

As voltage drop across the output resistance (RoA) is negligible,

output voltage (Vo) can be given as –

Vo = Ao(S )VA

RzAo(S )

= −(iin + Vo ) × ………………………………………….(26)

Rf 1+ SCzRz

120

RzAo(S ) RzAo(S )

⇒ Vo{1+ } = −iin ×

Rf (1+ SCzRz) 1+ SCzRz

⇒ Vo{ } = −iin ×

Rf (1+ SCzRz) 1+ SCzRz

RfRzAo(S )

⇒ Vo = − ………………………………….(27)

iin Rf (1+ SCzRz) + RzAo(S )

off model, given by –

S + ωt

⇒ Rm = V o = − RfRzAoωt

iin Rf (1+ SCzRz)(S + ωt ) + RzAoωt

=− RfRzAoωt ………………….(29)

Rf ωt + RzAoωt + S 2 RfCzRz + SRf (1+ ωtCzRz)

Rm = Vo = − RfRzAoωt ……(30)

iin Rf ωt + RzAoωt − ω RfCzRz + jω Rf (1+ ωtCzRz)

2

We know that at the 3dB point the real part and the imaginary part

of the gain equation will become equal.

121

⇒ ω 2 RfCzRz + ω Rf (1+ ωtCzRz) −{ωt ( Rf + RzAo)} = 0

− Rf (1+ ωtCzRz) ± Rf 2 (1+ ωtCzRz)2 + 4CzRzRf ωt ( Rf + RzAo)

⇒ω =

2CzRzRf

− Rf (1+ 2π ftCzRz) ± Rf 2 (1+ 2π ftCzRz)2 + 8π ftCzRzRf ( Rf + RzAo)

⇒f=

4π CzRzRf

………..(31)

Inverting Configuration:

configuration.

Feedback current, if = Vo ;……………………………………………………...(32)

Rf

122

iin + if + ix = 0

⇒ ix = −(iin + if )

⇒ ix = −(iin + Vo )

Rf

………………………………...………………(33)

that is - we assumed input resistance (RiA) of the current

amplifier is small and output resistance (RoA) tends to infinity.

So we considered that a negligible amount of current passes

through output resistance (RoA).

RiA + ((1/ SCz)|| Rz)

Rz

= 1+ SCzRz × ix

RiA + Rz

1+ SCzRz

= Rz × ix

( RiA + Rz) + SCzRzRiA

= 1 × ix

R

(1+ ) + SCzRiA

iA

Rz

……………………………………..……….(34)

that RiA << Rz. So we can neglect (RiA / Rz) from equation -34.

∴From equation – 34 :

iiA ≈ 1 × ix ………………………………………………(35)

1+ SCzRiA

123

considered it as an open circuit.

∴Output current,

ioA ≈ Ai(S )iiA

= Ai(S )ix

1+ SCzRiA

………………..……………………………………(36)

- we assumed input resistance (Rig) and output resistance (Rog) of

the transimpedance block tends to Zero. So we considered that

voltage drop across the output resistance (RoA) is negligible. Let

the gain of the transimpedance block is Rm(S).

Vo = Rm(S ) × ioA

Ai(S )ix

= Rm(S ) ×

1+ SCzRiA

Rm(S ) Ai(S )

= −(iin + Vo ) ×

Rf 1+ SCzRiA

Rm(S ) Ai(S ) Rm(S ) Ai(S )

⇒ Vo{1+ } = −iin ×

Rf (1+ SCzRiA) 1+ SCzRiA

⇒ Vo{ } = −iin ×

Rf (1+ SCzRiA) 1+ SCzRiA

RfRm(S ) Ai(S )

⇒ Vo = − ……………………………………(37)

iin Rf (1+ SCzRiA) + Rm(S ) Ai(S )

off model, given by –

S + ωt

124

larger than the transimpedance block. For the transimpedance

block we can take Rm(S) = Rm.

Rm = Vo = − RfRmAiωt

iin Rf (1+ SCzRiA)(S + ωt ) + RmAiωt

=− RfRmAiωt ………………………(39)

Rf ωt + RmAiωt + S CzRiARf + SRf (1+ CzRiAωt )

2

Rm = − RfRmAiωt ………………..(40)

Rf ωt + RmAiωt − ω 2CzRiARf + jω Rf (1+ CzRiAωt )

imaginary part of the gain equation will become equal.

⇒ω =

2CzRiARf

− Rf (1+ 2π ftCzRiA) ± Rf 2 (1+ 2π ftCzRiA)2 + 8π ftCzRiARf ( Rf + RmAi)

⇒f=

4π CzRiARf

…………(41)

125

Appendix B

clear all

Prm=input('Enter Ai, Wt, Ro, Rf, Ri : ');

[M0,N0,N1]=params_config1(Prm);

g=tf([M0],[N1 N0]);

bode(g)

grid on

figure

rstr=Prm(5);

for x=1:1:4

Prm(5)=10^(x);

[M0_,N0_,N1_]=params_config1(Prm);

g=tf([M0_],[N1_ N0_]);

bode(g)

title('Varing Ri');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

Prm(5)=rstr;

rstr1=Prm(4);

figure

for m=1:1:4

Prm(4)=10^(m);

[M0_1,N0_1,N1_1]=params_config1(Prm);

g=tf([M0_1],[N1_1 N0_1]);

bode(g)

title('Varing Rf');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

126

Prm(4)=rstr1;

figure

for n=1:1:4

Prm(3)=10^(n);

[M0_2,N0_2,N1_2]=params_config1(Prm);

g=tf([M0_2],[N1_2 N0_2]);

bode(g)

title('Varing Ro');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

function[M0,N0,N1]=params_config1(Prm)

M0=-1*(Prm(1)*Prm(2)*Prm(3)*Prm(4))/Prm(5);

N0=Prm(2)*(Prm(4)+Prm(3)+Prm(1)*Prm(3));

N1=Prm(4)+Prm(3);

clear all

Prm=input('Enter Ao, Wt, Gm, Cz, Rz, Ro, Rf : ');

[M0,N0,N1,N2]=params_config2(Prm);

g=tf([M0],[N2 N1 N0]);

bode(g)

grid on

figure

rstr1=Prm(7);

for m=1:1:4

Prm(7)=10^(m);

[M0_1,N0_1,N1_1,N2_1]=params_config2(Prm);

g=tf([M0_1],[N2_1 N1_1 N0_1]);

bode(g)

title('Varing Rf');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

Prm(7)=rstr1;

127

figure

for n=1:1:4

Prm(6)=10^(n);

[M0_2,N0_2,N1_2,N2_2]=params_config2(Prm);

g=tf([M0_2],[N2_2 N1_2 N0_2]);

bode(g)

title('Varing Ro');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

function[M0,N0,N1,N2]=params_config2(Prm)

M0=-1*Prm(7)*Prm(5)*Prm(1)*Prm(2)*Prm(3);

N0=Prm(6)*Prm(5)*Prm(1)*Prm(2)*Prm(3)+Prm(2)*(Prm(7)+Prm(6));

N1=(1+Prm(4)*Prm(5)*Prm(2))*(Prm(7)+Prm(6));

N2=Prm(4)*Prm(5)*(Prm(7)+Prm(6));

clear all

Prm=input('Enter Ao, Wt, Cz, Rz, Rf : ');

[M0,N0,N1,N2]=params_config3(Prm);

g=tf([M0],[N2 N1 N0]);

bode(g)

grid on

figure

for m=1:1:4

Prm(5)=10^(m);

[M0_1,N0_1,N1_1,N2_1]=params_config3(Prm);

g=tf([M0_1],[N2_1 N1_1 N0_1]);

bode(g)

title('Varing Rf');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

128

function[M0,N0,N1,N2]=params_config3(Prm)

M0=-1*Prm(5)*Prm(4)*Prm(1)*Prm(2);

N0=Prm(2)*(Prm(5)+Prm(4)*Prm(1));

N1=Prm(5)*(1+Prm(3)*Prm(4)*Prm(2));

N2=Prm(3)*Prm(4)*Prm(5);

clear all

Prm=input('Enter Ai, Wt, ,Rm, Cz, Ria, Rf : ');

[M0,N0,N1,N2]=params_config4(Prm);

g=tf([M0],[N2 N1 N0]);

bode(g)

grid on

figure

for m=1:1:4

Prm(6)=10^(m);

[M0_1,N0_1,N1_1,N2_1]=params_config4(Prm);

g=tf([M0_1],[N2_1 N1_1 N0_1]);

bode(g)

title('Varing Rf');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

function[M0,N0,N1,N2]=params_config4(Prm)

M0=-1*Prm(6)*Prm(3)*Prm(1)*Prm(2);

N0=Prm(2)*(Prm(6)+Prm(3)*Prm(1));

N1=Prm(6)*(1+Prm(4)*Prm(5)*Prm(2));

N2=Prm(4)*Prm(5)*Prm(6);

neglected terms).

clear all

Prm=input('Enter Ai, Wt, Ro, Rf, Ri ,Ria ,Rz ,Cz: ');

[M0,N0,N1,N2]=params_config1(Prm);

g=tf([M0],[N2 N1 N0]);

bode(g)

129

grid on

figure

rstr=Prm(5);

for x=1:1:4

Prm(5)=10^(x);

[M0_,N0_,N1_,N2_]=params_config1(Prm);

g=tf([M0_],[N2_ N1_ N0_]);

bode(g)

title('Varing Ri');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

Prm(5)=rstr;

rstr1=Prm(4);

figure

for m=1:1:4

Prm(4)=10^(m);

[M0_1,N0_1,N1_1,N2_1]=params_config1(Prm);

g=tf([M0_1],[N2_1 N1_1 N0_1]);

bode(g)

title('Varing Rf');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

Prm(4)=rstr1;

figure

for n=1:1:4

Prm(3)=10^(n);

[M0_2,N0_2,N1_2,N2_2]=params_config1(Prm);

g=tf([M0_2],[N2_2 N1_2 N0_2]);

bode(g)

title('Varing Ro');

grid on

hold on

end

legend('1st','2nd','3rd','4th',4);

function[M0,N0,N1,N2]=params_config1(Prm)

M0=-1*(Prm(1)*Prm(2)*Prm(3)*Prm(4))/Prm(5);

N0=Prm(2)*(Prm(4)+Prm(3))+Prm(1)*Prm(2)*Prm(3)+Prm(2)*(Prm(6)/Prm(7));

N1=Prm(4)+Prm(3)+(Prm(6)/Prm(7))+Prm(8)*Prm(6);

N2=Prm(8)*Prm(6);

130

Appendix C

Schematic Netlists

generation current conveyor (CCII+)

************************************************************************

V_V1 $N_0001 0 700mV

R_R1 0 $N_0002 1k

M_M1 $N_0004 chk1 $N_0003 $N_0003 MbreakN

+ L=1um

+ W=100um

M_M2 $N_0005 0 $N_0003 $N_0003 MbreakN

+ L=1um

+ W=100um

M_M3 $N_0004 $N_0004 $N_0006 $N_0006 MbreakP

+ L=1um

+ W=40um

M_M4 $N_0005 $N_0004 $N_0006 $N_0006 MbreakP

+ L=1um

+ W=40um

M_M5 $N_0003 $N_0001 0 0 MbreakN

+ L=1um

+ W=20um

M_M6 $N_0006 $N_0005 $N_0007 $N_0007 MbreakN

+ L=1um

+ W=45um

M_M7 $N_0007 $N_0001 0 0 MbreakN

+ L=1um

+ W=10um

M_M8 $N_0008 $N_0006 chk1 chk1 MbreakN

+ L=1um

+ W=2.7um

131

+ L=1um

+ W=5um

M_M10 chk1 $N_0005 $N_0006 $N_0006 MbreakP

+ L=1um

+ W=60um

M_M11 chk1 $N_0007 0 0 MbreakN

+ L=1um

+ W=20um

M_M12 $N_0002 $N_0005 $N_0006 $N_0006 MbreakP

+ L=1um

+ W=60um

M_M13 $N_0002 $N_0007 0 0 MbreakN

+ L=1um

+ W=20um

C_C1 $N_0005 $N_0008 0.5pF

I_I1 chk1 0 DC 0A AC 0.7071mA

+SIN 0A 1mA 5kHz 0 0 0

V_V3 $N_0006 0 2V

.lib

.ac LIN 10000 10HZ 20GHZ

.tran 100ns 1ms

.OP

.probe

.END

************************************************************************

M_M8 $N_0001 $N_0001 +V +V MbreakP

+ L=1u

+ W=20u

M_M10 $N_0002 $N_0001 +V +V MbreakP

+ L=1u

+ W=80u

M_M9 $N_0003 $N_0001 +V +V MbreakP

+ L=1u

132

+ W=20u

M_M2 $N_0001 $N_0003 $N_0004 $N_0004 MbreakN

+ L=1u

+ W=20u

M_M1 $N_0006 $N_0005 $N_0004 $N_0004 MbreakP

+ L=1u

+ W=20u

M_M6 $N_0005 $N_0006 -V -V MbreakN

+ L=1u

+ W=20u

M_M5 $N_0006 $N_0006 -V -V MbreakN

+ L=1u

+ W=20u

M_M7 $N_0002 $N_0006 -V -V MbreakN

+ L=1u

+ W=80u

I_I1 $N_0004 0 DC 0mA AC 0.7071mA

+SIN 0V 1mA 100Hz 0 0 0

M_M3 $N_0005 $N_0005 0 0 MbreakP

+ L=1u

+ W=20u

M_M4 $N_0003 $N_0003 0 0 MbreakN

+ L=1u

+ W=20u

R_R1 0 $N_0002 5k

V_V2 0 -V 5V

V_V1 +V 0 5V

.lib

.tran 1us 0.1s

.probe

.OP

.END

133

topology – 1 for inverting configuration with the

MOS device parameters used latter.

************************************************************************

*spice option:

.width out=80

.OPTION STEPGMIN

C_C2 $N_0001 $N_0002 0.5pF

M_M16 $N_0003 $N_0003 +V +V penh

+ L=1um

+ W=40um

M_M17 $N_0001 $N_0003 +V +V penh

+ L=1um

+ W=40um

M_M19 +V $N_0001 $N_0004 $N_0004 nenh

+ L=1um

+ W=45um

V_V4 $N_0005 0 700mV

M_M18 $N_0006 $N_0005 0 0 nenh

+ L=1um

+ W=20um

M_M20 $N_0004 $N_0005 0 0 nenh

+ L=1um

+ W=10um

M_M15 $N_0001 0 $N_0006 $N_0006 nenh

+ L=1um

+ W=100um

M_M26 $N_0007 $N_0004 0 0 nenh

+ L=1um

+ W=20um

M_M25 $N_0007 $N_0001 +V +V penh

+ L=1um

+ W=60um

M_M34 $N_0008 $N_0008 0 0 nenh

+ L=1u

+ W=20u

M_M35 $N_0009 $N_0009 0 0 penh

+ L=1u

+ W=20u

M_M30 $N_0010 $N_0009 $N_0007 $N_0007 penh

+ L=1u

+ W=20u

M_M27 $N_0011 $N_0008 $N_0007 $N_0007 nenh

134

+ L=1u

+ W=20u

M_M29 $N_0011 $N_0011 +V +V penh

+ L=1u

+ W=20u

V_V7 +V 0 5V

M_M24 chk1 $N_0004 0 0 nenh

+ L=1um

+ W=20um

M_M22 $N_0002 0 chk1 chk1 penh

+ L=1um

+ W=5um

M_M21 $N_0002 +V chk1 chk1 nenh

+ L=1um

+ W=2.7um

M_M23 chk1 $N_0001 +V +V penh

+ L=1um

+ W=60um

M_M14 $N_0003 chk1 $N_0006 $N_0006 nenh

+ L=1um

+ W=100um

M_M28 $N_0008 $N_0011 +V +V penh

+ L=1u

+ W=20u

M_M36 $N_0012 $N_0011 +V +V penh

+ L=1u

+ W=80u

R_Rload 0 $N_0012 0.5k

R_Rfeedback chk1 $N_0012 1k

R_Rgncntrl $N_0013 chk1 100

V_V6 $N_0013 0 DC 0v AC 0.7071v

+SIN 0v 1v 5kHz 0 0 0

M_M31 $N_0009 $N_0010 0 0 nenh

+ L=1u

+ W=20u

M_M33 $N_0012 $N_0010 0 0 nenh

+ L=1u

+ W=80u

M_M32 $N_0010 $N_0010 0 0 nenh

+ L=1u

+ W=20u

*model specification:

*MCE 3 Micron CMOS processes parameters-process 2

*N channel typ

.model nenh nmos level=2 vto=0.85 kp=30e-6 tox=470e-10 nsub=38e14

135

mj=0.5 mjsw=0.33 pb=0.81

*p channel typ

.model penh pmos level=2 vto=-0.85 kp=12e-6 tox=470e-10 nsub=8.7e14

+ld=0.5e-6 uo=200 uexp=0.18 vmax=12e4 neff=4.0 delta=2.0

+cj=100e-6 cjsw=180e-12 mj=0.5 mjsw=0.33 pb=0.7

.ac DEC 10000 10 10000GHz

.OP

.probe

.END

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