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Institute of Engineering Studies (IES,Bangalore) Analog Electronics Old GATE ECE

GATE-1999 One Mark Questions


1. The first dominant pole encountered in the frequency response of a
compensated op-amp is approximately at
a. 5 Hz b. 10 kHz
c. 1 MHz d. 100 MHz

2. Negative feedback in an amplifier


a. reduce gain
b. increase frequency and phase distortions
c. reduces bandwidth
d. increases noise

3. In the cascade amplifier shown in the figure, if the common-emitter stage (Q1)
has a transconductange gm1, and the common base stage (Q2) has a
transcodnuctance gm2 then the overall transconductance g(=i0/vi) of the cascade
amplifier is
Q2 ← io
Vo

RL

Vi Q1

a. gm1
b. gm2
c. gm1/2

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d. gm2/2

4. Crossover distortion behaviour is characteristic of


a. Class A output stage b. Class B output stage
c. Class AB output stage d. Common-base output stage

GATE-1999 Two Marks Questions


5. An npn transistor (with C = 0.3 pF) has a unit-gain cutoff frequency fT of 400
MHz at a dc bias current Ic = 1mA. The value of its Cµ (in pF) is approximately
(VT = 26 mV)
a. 15 b. 30
c. 50 d. 96

6. An amplifier has an open-loop gain of 100, an input impedance of 1kΩ and an


output impedance of 100Ω. A feedback network with a feedback factor of 0.99 is
connected to the amplifier in a voltage series feedback mode. The new input and
output impedances, respectively are.
a. 10 Ω and 1 Ω b. 10 Ω and 10 Ω
c. 100 k Ω and 1 Ω d. 100 kΩ and 1 k Ω

7. A dc power supply has a no-load voltage of 30 V, and a full-load voltage of 25


V at a full-load current of 1A. Its output resistance and load regulation,
respectively are
a. 5 Ω and 20% b. 25 Ω and 20%
c. 5 Ω and 16.7% d. 25 Ω and 16.7%

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8. An amplifier is assumed to have a single-pole high-frequency transfer function.


The rise time of its output response to a step function input is 35 nsec. The upper –
3 dB frequency (in MHz) for the amplifier to a sinusoidal input is approximately at
a. 4.55 b. 10
c. 20 d. 28.6

GATE-2000 One Mark Questions


9. In the differential amplifier of the figure, if the source resistance of the current
source IEE is infinite, then the common-mode gain is
a. zero
b. infinite
c. indeterminate

d.

R R

V in1
Vin2

↓ IEEE
-VEE

10. In the circuit of the figure V0 is

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+15V

V0
+ 1V
R
-15V

a. -1V b. 2V
c. + 1V d. + 15V

11. Introducing a resistor in the emitter of a common amplifier stabilizes the dc


operating point against variations in
a. only the temperature b. only the β of the transistor
c. both temperature and β d. none of the above

12. The current gain of a bipolar transistor drops at high frequencies because of
a. transistor capacitances
b. high current effects in the base
c. parasitic inductive elements
d. the Early effect

13. If the op-amp in the figure is ideal, the v0 is

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C
Sin t

Sin t
C

a. zero b. (V1-V2) sinωt


c. – (V1 + V2 ) sinωt d. (V1 + V2) sinωt

14. The configuration of the figure is

R C

a. precision integrator b. Hartely oscillator


c. Butterworth high pass filter d. Wien-bridge oscillator

15. Assume that the op-amp of the figure is ideal. If Vi is a triangular wave then v0
will be

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a. square wave b. triangular wave


c. parabolic wave d. sine wave

16. The most commonly used amplifier in sample and hold circuits is
a. a unity gain inverting amplifier
b. a unity gain non-inverting amplifier
c. an inverting amplifier with a gain of 10
d. an inverting amplifier with a gain of 100

GATE-2000 Two Marks Questions


17. In the circuit of the figure, assume that the transistor is in the active region. It
has a large β and its base emitter voltage is 0.7V. the value of Ic is
15V

Rc
10K
↓ Ic

5K
430

a. Indeterminate since Rc is not given

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b. 1mA
c. 5 mA
d. 10 mA

18. If the op-amp in the figure has an input offset voltage of 5mV and an open-
loop voltage gain of 10,000 then v0 will be
+15V

-15V

a. 0V b. 5mV
c. +15V or – 15V d. +50V or – 50V

GATE-2001 One Mark Questions


19. The current gain of a BJT is
a. gmro b. gm/r0
c. gmrπ d. gm/rπ

20. The ideal OP-AMP has the following characteristics.


a. Ri = ∞, A= ∞, R0 = 0 b. Ri = 0, A= ∞, R0 = 0
c. R1 = ∞, A= ∞, R0 = ∞ d. Ri = 0, A= ∞, R0 = ∞

21. Consider the following two statements:


Statement 1:
A stable multivibrator can be used for generating square wave.

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Statement 2:
Bistable multivibrator can be used for storing binary information.
a. Only statement 1 is correct
b. Only statement 2 is correct
c. Both the statements 1 and 2 are correct
d. Both the statements 1 and 2 are incorrect

GATE-2001 Two Marks Questions


22. An npn BJT has gm = 38 mA/V, Cµ = 10-14 F, Cπ = 10-13 F, and DC current gain
β0 = 0-. For this transistor fT and fβ are
a. fT = 1.64 x 108 Hz and fβ = 1.47 x 1010 Hz
b. fT = 1.47 x 1010 Hz and fβ = 1.64 x 108 Hz
c. fT = 1.33 x 1012 Hz and fβ = 1.47 x 1010 Hz
d. fT = 1.47 x 1010 Hz and fβ = 1.33 x 1012 Hz

23. The transistor shunt regulator shown in the figure has a regulated output
voltage of 10V, when the input varies from 20V to 30V. the relevant parameters
for the zener diode and the transistor are: Vz = 9.5, VBE = 0.3V β = 99. neglect the
current through RB. then the maximum power dissipated in the zener diode (Pz)
and the transistor (PT) are
20

↓ Iz ↓I
c

Vz
=10V
+
20-30 V RB VBE -

a. Pz = 75 mW, PT = 7.9 W

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b. Pz = 85 mW, PT = 8.9 W
c. Pz = 95 mW, PT = 9.9 W
d. Pz = 115 mW, PT = 11.9 W

24. The oscillator circuit shown in the figure is


-

Lc

L=10 H
Cc

C1 =2pF C2 =2pF

Ce

a. Hartley oscillator with foscillation = 79.6 MHz


b. Colpitts oscillator with foscillation = 50.3 MHz
c. Hartley oscillator with foscillation = 159.2 MHz
d. Colpitts oscillator with foscillation = 159.2 MHz

25. The inverting OP-AMP shwn in the figure has an open-loop gain of 100. the
closed-loop gain V0/Vs is

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=10K

=1K
+
-

a. – 8 b. -9
c. -10 d. -11

26. In the figure assume the OP-AMPs to be ideal. The output v0 of the circuit is:

10mH 10 F

10
+ 100
1 -
=10cos (100t)
2 3

a. 10 cos (100t) b.

c. d.

GATE-2002 One Mark questions


27. In a negative feedback amplifier using voltage series (i.e. voltage smapling,
series mixing) feedback,

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a. Ri decreases and R0 decreases


b. Ri decreases and R0 increases
c. Ri increases and R0 decreases
d. Ri increases and R0 increases
(Ri and R0 denote the input and output resistance respectively)

28. A 741-type opamp has a gain-bandwidth product of 1 MHz. A non inverting


amplifier using this opamp and having a voltage gain of 20dB will exhibit a 3-dB
bandwidth of
a. 50 KHz b. 100 KHz
c. 1000/17 KHz d/ 1000/7.07 KHz

29. Three identical RC-coupled transistor amplifiers are cascaded. If each of the
amplifiers has a frequency responses as shown in the figure, the overall frequency
response is as given in

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GATE-2002 Two Marks Questions


30. An amplifier using an opam with a slew-rate SR=1 V/µsec has a gain of 40dB.
if this amplifier has to faithfully amplifiy sinusoidal signals from dc to 20 KHz
without introducing any slew-rate induced distortion, then the input signal level
must not exceed.
a. 795 mV b. 395 mV
c. 79.5 mV d. 39.5 mV

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31. The circuit in the figure employs positive feedback and is intended to generate

sinusoidal osicallation. If at a frequency f0 B(f)= then to sustain


oscillation at this frequency.

+↑

(f)
+ Network
-↓
B(f)
- (f)

a. R2 = 5R1 b. R2 = 6R1
c. R2 = R1/6 d. R2 = R1/5

32. A Zener diode regulator in the figure is to be designed to meet the


specifications: IL = 10mA, V0 = 10V and Vin varires from 30 V to 50V. The zener
diode has Vz = 10V and Izk (knee current)= 1mA For satisfactory operation
+↑ ↑
IL = 10mA
Iz ↓

Dz


- ↓

a. R ≤ 1800 Ω b. 2000 Ω R ≤ 22000 Ω


c. 3700 Ω ≤ R ≤ 4000 Ω d. R > 4000 Ω

33. The voltage gain Av = v0/vt of the JFET amplifier shown in the figure is

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VDD = +10V
↓ ID=1mA
RD
(3K ) C2

C1 +

+

RG Rs Cs
(1M ) (2.5K )
-

IDss = 10 mA
(Assume C1, C2 and Cs to be very large)
a. +18 b. -18
c. + 6 d. -6

34. Consider the following statements in connection with the CMOS inverter in
the figure, where both the MOSFETs are of enhancement type and both have a
thresh old voltage of 2V.
Statement 1: T1 conducts when V1 ≥ 2V.
Statement 2: T1 is always in saturation when V0 = 0V.
+ 5V

→ T2


T1

Which of the following is correct?

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a. Only statement 1 is TRUE


b. Only Statement 2 is TRUE
c. Both the statements are TRUE
d. Both the Statements are FALSE.

GATE-2003 One Mark Questions


35. Choose the correct match for input resistance of various amplifier
configuration shown below.
Configuration Input resistance
CB: Common Base LO: Low
CC: Common Collector MO: Moderate
CE: Common Emitter HI: High
a. CB-LO, CC-MO, CE-HI b. CB-LO, CC-HI, CE-MO
c. CB-MO, CC-HI, CE-LO d. CB-HI, CC-LO, CE-MO

36. The circuit shown in the figure is best described as a

~ Output

a. bridge rectifier b. ring modulator


c. frequency discriminatory d. voltage doubler

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37. If the input to the ideal comparator shown in the figure is a sinusoidal signal of
8V (peak to peak) without any DC component, then the output of the comparator
has a duty cycle of

Input
Output
Vref =2V

a. 1/2 b. 1/3
c. 1/6 d. 1/12

38. If the differential voltage gain and the common mode voltage gain of a
differential amplifier are 48 dB and 2 dB respectively, then its common mode
rejection ratio is
a. 23 dB b. 25 dB
c. 46 dB d. 50 dB

39. Generally, the gain of a transistor amplifier falls at high frequencies due to the
a. internal capacitances of the device
b. coupling capacitor at the input
c. skin effect
d. coupling capacitor at the output
GATE-2003 Two Marks Questions
40. An amplifier without feedback has a voltage gain of 50, input resistance of
1KΩ and output resistance of 2.5 KΩ. The input resistance of the current-shunt
negative feedback amplifier using the above amplifier with a feedback factor of
0.2 is
a. 1/11KΩ b. 1/5 KΩ
c. 5 KΩ d. 11K Ω

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41. In the amplifier circuit shown in the figure, the values of R1 and R2 are such
that the transistor is operating at VCE = 3V and IC = 1.5mA when its β is 150. for a
transistor with β of 200, the operating point (VCE, IC) is

a. (2V, 2mA) b. (3V, 2mA)


c. (4V, 2mA) d. (4V, 1mA)

42. The oscillator circuit shown in the figure has an ideal inverting amplifier. Its
frequency of oscillation (in Hz) is

C C C

R R R

a. b.

c. d.

43. The output voltage of the regulated power supply shown in the figure is

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1K
15V DC
Unregulated
Power source Vz=3V

40K Regulated
20K DC Output
-

a. 3V b. 6V
c. 9V d. 12 V

44. The action of a JFET in its equivalent circuit can best be represented as a
a. Current Controlled Current Source
b. Current Controlled Voltage Source
c. Voltage Controlled Voltage Source
d. Voltage Controlled Current Source

45. If the op-amp in the figure is ideal, the output voltage V out will be equal to

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5K

1K
2V
3V
1K
8K

a. 1V b. 6V
c. 14 V d. 17V

46. Three identical amplifiers with each one having a voltage gain of 50, input
resistance of 1KΩ and output resistance of 250 Ω, are cascaded. The open circuit
voltage gain of the combined amplifier is
a. 49 dB b. 51 dB
c. 98 dB d. 102 dB

47. An ideal saw tooth voltage waveform of frequency 500 Hz and amplifier 3 V
is generated by charging a capacitor of 2µ F in every cycle. The charging requires
a. constant voltage source of 3 V for 1 ms
b. constant voltage source of 3 V for 2 ms
c. constant current source of mA for 1 ms
d. constant current source of 3mA for 2 ms

GATE- 2004 One Mark Questions


48. An ideal op-amp is an ideal
a. voltage controlled current source
b. voltage controlled voltage source
c. current controlled current source

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d. current controlled voltage source

49. Voltage series feedback (also called series-shunt feedback) results in


a. increase in both input and output impedances
b. decrease in both input and output impedances
c. increase in input impedance and decrease in output impedance
d. decrease in input impedance and increase in output impedance

50. The circuit in the figure is a


5K

R R

a. low-pass filter b. high-pass filter


c. band-pass filter d. band-reject filter

51. Assuming VCEsat= 0.2V and β = 50, the minimum base current (IB) required to
drive the transistor in the figure to saturation is
3V
↓I c

I 1K

B

a. 56 µA b.140 mA
c. 60 mA d. 3 mA

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GATE-2004 Two Marks Questions


52. A bipolar transistor is operating in the active region with a collector current of
1 MA. Assuming that the β of the transistor is 100 and the thermal voltage (VT) is
25 mV, the transconductance (gm) and the input resistance (rπ) of the transistor in
the common emitter configuration are
a. gm = 25mA/V and rπ = 15.625kΩ
b. gm = 40/V and rπ = 4.0kΩ
c. gm = 25mA/V and rπ = 2.5kΩ
d. gm = 40 mA/V and rπ = 2.5kΩ

53. The value of C required for sinusoidal oscillations of frequency 1 kHz in the
circuit of the figure is
1K 2.1K

1K

1K C

a. b. 2πµ F

c. d. 2 π √6 µ F

54. In the op-amp circuit given in the figure the load current iL is

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iL

a. b.

c. d.

55. In the voltage regulator shown in the figure the load current can vary from
100mA to 500 mA. Assuming that the zener diode is ideal (i.e. the Zener knee
current is negligibly small and zener resistance is zero in the breakdown region),
the value of R is
R

+
12V 5V
- Variable Load
100 to 500 mA

a. 7Ω b. 70 Ω
c. 70/3 Ω d. 14 Ω

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56. In a full-wave rectifier using two ideal diodes Vdc and Vm are the dc and peak
values of the voltage respectively across a resistive load. If PIV is the peak inverse
voltage of the diode, then the appropriate relationships for the rectifier are

a. b.

c. d.

GATE-2005 One Mark Questions

57. The effect of current shunt feedback in an amplifier is to


a. increase the input resistance and decrease the output resistance
b. increase both input and output resistances
c. decrease both input and output resistance
d. decrease the input resistance and increase the output resistance

58. the input resistance of Ri of the amplifier shown in the figure is

a. 30/4 kΩ b. 10 K kΩ
d. 40 kΩ d. infinite

59. The cascade amplifier is a multistage configuration of


a. CC-CB b. CE-CB
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c. CB-CC d. CE-CC
GATE- 2005 Two Marks Questions
60. For an npn transistor connected as shown in the figure VBE = 0.7 volts. Given
that reverse saturation current of the junction at room temperature 3000 K is 10-13
A, the emitter current is

↓I c

VBE

a. 30 mA b. 39 mA
c. 49 mA d. 20 mA

61. The voltage e0 indicated in the figure has been measured by an ideal voltmeter.
Which of the following can be calculated?
1M

e0

1M

a. Bias current of the inverting input only


b. Bias current of the inverting and non-inverting inputs only
c. Input offset current only
d. Both the bias-current and the input offset current

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62. The OP-amp circuit shown in the figure is a filter. The type of filter and its
cut-off frequency are respectively
10 K

10 K

1 F
1K

a. high pass, 1000 rad/sec. b. low pass, 1000 rad/sec.


c. high pass, 10000 rad/sec. d. low pass, 10000 rad/sec.

63. In an ideal differential amplifier shown in the figure, a large value of (RE)

-VEE

a. increases both the differential and common mode gains.


b. increase the common-mode gain only.
c. decrease the differential-mode gain only
d. decrease the common-mode gain only

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64. For an n-channel MOSFET and its transfer curve shown in the figure, the
threshold voltage is
ID ↑ VD= 5V

D
Transfer VG=3V
characteristics

G

| | →
1V VGS
S
Vs= 1V

a. 1V and the device is in active region


b. -1V and the device is in saturation region
c. 1 V and the device is in saturation region
d. -1 V and the device is in active region

65. The circuit using a BJT with β = 50 and VBE = 0.7V is shown in the figure.
The base current IB and collector voltage Vc are respectively

20 V
2k
430K

10 F
1K 40 F

a. 43 µA and 11.4 Volts b. 40µA and 16 Volts


c. 45µA and 11 Volts d. 50µA and 10 Volts

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66. The zener diode in the regulator circuit shown in the figure has a Zener voltage
of 5.8 volts and a Zener knee current of 0.5mA. the maximum load current drawn
from this circuit ensuring proper functioning over the input voltage range between
20 and 30 volts, is
1k


=5.8V Load
20-30

a. 23.7 mA b. 14.2 mA
c. 13.7 mA d. 24.2 mA

67. Given the ideal operational amplifier circuit shown in the figure indicate the
correct transfer characteristics assuming ideal diodes with zero cut-in voltage.
+10V

-10V
2K

0.5K

2K

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+10V
(a) ←→

-8V -5V

←→
-10V


+10V
(b) ←→

-5V +8V

←→
-10V


+5V
(c) ←→

-5V +5V

←→
-10V


+10V
(d) ←→

-5V +5V

←→
-5V

Common Data Questions 68, 69, 70


Given rd = 20 kΩ, IDSS = 10 mA, VP = - 8V

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68. Zi and Z0 of the circuit are respectively


a. 2M Ω and 2k Ω b. 2M Ω and 20/11 k Ω
c. infinity and 2 M Ω d. infinity and 20/11 k Ω

69. ID and VDS under DC conditions respectively


a. 5.625mA and 8.75 V b. 7500 mA and 5.00V
c. 4.500 mA and 11.00 V d. 6.250 mA and 7.50V

70. Transconductance in milli-Siemens (ms) and voltage gain of the amplifier are
respectively
a. 1.875 ms and 3.41 b. 1.875 ms and -3.41
c. 3.3 mS and -6 d. 3.3 mS and 6

GATE- 2006 One Mark Questions


71. The input impedance (Zi) and the output impedance (Z0) of an ideal
transconductance (voltage controlled current source) amplifier are
a. Zi = 0, Z0 = 0 b. Zi = 0, Z0 = ∞
c. Zi =∞, Z0 = 0 d. Zi =∞, Z0 = ∞

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72. An n-channel depletion MOSFET has following two points on its ID – VGS
curve.
(i) VGS = 0 at ID = 12 mA and
(ii) VGS = - 6 Volts at Z0 = ∞

Which of the following Q-points will give the highest trans-conductance gain for
small signals?
a. VGS = -6 Volts b. VGS = - 3 Volts
c. VGS = 0 Volts d. VGS = 3 Volts

GATE-2006 Two Marks Questions


73. For the circuit shown in the following figure, the capacitor C is initially
uncharged. At t = 0, the switch S is closed. The voltage VC across the capacitor at t
= 1 millisecond is
C=1 F
S
- +

1K
10V

In the figure shown above, the OP-AMP is supplied with ± 15 V.


a. 0 Volt b. 6.3 Volts
c. 9.45 Volts d. 10 Volts

74. For the circuit shown below, assume that the zener diode is ideal with a break
down voltage of volts. The waveform observed across R is

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6V

12sin t ~ R VR

(a)

6V
(b)
-12V
12V
(c)
-6V

(d)
-6V

Common Data for Questions 75, 76 & 77


In the transistor amplifier circuit shown in the figure below, the transistor has the
following parameters.
βDC = 60, VBE = 0.7, hie →∞, hfe →∞
The capacitance Cc can be assumed to be infinite.
12v

1K
53K
+
5.3K

Vc
Cc
~ -

In the figure above, the ground has been shown by the symbol ▼
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75. Under the DC conditions, the collect to-emitter voltage drop is


a. 4.8 Volts b. 5.3 volts
c. 6.0 volts d. 6.6 volts

76. If βDC is increased by 10% the collector to emitter voltage drop


a. increases by less than or equal to 10%
b. decreases by less than or equal to 10%
c. increases by more than 10%
d. decreases by more than 10%

77. the small-signal gain of the amplifier vc/vs is


a. -10 b. – 5.3
c. 5.3 d. 10
Common Data for Questions 78 & 79.
\a regulated power supply shown in figure below, has an unregulated input (UR)
of 15 volts and generates a regulated output Vout. Use the component values shown
in the figure

15V (UR) Q1
+
12
1K
12

6V 24

In the figure above, the ground has been shown by the symbol of ▼

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78. The power dissipation across the transistor Q1 shown in the figure is
a. 4.8 Watts b. 5.0 Watts
c. 5.4 Watts d. 6.0 Watts

79. If the unregulated voltage increases by 20% the power dissipation across the
transistor Q1
a. increases by 20% b. increases by 50%
c. remains unchanged d. decreases by 20%

GATE-2007 One Mark Questions


80. The correct full wave rectifier circuit is

81. In a transconductance amplifier it is desirable to have


a. a large input resistance and a large output resistance
b. a large input resistance and a small output resistance
c. a small input resistance and a large output resistance
d. a small input resistance and a small output resistance

GATE- 2007 Two Marks Questions


82. The DC current gain (β) of a BJT is 50. Assuming that the emitter injection
efficiency is 0.995, the base transport factor is

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a. 0.980 b. 0.985
c. 0.990 d. 0.995

83. For the Op-Amp circuit shown in the figure, V0 is


2K

1K

1V

1K
1K

a. -2V b. -1V
c. -0.5 V d. 0.5V

84. For the BJT circuit shown, assume that the β of the transistor is very large and
VBE = 0.7 V. The mode of operation of the BJT is

10K

+ 10V
-
2V +
- 1K

a. cut-off b. saturation
c. normal active d. reverse active

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85. In the OP-Amp circuit shown, assume that the diode current follow the
equation I=Is exp (V/VT). for Vi = 2V, V0 = v01, and for Vi = 4 V, V0 = V02. the
relationship between V01 and V02 is

2K

a. V02 = √2 V01 b. V02 = e2 V01


c. V02 = V01 In 2 d. V01 – V02 = VT In 2

86. In the CMOS inverter circuit shown, if the transconductance parameters of the
NMOS and PMOS transistors are kn = kp = µn Cox Wn/Ln = µn Cox Wp/Lp = 40 µ
A/V2 and their threshold voltages are VTHn = |VTHp| = 1V, the current is
5V

PMOS
↓I
2.5 V
NMOS

a. 0A b. 25µA
c. 45 µA d. 90 µA

87. For the Zener diode shown in the figure, the zener voltage at knee is 7V, the
knee current is negligible and the Zener dynamic resistance is 10 Ω. If the input
voltage (Vi) range is from 10 to 16 V, the output voltage (V0) range from

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200

a. 7.00 to 7.29 V b. 7.14 to 7. 29V


c. 7.14 to 7. 43 V d. 7. 29 to 7. 43 V

Common Data Questions 88, 89, 90


The figure shows the high-frequency capacitance voltage (C-V) characteristics of
a Metal/SiO2/silicon (MOS) capacitor having an area of 1 x 10-4 cm2. assume that
the permitivities (ε0 εr) of silicon and SiO2 are 1 x 10-12 F/cm and 3.5 x 10-13 F/cm
respectively.

88. The gate oxide thickness in the MOS capacitor is


a. 50 mm b. 143 mm
c. 350 mm d. 1µm

89. The maximum depletion layer width in silicon is


a. 0.143 µm b. 0.857 µm
c. 1 µm d. 1.143 µm

90. Consider the following statements about the C-V characteristics plot;

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S1: The MOS capacitor has as n-type substrate.


S2: If positive charges are introduced in the oxide, the C-V plot will shift to the
left.
Then which of the following is true?
a. Both S1 and S2 are true b. S1 is true and S2 is false
c. S1 is false and S2 is true d. Both S1 and S2 are false

Statement for Linked Answer Questions 91 & 92.


Consider the Op-Amp circuit shown in the figure.

R
C

91. The transfer function V0 (s)/Vi(s) is

a. b.

c. d.

92. If Vi = V1 sin (ωt) and V0 = V2 sin (ωt + φ), then the minimum and maximum
values of φ (in radians) are respectively
a. – π/2 and π/2 b. 0 and π/2
c. – π and 0 d. – π/2 and 0

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GATE-2008 One Mark Questions


93. In the following limiter circuit, an input voltage V i = 10 sin 100 πt is applied.
Assume that the diode drop is 0.7V when it is forward biased. The zener
breakdown voltage is 6.8 V.

1K
D1
D2

Z 6.8V

The maximum and minimum values of the output voltage respectively are
a. 6.1 V, - 0.7 V b. 0.7 V, -7.5 V
c. 7.5 V, - 0.7 V d. 7.5 V, - 7.5 V

GATE-2008 Two Marks Questions


94. Consider the following circuit using an ideal OPAMP. The I-V characteristics

of the diode is described by the relation


Where VT = 25m V, I0 = 1µA and V is the voltage across the diode (taken as
positive for forward bias).
D 4K

=-1V

100 K

For an input voltage Vi = -1V, the output voltage V0 is


a. 0 V b. 0.1 V
c. 0.7 V d. 1.1 V

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95. The OPAMP circuit shown above represents a


C

a. high pass filter b. low pass filter


c. band pass filter d. band reject filter
96. Two identical NMOS transistors M1 and M2 are connected as shown below.
Vbias is chosen so that both transistors are in saturation. The equivalent gm of the

pair is defined to be at constant Vout.

The equivalent gm of the pair is


a. the sum of individual gm’s of the transistors
b. the product of individual gm’s of the transistors
c. nearly equal to the gm of M1
d. nearly equal to gm/g0 of M2

97. Consider the Schmidt trigger circuit shown below

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I out

Vbias M2

M1

A triangular wave which goes from – 12V to 12V is applied to the inverting input
of the OPAMP. Assume that the output of the OPAMP swings from +15V to -
15V. the voltage at the non-inverting input switches between
a. -12V and +12v b. -7.5 and +7.5 V
c. -5V and + 5V d. OV and 5 V

Statement for linked Answer Questions 98 and 99.


In the following transistor circuit, VBE = 0.7 V, re = 25 mV/IE and β and all

=9V
20K 3K

Cc2

C c1 ↓I
E
10K
2.3K 3K
CE

98. The value of DC current IE is


a. 1mA b. 2 mA
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c. 5 mA d. 10 mA

GATE-2009 Two marks Questions


100. In the circuit below, the diode is ideal. The voltage V is given by
+ V-

1 1
+ ↓ 1A
-

a. min (Vi 1) b. max (Vi 1)


c. min (-Vi 1) d. max (-Vi 1)

101. A small signal source vi (t) = A cos 20t + B sin 106t is applied to a transistor
amplifier as shown below. The transistor has β = 150 and hie = 3KΩ. Which
expression best approximates v0 (t)?
12V

100 K 3K
(t)
(t) 100 nF

900K
20 K 10 F

a. v0 (t) = -1500 (A cos 20t + B sin 106t)


b. v0 (t) = -150 (A cos 20t +B sin 106t)
c. v0 (t) = -1500 B sin 106t
d. v0 (t) = -150 B sin 106t
Common Data for Questions 102 and 103.

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Consider a silicon p-n junction at room temperature having the following


parameters:
Doping on the n-side = 1 x 1017 cm-3
Depletion width on the n-side = 0.1 µm
Depletion width one the p-side = 1.0 µm
Intrinsic carrier concentration = 1.4 x 1010 cm-3
Thermal voltage =26 mV
Permittivity of free space = 8.85 x 10-14 F.cm-1
Dielectric constant of silicon = 12

102. The built-in potential of the junction


a. is 0.70 V
b. is 0.76 V
c. is 0.82 V
d. cannot be estimated from the data given

103. The peak electric filed in the device is


a. 0.15 MV.cm-1, directed from p-region to n-region
b. 0.15MV. cm-1, directed from n-region to p-region
c. 1.80 MV.cm-1 directed from p-region to n-region
d. 1.80 MV. cm-1 directed from n-region to p-region

Statement for Linked Answer Question 104 and 105.


Consider the CMOS circuit shown, where the gate voltage VG of the n-MOSFET
is increased from zero, while the gate voltage of the p-MOSFET is kept constant at
3V. Assume that for both transistors, the magnitude of the threshold voltage is 1 V

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and the product of the transconductance parameter and the (W/L) ratio, i.e. the
quantity µCox(W/L). is 1mA. V-2.
5V


3V

VG →

104. For small increase in VG beyond 1V, which of the following gives the correct
description of the region of operation of each MOSFET?
a. Both the MOSFETs are in saturation region
b. Both the MOSFETs are in triode region
c. n-MOSFET is in triode and p-MOSFET is in saturation region
n-MOSFET is in saturation and p-MOSFET is in triode region

105. Estimate the output voltage V0 for VG = 1.5 V, [Hints: use the appropriate
current-voltage equation for each MOSFET, based on the answer to Q.57]

a. b.

c. d.

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ANSWERS & EXPLANATIONS


1. (a)
2. (a)
3. (a)

IC1 = βIB, IE2 = IC1


io ≈ βIB, Vi = IB, rπ

4. (b)
5. (a)

6. (c)
A = 100,
B= 0.99
1 + AB = 100
For voltage series Ri ↑ & R0 ↓ by 1 + AB
-- Ri = 100 x 1K = 100 K

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7. (b)

Regulation

O/P Resistance =

8. (b)
tr x B.ω = 0.35

B.ω =

9. (a)
Common mode gain,
VC = AC Vi (Vi1 = Vi2 = Vi)
If Re is infinite then because of symmetry of fig., Vc becomes zero.
ie1 = ie2 = 0
ib2 < < ic2
So ic2 ~ ie2

10. (d)
In positive feedback op-amp act in its satuation region ± Vsat. Here applied voltage
is positive.
V0 = + Vsat = + 15 V

11. (c)

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12. (a)

At low frequency, Ai = - hfe and Ai decreases as frequency increases.

13. (c)

Here

14. (d)

15. (a)
This circuit acts as a differentiator and differentiation of triangular wave gives
square wave.

16. (b)

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Control
Gate

17. (d)
15V

Rc

R th

10/3
Vth 5V
430

Since β is large IB ≈ 0, Rth = 5 || 10

18. (c)
V00 = Vi0.A = 5 mV x 10,000 = 50 V
But V00 = ± 15V,
V00 can never be greater than ± Vsat

19. (c)

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hfe = gm .rπ

22. (b)

(β0 = hfe)

23. (C)
I1 20

↓ Iz ↓IC

IB
→ =10V
+
20-30V RB
VBE - ↓ I E

(i.e. when Iz = 0)
IE = IC +Iz
IB = Iz (as no current flows in RB)

From (i) IE = βIz + Iz = (99 +1) Iz


IE = 100 Iz

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I1 = IE = 100 Iz

Iz =
Pz = VzIz = 9.5 x 0.01 = 95mW
Ic = 99Iz = 99 x 0.01 = 0.99A
Pc = VCIC = 10 x 0.99 = 9.9 W

24. (b)
Fig shown is Colpitts oscillator.

25. (b)

Avf = - 9

26. (a)

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10mH 10 F

10
+ 100
1 -
=10cos (100t)
2 3

KCL at node 1,

V0 = -10V2 = -10(-cos 100t)


V0 = 10cos 100t

27. (c)
Ri increases by factor of 1 + Aβ and R0 decreases by 1+ Aβ.

28. (b)
Gain X B. ω = 1x106

20 log x = 20 dB
X = 10

29. (a)
fL = 20 Hz fH = 1 KHz for single stage.

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For cascaded stage

30. (c)
Slew rate = A. 2π fVm
V = A.Vm sin ωt

20 log X = 40
X = 100 = A

Vm = 79. 5 mV

31. (a)

KCL at node 1

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32. (a)
I1
+ → ↑
↓I ↓I
z L

RL

ZL
- ↓

(Iz + IL = I1)
When Vin = 30 V

When Vin = 50 V

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R ≤ 3636

33. (d)

VG = 0, Vs = ID .Rs = 1 mA x 2.5 K = 2.5 V


VGS = VG – Vs = - 2.5 V

AV = -gm RD ( because rd is not given, it is taken as ∞).


= - 2ms x 3K = -6

34. (c)
T1 is N-MOSFET which conduct when Vi > Vth When V0 = 0, CMOS inverter has
I/P = 1 i.e. 5 V So T1 is in saturation and conducts.

35. (b)
36. (d)
37. (b)

8Vp-p
So, Vi = 4 sin ω t
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At Vi = 2

Another crossover at

Therefore Duty cycle =

38. (c)

39. (a)
A= 50, β = 0.2
D =1 + A β = 1 + 50 x 0.2 = 11
Current shunt: R0 increases & R1 decreases by D.

41. (a)
VCE = VCC – IC R2
3 = 6 – 1.5 mA x R2
1.5 mA x R2 = 3
R2 = 2 KΩ

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When β = 200,
IC = βIB (as R1 is same IB remains same)
= 0.01 mA x 200
IC = 2 mA
VCE = VCC – IC R2
= 6-2 mA x 2 kΩ
VCE = 2V

42. (a)

Frequency of oscillation for RC phase shift oscillator is

43. (c)
As volt at non inverting terminal is 3V due to zener diode, voltage at inverting
terminal will be 3V because of virtual ground.

So current in 20K is

44. (d)

45. (b)

V0 = 6V

46. (c)

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250 250 250

1K 1K V
+ +- 4
1K + -
-
50 50 50

Volt. Across 1 K after 1st stage =

Similarly

Therefore AV = 40 x 40 x 50 = 8 x 104
AV in dB = 20 log (8 x 104) = 98 dB
47. (d)

I = 3mA

50. (a)

At ω = ∞, & at ω = 0

51. (a)
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VCE = VCC -ICRC


0.2 = 3-IC x 1 K
IC = 2.8 mA

52. (d)

hfe = gm. rπ, hfe = β

53. (a)
2.1K

1K

C
1K
← ↓

1K C

R= 1K

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For oscillation imaginary part is zero.

i.e.

ω2 C2 R2 – 1 = 0

54. (a)

1K
V


iL

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…..(i)

….. (ii)

Putting V0 from (1)

55. (d)

When IL = 100 mA,

When IL = 500mA,

Therefore R= 14 Ω (choosing minimum one)

56. (b)

57. (d)

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58. (b)

59 (b)

60. (c)
When two terminals of a transistor are shorted it acts as diode.

61. (c)
- 1M +

IB2 ↓
e0

IB1 1M

V1 = - IB1 x 1M, V2 = V1 = - IB1 x 1M (due to virtual ground)


Drop in feedback resistor 1M = IB2 x 1M
e0 = V2 + IB2 x 1M
e0 = - IB1 x 1M + IB2 x 1M
e0 = (IB2 – IB1) x 1M
where (IB2- IB1) is offset current

62. (a)
Since O/P is taken across 10K it is a high pass filter. I/P is at non-inverting point.
So,

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63. (d)
Only common mode gain depends on RE and differential mode gain is independent
of RE.

64. (c)
From the graph its clear that Vth = 1V
VGs = 3-1 = 2V
VDS = 5-1= 4V
Since VDs ≥ VGS – VT S. MOSFET is in saturation region.

65. (b)
IE = IC + IB = βIB +IB = (β+ 1)IB
KVL in I/P loop gives,
VCC – VBE = IBRB + IE RE = IB RB + (β+1) IB RE

IB = 40 µA
IC = β = 50 x 40 µA = 2000 µA = 2 mA
VC = VCC- ICRC = 20-2 mA X 2K
VC = 16 V

66. (a)
I1 1K IL
→ →
↓I
z

20-30V Load
5.8V

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VL= ‘5.8 V

Maximum load current will be when V1 = Vmax


24.2mA = IL + Iz
IL = 24.2 mA – 0.5 mA = 23.7 mA

67. (b)
Vut = βu Vsat

When lower diode is ON,

Vιt = - βι Vsat (when upper diode is ON, βι =

Vut & Vιt are upper and lower transition voltage.

68. (b)
Zin = 2 MΩ
Z0 = rd || RD = 20 K || 2 K

69. (a)

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ID = 10 mA x
VDS = VDD – ID RD = 20- 5.625 mA x 2 K
VDS = 8. 75 V

70. (b)

Gm = 1.875 ms
AV = - gm (rd || RD) (gm Z0)

AV = - 3.41

72. (d)
From the graph it is clear that as VGS increase conductance i.e. slope of graph
increase.
↑ ID

12mA

-6V V
GS
(Z 0 = )

Transfer character of n-channel D-MOSFET

73. (d)

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1 F

- +
1K
1
10V

10V

Applying KCL at node 1

74. (b)
Zener diode works as normal diode in FB. So, when Vin < 0, VR = Vin When 0 <
Vin < 6, Diode is OFF and VR = 0.
When Vin > 6, Diode conducts and VR = Vin

75. (c)
Applying KVL in base-emitter loop,
12-IERC – IB . Rf – 0.7 = 0

12-0.7 = IE . 1K +

VCE = VCC – IE . RC = 12-6 mA x 1 K = 6 V

76. (b)
When β increases by 10%, new β = 66

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VCE = VCC – IE . RC = 12- 6.31 mA x 1K = 5.7

% change in

77. (a)

78. (d)
15V Q1
+
12K
1K (3v) 12K

6v -

(6V) 24K
6V

Volt across 24K = 6V due to virtual ground concept. So volt across 12K is 3V.
Vout = V12K + V24K = 3+6
Vout = 9 V
VCE = 15- Vout = 15-9 = 6V

Therefore P= VCE . IC = 6 V x 1A
P= 6 Watts

79. (b)

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New unregulated voltage = 18V


Therefore VCE = 18-9 = 9 V
IC = 1A
Therefore P = 9 x 1 = 9 watts

80. (c)

81. (a)

82. (b)
IPC1
IPE

P n P

InE

+ - +
-

VEB VCB

Transport factor

Current in emitter is both due to holes and electrons Neglect current due to
electrons

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83. (c)
2K

1V 1k
X
1k y
1V

1K

X = 1 volt y = 0.5 (using voltage division rule)

84. (b)
Given β is large so IB = 0 & IE = IC
Assuming BJT is in active
Applying KVL in Base. Emitter loop
2 – 0.7 = 1 K Ω x IE
IE = 1.3 mA

Now ICsat =

As ICactive > ICsat


So BJT is in saturation

85. (d)
Applying KCL
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IR = I D

V 0 = - VT

Now, V01 = - VT

V01 – V02 = VT / n 2

86. (d)
VGS for each MOS is 2.5V
VT = 1 volt device parameter K = 40 µ A/v2
So ID = K (VGS – VT)2

= 40
ID = 90 µA

87. (c)
VZ = 7 volt IK = 0, R z = 10 Ω
Range of Vi = 10 to 16V
Range of voltage across 200 Ω = Vi- Vz = 3 to 9 volt
Range of current through 200 Ω = 15 to 45 mA
Range of variation in output voltage

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= (15 to 45mA) x Rz = 0.15 to 0.45 Volt


So range of output voltage = 7 + (0.15 to 0.45 volt)
= 7.15 volt to 7. 45 volt

88. (a)

89. (c)

90. (d)

91. (a)
From the figure given in the question

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92. (c)

θ = - tan -1 ωRC – tan-1 ωRC


θ = - 2tan -1 ωRC
minimum value of θ = - π (at ω → ∞)
maximum value of θ = 0 (at ω = 0)

93. (c)
For the positive half of Vi
D1 is forward biased and Zener diode is in breakdown stage
V0 = 0.7 + 6.8 = 7.5 V
For the negative half of Vi D2 is forward biased.
V0 = - 0.7 V

94. (b)

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95. (b)

Which is equivalent to standard form of transfer function of low pass filter, i.e.

97. (c)
Le the voltage at the non-inverting input be V1
Applying KCL at non-inverting input end

15-V1 + V0 – V1 = V1 + 15

Since, V0 swings from – 15V to + 15 V,


Therefore V1 switches between – 5V & + 5V.

98. (a)
The given circuit can be redesigned as shown below

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= 9V

3K

RTh

VTh I
E

2.3K

= 6.67 k
Since β is large IB can be ignored

99. (d)
Mid-band voltage gain,

= - 60

100. (a)

101. (b)
The best approx answer for output voltage v0 is
V0 = Ar. vi

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≈ - 150 (A cos 20t + B sin 106 )


Note: Magnitude of gain is taken by total approx.

102. (b)
N side is heavily doped

103. (*)

(directed from N to P side)

104. (d)

105. (*?)

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