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ANNEXE du TP 2:

PROGRAMMATION VHDL.
ADDITIONNEUR-SOUSTRACTEUR
32-bits
OPTIMISATION ESPACE-TEMPS

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 1
I.
INTRODUCTION &
RAPPELS THEORIQUES

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 2
Additionneur Complet 1-bits

Ai Bi

Additionneur
C i+1 Complet Ci
(1-bit)

Si
Block Diagramme

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 3
Soustraction Binaire
A 0111 → 0111
Rappel B - 0110 → + 1010
1 0001
‰ Complément à 2 est:
Complémenter (inverser)
tous les bits
+
Ajouter ‘1’ au bit le moins
significatif

Add_Soust (0 Æ Add, 1 Æ Soust)


A 0111 → 0111 B0
B - 0110 → + 1001 B0 if Add_Soust = 0,
NOT B0 if Add_Soust = 1
+ 1

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 4
Add/Soust
L’ajout ‘1’ au bit le moins significatif c0=carry_in
est DIRECT puisque c’est le bit de A0 1-bit
AC S0
control ‘Add/Soust’ lui même peut
B0 c1
jouer ce rôle.
A1 1-bit
AC S1
B1
c2
A2 1-bit
Additionneur/Soustracteur S2
AC
32-bits
B2 c3

...
Le Programme: c31
A31 1-bit
AC S31
B31
c32=carry_out

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 5
---------- Additionneur Complet 1-bit -------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Add_Complet IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END Add_Complet;

ARCHITECTURE Flow_Donnees OF Add_Complet IS


BEGIN
sum <= a XOR b XOR c_in;
c_out <= (a AND b) OR (c_in AND (a OR b));
END Flow_Donnees;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 6
---------------- Additionneur/Soustracteur Complet 32-bits (Type : Carry Chain) -----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Add_Soust_32CP is
Port (
CLK : in std_logic;
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Add_Soust : in std_logic;
C_R : out std_logic_vector(31 downto 0);
Cout_R : out std_logic);
end Add_Soust_32CP;

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DSA-UQAC 7
architecture STRUCTURE of Add_Soust_32CP is

COMPONENT Add_Complet
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
c_in : IN STD_LOGIC;
sum : OUT STD_LOGIC;
c_out : OUT STD_LOGIC);
END COMPONENT Add_Complet;

SIGNAL Co_I :
STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL A_R, B_R, C : STD_LOGIC_VECTOR(31
DOWNTO 0);
SIGNAL Cin_R, Cout : STD_LOGIC;
SIGNAL Bt : STD_LOGIC;
BEGIN

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DSA-UQAC 8
Bt <= B when Add_Soust = ‘0’ else not B; Process (Add_Soust) Begin

IN_REGS: process (CLK) if Add_Soust = ‘0’ then Bt <= B;

begin
else Bt <= not B;
if (CLK'event and CLK='1') then
End process
A_R <= A;B_R <= Bt;Cin_R <= Cin;
end if; Synthèse Æ Mux2_1 ou XOR
end process IN_REGS;
Logique_Comb_CADDER: block
Begin

c0 : Add_Complet
PORT MAP (a => A_R(0), b => B_R(0), c_in => Add_Soust, sum => C(0),
c_out => Co_I(0));

Loop_c1to30 : FOR i IN 1 TO 30 GENERATE


c1to30: Add_Complet PORT MAP (A_R(i),B_R(i),Co_I(i-1),C(i), Co_I(i));
END GENERATE;
c31 : Add_Complet PORT MAP (A_R(31),B_R(31),Co_I(30),C(31), Cout);
end block Logique_Comb_CADDER;

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DSA-UQAC 9
OUT_REGS: process (CLK)
begin
if (CLK'event and CLK='1') then
C_R <= C;Cout_R <= Cout;
end if;
end process OUT_REGS;
end STRUCTURE;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 10
Additionneur Soustracteur N-bits

Pour obtenir un Additionneur Soustracteur (à N-bit), il suffit


d’enchaîner ‘N’ Additionneur Complet (à 1-bit) en série + N XORs.
Par exemple, pour N=4:

Add_Soust = C0

B3 B2 B1 B0
A3 A2 A1 A0

Additionneur Additionneur Additionneur Additionneur


Complet Complet Complet Complet
(1-bit) C3 (1-bit) C2 (1-bit) C1 (1-bit)

C4 S3 S2 S1 S0

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DSA-UQAC 11
Nous avons vu comment réaliser un Additionneur Rapide avec
l’architecture ‘LookAhead’. Cette technique donne lieu à énormément
de Hardware, mais le résultat de l’addition est très rapide.
A titre d’illustration:
‰Lessorties (les retenues) se stabilisent rapidement
comme suit:
zRetard_C3 = 2* Retard_AND + Retard _OR (meilleur des cas)
z…

zRetard_C31 = 5 * Retard_AND + Retard _OR (meilleur des cas)


‰ Le Problème: son prix est exorbitant à cause de la
consommation Hardware exorbitant.

Question: Y’a t-il moyen de combiner les 2 architectures (Propagation de


Retenue et LookAhead) pour avoir les avantages de l’un et de l’autre
à la fois. En d’autres termes, réaliser un meilleur compromis:
Temps-Nombre de Portes.
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 12
Solution Hiérarchique I

„ Grouper l’additionneur 32-bits en 8 groupes


d’additioneurs 4-bit

„ Pour chaque groupe, l’architecture


LookAhead est appliquée.

„ Utiliser l’additionneur LookAhead 4-bit


comme bloc élémentaire. Ensuite ces blocs
sont connectés avec une architecture
‘Propagation de Retenue’.

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 13
Ainsi:
c0 =Retenue d’entrée
c1 =g0+ p0.c0

c2 = g1+ p1.c1 = g1+ p1.(g0+ p0.c0) = g1+ p1.g0 + p1.p0.c0

c3 =g2+ p2.c2 = g2+ p2.(g1+ p1.c1) = …


= g2+ p2.g1 + p2.p1.g0 + p2.p1.p0.c0

c4 = g3+ p3.c3 = g3+ p3.(g2+ p2.c2) = g3+ p3.g2 + p3.p2.c2


= g3+ p3.g2 + p3.p2.[g1+ p1.g0 + p1.p0.c0 ]

c4 = g3+ p3.g2 + p3.p2.p1.g0 + p3.p2.p1.p0.c0


(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 14
c0=carry_in
A0 c27=carry_in
B0 A0
A1 B0
B1 ADD A1
4-bits result 0-3 B1 ADD
A2 result 24-27
(LA) A2 4-bits
B2
A3 B2 (LA)
B3 A3
B3
c4=carry_in
A4 … A4
c31=carry_in
B4
A5 B4
B5 ADD A5
4-bits B5 ADD
A6 result 4-7
(LA) A6 4-bits result 28-31
B6
A7 B6 (LA)
B7 A7
B7

c8=carry_in
c32=carry_out

Retard = 8 * Retard ( Add_LA_4-bit) Au lieu de 32 * Retard ( Add_CP_1-bit)

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 15
Solution Hiérarchique II

„ Grouper l’additionneur 32-bits en 8 groupes


d’additioneurs 4-bit

„ Pour chaque groupe, l’architecture


LookAhead est appliquée.

„ Un autre niveau d’architecture LookAhead


s’impose pour connecter ces groupes de 4-
bits.

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 16
Revoir Autrement
c0 =Retenue d’entrée
c1 =g0+ p0.c0

c2 = g1+ p1.c1 = g1+ p1.(g0+ p0.c0) = g1+ p1.g0 + p1.p0.c0

c3 =g2+ p2.c2 = g2+ p2.(g1+ p1.c1) = …


= g2+ p2.g1 + p2.p1.g0 + p2.p1.p0.c0
c4 = g3+ p3.c3 = g3+ p3.(g2+ p2.c2) = g3+ p3.g2 + p3.p2.c2
= g3+ p3.g2 + p3.p2.[g1+ p1.g0 + p1.p0.c0 ]

c4 = g3+ p3.g2 + p3.p2.p1.g0 + p3.p2.p1.p0.c0 = G0.+P0.c0 = C1


C2 = G1.+P1.C1
G0 (i=0Æ3) P0 (i=0Æ3)
P1 (i=4Æ7) C3 = G2.+P2.C2
G1 (i=4Æ7)
C4 = G3.+P3.C3
… etc.
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 17
c0
A0
B0
cin Unité
Look
result 0-3 = 1er Étage
Ahead pi + c i
pi(i=0Æ3) (i=0Æ3) •Entrees A0-A15, B0-B15
P0
A3 gi (i=0Æ3)
B3 G0
C1 •calculer P0-P3, G0-G3 pour chaque
c4 =G0+
= c4 P0.c0 result 4-7 groupe
A4
B4

pi(i=4Æ7) P1 •deduire C1-C4


A7 gi (i=4Æ7) G1
B7
C2 C2 =G1+ •Pour chaque ADD 4-bit calculer ses
P1.C1 results (Æ result 0-15)
A8 result 8-11
B8
De chaque groupe LookAhead ADD 4-bits

pi(i=8Æ11)
result(i) = pi + ci ET
P2
A11
B11 gi (i=8Æ11) G2
C3 C3 =G2+
gi =Ai.Bi pi= Ai+Bi
A12 P2.C2
B12 P0 = p3.p2.p1.p0
pi(i=12Æ15) P3 result 12-15 G0 = g3+ p3.g2 + p3.p2.p1.g0
gi (i=12Æ15) G3 = pi + ci P1 = p7.p6.p5.p4
A15 C4 =G3+ (i=12Æ15)
G1 = g7+ p7.g6 + p7.p6.p5.g4 … etc.
B15 P3.C3
Ci+1 = Gi.+Pi.Ci
C4
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 18
C4
A16
B16
cin Unité
Look
result 16-19 2eme Étage
Ahead =pi + ci
pi(i=16Æ19) (i=16Æ19)
P4
A19 gi (i=16Æ19)
B19 G4
C5 •Entrees A16-A31, B16-B31
C5 =G4+
A20 P4.C4 result 20-23
B20
•calculer P4-P7, G4-G7 pour chaque
pi(i=20Æ23) P5 groupe
A23 gi (i=20Æ23) G5
B23
C6 C6 =G5+ •Deduire C5-C7 et COUT
P5.C5
A24 result 24-27
B24 •Pour chaque ADD 4-bit calculer ses
results (Æ result 16-31)
pi(i=24Æ27) P7
A27
gi (i=24Æ27) G7
B27
C7
MAIS Les 2 Étages sont
C7 =G6+
A28 P6.C6 Connectés à la
B28 Propagation de Retenue
pi(i=28Æ31) P8 result 28-31
G8 = pi + ci
Avec le C4 qui joue le rôle
gi (i=28Æ31)
A31 C8 =G7+ (i=28Æ31) De c0 du 1er étage.
B31 P7.C7

C8 = COUT
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 19
Retenue Rapide en utilisant le 2eme niveau d’abstraction
P0 = p3.p2.p1.p0
P1 = p7.p6.p5.p4
P2 = p11.p10.p9.p8
P3 = p15.p14.p13.p12
G0 = g3+(p3.g2) + (p3.p2.g1) + (p3.p2.p1.g0)
G1 = g7+(p7.g6) + (p7.p6.g5) + (p7.p6.p5.g4)
G2 = g11+(p11.g10)+(p11.p10.g9) + (p11.p10.p9.g8)
G3 = g15+(p15.g14)+(p15.p14.g3)+(p15.p14.p13.g12)

C1 = G0+(P0•c0)
C2 = G1+(P1•C1)= G1+(P1•G0)+(P1•P0•c0)
C3 = G2+(P2•C2)= G2+(P2•G1)+(P2•P1•G0)+(P2•P1•P0•c0)
C4 = G3+(P3•C3)= G3+(P3•G2)+(P3•P2•G1)+(P3•P2•P1•G0)
+ (P3•P2•P1•P0•c0)

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DSA-UQAC 20
P4 = p19.p18.p17.p16
P5 = p23.p22.p21.p20
P6 = p27.p26.p25.p24
P7 = p31.p30.p29.p28
G4 = g19+(p19.g18) + (p19.p18.g17) + (p19.p18.p17.g16)
G5 = g23+(p23.g22) + (p23.p22.g21) + (p23.p22.p21.g20)
G6 = g27+(p27.g26)+(p27.p26.g25) + (p27.p26.p25.g24)
G7 = g31+(p31.g30)+(p31.p30.g29)+(p31.p30.p29.g28)
C5 = G4+(P4.G3)+(P4.P3•G2)+(P4.P3•P2•G1)+
A (P4.P3•P2•P1•G0) + (P4.P3•P2•P1•P0•c0)
T
T C6 = G5+(P5.G4)+(P5.P4.G3)+(P5.P4.P3•G2)+(P5.P4.P3•P2•G1)+
(P5.P4.P3•P2•P1•G0) + (P5.P4.P3•P2•P1•P0•c0)
E
N C7 = G6+(P6.G5)+(P6.P5.G4)+(P6.P5.P4.G3)+(P6.P5.P4.P3•G2)+
T (P6.P5.P4.P3•P2•G1)+(P6.P5.P4.P3•P2•P1•G0) + (
I P6.P5.P4.P3•P2•P1•P0•c0)
COUT = G7+(P7.G6)+(P7.P6.G5)+(P7.P6.P5.G4)+(P7.P6.P5.P4.G3)+
O (P7.P6.P5.P4.P3•G2)+(P7.P6.P5.P4.P3•P2•G1)+
N (P7.P6.P5.P4.P3•P2•P1•G0) +(P7.P6.P5.P4.P3•P2•P1•P0•c0)
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 21
P4 = p19.p18.p17.p16
Économie de
P5 = p23.p22.p21.p20 Portes par
P6 = p27.p26.p25.p24 Rapport à
L’architecture
P7 = p31.p30.p29.p28 LookAhead
G4 = g19+(p19.g18) + (p19.p18.g17) + Seule
(page précédente)
(p19.p18.p17.g16)
G5 = g23+(p23.g22) + (p23.p22.g21) +
(p23.p22.p21.g20)
G6 = g27+(p27.g26)+(p27.p26.g25) + (p27.p26.p25.g24)
G7 = g31+(p31.g30)+(p31.p30.g29)+(p31.p30.p29.g28)

M C5 = G4+(P4•C4)
A C6 = G5+(P5•G4)+(P5•P4• C4)
C7 = G6+(P6•G5)+(P6•P5•G4)+(P6•P5•P4•C4)
I
COUT = G7+(P7•G6)+(P7•P6•G5)+(P7•P6•P5•G4) +
S (P7•P6•P5•P4•C4)

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 22
Conclusion

La solution Hiérarchique II est plus rapide que


la solution Hiérarchique I mais elle synthétise
plus de portes logiques car la propagation de
la retenue est moins longue.

Le Programme:

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 23
----------- Additionneur 4-bits (Type: LOOK AHEAD) --------------------------
-- LES PORTS NE SONT PAS ENREGISTREES POUR L’INSTANT

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Add4b_LA IS
PORT
(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_out : OUT STD_LOGIC
);
END Add4b_LA ;

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DSA-UQAC 24
ARCHITECTURE COMPORTEMENT OF Add4b_LA IS
SIGNAL h_sum : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL carry_generate : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL carry_propagate : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL carry_in_internal : STD_LOGIC_VECTOR(3 DOWNTO 1);

BEGIN
Logique_Comb_LA_ADDER: block BEGIN
h_sum <= x_in XOR y_in;
carry_generate <= x_in AND y_in;
carry_propagate <= x_in OR y_in;
PROCESS (carry_generate,carry_propagate,carry_in_internal) BEGIN
carry_in_internal(1) <= carry_generate(0) OR (carry_propagate(0) AND carry_in);
inst: FOR i IN 1 TO 2 LOOP
carry_in_internal(i+1) <= carry_generate(i) OR (carry_propagate(i) AND carry_in_internal(i));
END LOOP;
carry_out <= carry_generate(3) OR (carry_propagate(3) AND carry_in_internal(3));
END PROCESS;
sum(0) <= h_sum(0) XOR carry_in;
sum(3 DOWNTO 1) <= h_sum(3 DOWNTO 1) XOR carry_in_internal(3 DOWNTO 1);
end block Logique_Comb_LA_ADDER;

END COMPORTEMENT;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 25
Solution Hiérarchique I

------- Additionneur/Soustracteur Complet 32-bits (Type : Mixte CP&LA Solution I) -----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Add_Soust_32CPLA_I is
Port (
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Add_Soust : in std_logic;
C_R : out std_logic_vector(31 downto 0);
Cout_R : out std_logic);
end Add_Soust_32CPLA_I ;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 26
architecture STRUCTURE_I of Add_Soust_32CPLA_I is

COMPONENT Add4b_LA
PORT(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_out : OUT STD_LOGIC
END COMPONENT Add4b_LA ;

SIGNAL Co_I : STD_LOGIC_VECTOR(30 DOWNTO 0);


SIGNAL A_R, B_R, C : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL Cin_R, Cout : STD_LOGIC;
SIGNAL Bt : STD_LOGIC;
SIGNAL C4, C8, C12, C16, C20, C24, C28, C32 : STD_LOGIC;
-- OU BIEN SIGNAL CIN_OUT : STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 27
Synthèse Æ Mux2_1 ou XOR
Bt <= B when Add_Soust = ‘0’ else not B;
IN_REGS: process (CLK) begin if (CLK'event and CLK='1') then -- Enregistrer les Entrées avec des FFs
A_R <= A;B_R <= Bt;Cin_R <= Cin end if;
end process IN_REGS;
Logique_Comb_CPLA_ADDER_I: block
Begin
-- On pouvait le faire comme avant avec: Loop_c1to6 : FOR i IN 1 TO 6 GENERATE pour C1 a C6
c0 : Add4b_LA PORT MAP (x_in => A_R(3 downto 0), y_in => B_R(3 downto 0),
carry_in => Add_Soust, sum => C(3 downto 0), carry_out => c4));
c1 : Add4b_LA PORT MAP (x_in => A_R(7 downto 4), y_in => B_R(7 downto 4),
carry_in => c4, sum => C(7 downto 4), carry_out => c8));
c2 : Add4b_LA PORT MAP (x_in => A_R(11 downto 8), y_in => B_R(11 downto 8),
carry_in => c8, sum => C(11 downto 8), carry_out => c12));
c3 : Add4b_LA PORT MAP (x_in => A_R(15 downto 12), y_in => B_R(15 downto 12),
carry_in => c12, sum => C(15 downto 12), carry_out => c16));
c4 : Add4b_LA PORT MAP (x_in => A_R(19 downto 16), y_in => B_R(19 downto 16),
carry_in => c16, sum => C(19 downto 16), carry_out => c20));
c5 : Add4b_LA PORT MAP (x_in => A_R(23 downto 20), y_in => B_R(23 downto 20),
carry_in => c20, sum => C(23 downto 20), carry_out => c24));
c6 : Add4b_LA PORT MAP (x_in => A_R(27 downto 24), y_in => B_R(27 downto 24),
carry_in => c24, sum => C(27 downto 24), carry_out => c28));
c7 : Add4b_LA PORT MAP (x_in => A_R(31 downto 28), y_in => B_R(31 downto 28),
carry_in => c28, sum => C(31 downto 28), carry_out => c32));
end block Logique_Comb_CPLA_ADDER_I;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 28
Enfin enregistrer les Sorties avec des FFs

OUT_REGS: process (CLK)


begin
if (CLK'event and CLK='1') then
C_R <= C;Cout_R <= Cout;
end if;
end process OUT_REGS;
end STRUCTURE_I;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 29
Solution Hiérarchique II

------- Unite LookAhead Generateur de Retenue (Type : Mixte CP&LA Solution II) -----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ULA_GenR_4 is
Port (
P0, P1, P2, P3 : in std_logic;
G0, G1, G2, G3 : in std_logic;
c0 : in std_logic;
C1, C2, C3, C4 : out std);
end ULA_GenR_4 ;

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DSA-UQAC 30
architecture DF of ULA_GenR_4 is

BEGIN
Logique_Comb_ULA_GenR_4: block
Begin

C1 <= G0 OR(P0 AND c0)

C2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND c0 )

C3 <= G2 OR(P2 AND G1) OR(P2 AND P1 AND G0) OR(P2


AND P1 AND P0 AND c0)

C4 <= G3 OR(P3 AND G2) OR(P3 AND P2 AND G1) OR(P3


AND P2 AND P1 AND G0) OR (P3 AND P2 AND P1 AND
P0 AND c0)
end block Logique_Comb_ULA_GenR_4;
end architecture DF;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 31
------- Fonctions G et P (Type : Mixte CP&LA Solution II) -----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity LA_GP_4 is
Port (
A, B : in std_logic_vector(3 downto 0);
Pi : out std_logic;
Gi : out std_logic);
end LA_GP_4;
architecture DF of LA_GP_4 is
Signal P, G : std_logic_vector(3 downto 0);
begin
P <= A XOR B;
G <= A XOR B;

Pi <= P(3) AND P(2) AND P(1) AND P(0);


Gi <= G(3) OR (P(3) AND G(2)) OR ( P(3) AND P(2) AND G(1) ) OR (P(3) AND P(2) AND
P(1) AND G(0))

End architecture DF

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 32
-------Unite LookAhead 16-bits (Type : Mixte CP&LA Solution II) -----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ULA_16 is
Port (
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
C_in : in std_logic; -- Add_Soust
C_out: out std_logic_vector(3 downto 0));
end ULA_16;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 33
architecture STRUCTURE of ULA_16 is

COMPONENT ULA_GenR_4
PORT(
P0, P1, P2, P3 : in std_logic;
G0, G1, G2, G3 : in std_logic;
c0 : in std_logic;
C1, C2, C3, C4 : out std);
END COMPONENT ULA_GenR_4;

COMPONENT LA_GP_4
PORT(
A, B : in std_logic_vector(3 downto 0);
Pi : out std_logic;
Gi : out std_logic);
END COMPONENT LA_GP_4 ;

BEGIN
SIGNAL P0, P1, P2, P3, G0, G1, G2, G3 : std_logic;
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 34
Logique_Comb_ULA_16 : block
Begin

GP_0 : LA_GP_4 PORT MAP (A => A(3 downto 0), B => B(3 downto 0),
Pi => P0, Gi =>G0);

GP_1 : LA_GP_4 PORT MAP (A => A(7 downto 4), B => B(7 downto 4),
Pi => P1, Gi =>G1);

GP_3 : LA_GP_4 PORT MAP (A => A(11 downto 8), B => B(11 downto 8),
Pi => P2, Gi =>G2);

GP_4 : LA_GP_4 PORT MAP (A => A(15 downto 12), B => B(15 downto 12),
Pi => P3, Gi =>G3);

ULA_1 : ULA_GenR_4 PORT MAP (P0 => P0, P1 => P1, P2 => P2, P3 => P3, G0 => G0, G1 =>
G1, G2 => G2, G3 => G3, c0 => C_in , C1 =>C1, C2 =>C2, C3 =>C3, C4 =>C4 );

end block Logique_Comb_ ULA_16;


C_out <= C4 & C3 & C2 & C1; -- Retenue Finale
End architecture STRUCTURE

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 35
ENFIN … Solution Hiérarchique II

------- Additionneur/Soustracteur Complet 32-bits (Type : Mixte CP&LA Solution I) -----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Add_Soust_32CPLA_II is
Port (
A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
Add_Soust : in std_logic;
C_R : out std_logic_vector(31 downto 0);
Cout_R : out std_logic);
end Add_Soust_32CPLA_II ;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 36
architecture STRUCTURE_II of Add_Soust_32CPLA_I is
SIGNAL C1_4, C5_8 : std_logic_vector(3 downto 0);

COMPONENT ULA_16
PORT(
A : in std_logic_vector(15 downto 0);
B : in std_logic_vector(15 downto 0);
C_in : in std_logic; -- Add_Soust
C_out: out std_logic);
END COMPONENT ULA_16;

COMPONENT Add4b_LA
PORT(
x_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_in : IN STD_LOGIC;
sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
carry_out : OUT STD_LOGIC
END COMPONENT Add4b_LA ;
BEGIN
(c) Hiver 2003, Rachid Beguenane
DSA-UQAC 37
Bt <= B when Add_Soust = ‘0’ else not B;
IN_REGS: process (CLK) begin if (CLK'event and CLK='1') then -- Enregistrer les Entrées avec des FFs
A_R <= A;B_R <= Bt;Cin_R <= Cin end if;
end process IN_REGS;
Logique_Comb_CPLA_ADDER_II: block
Begin
CMP1_ ULA_16 : ULA_16 PORT MAP (A => A_R(15 downto 0), B => B_R(15 downto 0),
C_in => Add_Soust, C_out => C1_4));
c0 : Add4b_LA PORT MAP (x_in => A_R(3 downto 0), y_in => B_R(3 downto 0),
carry_in => Add_Soust, sum => C(3 downto 0), carry_out => ‘0’);
-- pas besoin de carry_out dans ce cas puisqu’elles sont generees par la composante ULA_16
c1 : Add4b_LA PORT MAP (x_in => A_R(7 downto 4), y_in => B_R(7 downto 4),
carry_in => C1_4(0), sum => C(7 downto 4), carry_out => ‘0’);
c2 : Add4b_LA PORT MAP (x_in => A_R(11 downto 8), y_in => B_R(11 downto 8),
carry_in => C1_4(1), sum => C(11 downto 8), carry_out => ‘0’);
c3 : Add4b_LA PORT MAP (x_in => A_R(15 downto 12), y_in => B_R(15 downto 12),
carry_in => C1_4(2), sum => C(15 downto 12), carry_out => ‘0’);
CMP2_ ULA_16 : ULA_16 PORT MAP (A => A_R(31 downto 16), B => B_R(31 downto 16),
C_in => C1_4(3), C_out => C5_8));

c4 : Add4b_LA PORT MAP (x_in => A_R(19 downto 16), y_in => B_R(19 downto 16),
carry_in => C1_4(3), sum => C(19 downto 16), carry_out => ‘0’);
c5 : Add4b_LA PORT MAP (x_in => A_R(23 downto 20), y_in => B_R(23 downto 20),
carry_in => C5_8(0), sum => C(23 downto 20), carry_out => ‘0’);
c6 : Add4b_LA PORT MAP (x_in => A_R(27 downto 24), y_in => B_R(27 downto 24),
carry_in => C5_8(1), sum => C(27 downto 24), carry_out => ‘0’);
c7 : Add4b_LA PORT MAP (x_in => A_R(31 downto 28), y_in => B_R(31 downto 28),
carry_in => C5_8(2), sum => C(31 downto 28), carry_out => ‘0’);
(c) Hiver 2003, Rachid Beguenane
end block Logique_Comb_CPLA_ADDER_II;
DSA-UQAC 38
Enfin enregistrer les Sorties avec des FFs

OUT_REGS: process (CLK)


begin
if (CLK'event and CLK='1') then
C_R <= C;Cout_R <= C5_8(3);
end if;
end process OUT_REGS;
end STRUCTURE_II;

(c) Hiver 2003, Rachid Beguenane


DSA-UQAC 39