Digital System Clocking:

High-Performance and Low-Power Aspects

Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic

Chapter 2: Clocked Storage Elements Operation

Wiley-Interscience and IEEE Press, January 2003

 Evolution of a Latch :
R S R S

(a) keeper; information is latched

(b) S-R latch; information can be modified
(c) S-o-P latch; S-R latch that can implement a
function – IMPORTANT !
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 Adding Clock Control to a Latch

Latching can be done only when clock is active, otherwise

no change is allowed:

(a) Clocked D-latch; (b) timing diagram of clocked D-latch

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 Importance of Latch S-o-P Configuration

(a) Basic Earl’s Latch; (b) Implementing the Carry function

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 Master-Slave Latch

Vdd Vdd

Clk Clk
Q
D

Clk Clk

(a) non-overlapping clocks; (b) single external clock; (c) timing diagram;
(d) PowerPC 603 MS Latch (Gerosa, JSSC 12/94), Copyright © 1994 IEEE
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 IBM LSSD Compatible Clocked Storage Element

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 True-single-phase-clock (TSPC) M-S latch
Yuan and Svenson (1989), Copyright © 1989 IEEE

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 TSPC M-S Latch Operation

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 Pulse latch
(Kozu at al. 1996) Copyright © 1996 IEEE

(a) local clock generator; (b) single latch; (c) clock signals
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 Pulse latch: Intel’s explicit pulsed latch
(Tschanz at al. 2001), Copyright © 2001 IEEE

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 Flip-flop

(a) Early version of a flip-flop; (b) PDP-8 direct set-reset

sequential element
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 Difference between Flip-flop and M-S Latch
Data Data Data Data

Master
Clock Pulse Clock: Φ1
(L1)
Generator
Latch
Q1 Q1
S R
Clock: Φ2 Slave
(L2)
Q2 Latch Q2
Slave
No Clock Latch Pulse
Capturing
Q Q Latch
Q Q
Flip-Flop M-S Latch
(a) (b)

(a) General flip-flop structure; (b) general M-S latch structure

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 Black-box view of the Flip-flop and M-S latch
Data
Q
Data F-F FF

F-F Q
Clock
Clock
Data
Clock Q
Latch L
Data
Clock
Q

Master - L1 Slave - L2
D Q D Q Clock
Data
Latch Q Q Q

Clock Clk1 Clk2 Data

Clock
QL
Data

Q QFF
Flip-Flop
failed !

Experiment causing the flip-flop to

fail while the M-S latch is still
operational

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 Texas Instruments SN7474 Flip-flop

Very much used and analyzed

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 Pulse generator block of SN7474:
malfunctioning due to a gate-delay

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 Systematic Derivation of a FF using Karnaugh map

S n +1 = Clk + R + S n D
S n +1 = Clk R( S + D)

Derivation of the pulse-generating stage of

a flip-flop (only the Sn signal is shown)
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 (a) (b) (c)

(a) Pulse generator stage of the sense-amplifier flip-flop. (Madden and Bowhill, 1990);
(b) Improvement for floating nodes. (Dobberpuhl, 1997);
(c) Pulse generator stage improvement by proper design. (Nikolic and Oklobdzija, 1999).

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 Creating the time reference points for opening
and shutting the flip-flop

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 Hybrid-Latch Flip-Flop (HLFF) introduced by Partovi at al.

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 Logic representation of Partovi’s flip-flop (HLFF)

Clk

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 Systematically derived single-ended flip-flop
(according to the slide no. 18)

(a)

(b)
(a) circuit diagram; (b) logic representation.
(Nedovic and Oklobdzija, 2000). Copyright © 2000 IEEE
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