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ESE 570 MOS INVERTERS STATIC


CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Vin Vout

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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VDD

VDD
0
VOL
VT0n
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Slope of VTC
or
inverter gain

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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(oC)
(oC)
Tj = Ta + ΘP
Θ -> Thermal Resistance (oC/W)
(W)

PDC = Pstatic = VDD IDC

Minimum area nMOS, pMOS transistor layouts limited by design rules


Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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Minimum Area MOS Transistor Layouts

Minimum pMOS Layout


24 

6 3 4 
3
4 14 
2
5 2 5
2 2
Area=24∗14  =336 

Minimum nMOS Layout


16 
6 3
4 8
2 4 E2 = 2λ
2
2 2
Area=16∗8  =128 
1

Relevant Design Rules


Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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VSB

kn' = KPn

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Vin = VOL < VT0,n => nMOS Cut-off

Vout = VOH = VDD

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Vin = VDD
implies

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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-1

VIL

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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VDD

0 VT0n VDD
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
Take Limit as knRL -> ∞
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-> VT0n

-> VT0n

-> VT0n

-> 0

Vout
VDD
knRL -> ∞
semi-ideal VTC
Vin
0 VT0n VDD
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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Vout = VOL

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Multiplying by RL
W 30 x 2V
10
−6
W
DD −V OL  25−0.2
R =
5−0.2= R =
[25−10.2−0.2
2
−6 ]

L L k 'n 2V 2 2
2 DD−VLT0nV OL −V OL  30 x 10 25−10.2−0.2 
L

W
R L=2.05 x 105  NO UNIQUE W/L, RL
L
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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W 5
R L =2.05 x 10 
L

V DD V DD −V OL
P DC average =
2 RL

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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VOL = 0.147 V or 8.503 V ?

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Preferred Design
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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VSB,L ≠ 0

VSB,d
VSB,L

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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VSB,L ≠ 0

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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A
B

S
D

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V T , L =V T0 , L= ∣2 F∣V out − ∣2 F∣ 

D
C
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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DESIGN OF DEPLETION LOAD INVERTERS
VOH:
=0

=> Vout = VOH = VDD


VOL:
VDD ± VDD

VDD ± VDD

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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5V

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=> VGSp = Vin - VDD

=> VDSp = Vout - VDD

IDn = IDp

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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IDn = IDp

-1 Vout = Vin - VT0p

Vout = Vin - VT0n


V th−V T0p

V th
V th−V T0n
V out
=∞ (iff λ = 0)
V in
-1
V th V DD
-VT0n
V IL V IH
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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(1)

V (-1)
' VIL '
kn W kp W IL d V out
  2V in −V T0n =   [2V out −V DD 2V in −V DD −V T0p  ]
2 L n 2 L p d V in
d V out (-1)
¿[−2V out −V DD  ]
d V in

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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RECALL THAT

'
k n W / Ln n W / Ln
k R= ' =
k p W / L p  p W / L p
n  p

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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CURRENT VS. VIN

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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IF Vth is SET ideal Vth

IF, ALSO
Kenneth R. Laker, University of Pennsylvania, updated 09Feb10
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W / L p≈2.5W / Ln

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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EXAMPLE: Compute the noise margins for a symmetric CMOS


inverter has been designed to achieve Vth = VDD/2, where VDD = 5 V
and VT0n = - VT0p = 1 V.

NMH = NML = 2.125 V > VDD/4

RECALL

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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If the inverter cell is part of a


standard cell library, it will be Smaller Area
adhere to the cell layout Layout
protocols.

Kenneth R. Laker, University of Pennsylvania, updated 09Feb10


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Kenneth R. Laker, University of Pennsylvania, updated 09Feb10