LIBRARY ieee;

USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY univ IS
port(clk,pr,cr:in std_logic;i:in std_logic_vector(0 to 3);s:in std_logic_vector(0 to
1);o:inout std_logic);
END ENTITY univ;

--
ARCHITECTURE univ_beh OF univ IS
signal s1,s2,s3: std_logic;
BEGIN
process(clk,pr,cr,i,s)
begin
if(pr='0') then
o<='1';
s1<='1';
s2<='1';
s3<='1';
elsif(cr='0') then
o<='0';
s1<='0';
s2<='0';
s3<='0';
elsif(clk='1' and clk' event) then
if(s="00") then
s1<=s1;
s2<=s2;
s3<=s3;
o<=o;
elsif(s="01") then
s1<=i(0);
s2<=s1;
s3<=s2;
o<=s3;
elsif(s="10") then
s3<=i(3);
s2<=s3;
s1<=s2;
o<=s1;
elsif(s="11") then
s1<=i(0);
s2<=i(1);
s3<=i(2);
 o<=i(3);
end if;
end if;
end process;

END ARCHITECTURE univ_beh;