VERILOG HARDARE DESCRIPTION

LANGUAGE

LECTUER-6

DIVYA SHAH
04/03/09
SWITCH LEVEL MODELING
 SWITCH MODELING ELEMENT
MOS SWITCHES:
keywords nmos,pmos
instantiation of these swithes
nmos n1(out,data,control);
pmos p1(out,data,control);
//since switches are verilog primitives, so
like logic gate instance name is optional
LOGIC TABLES FOR NMOS AND PMOS GATE

• NMOS
CONTROL
0 1 X Z

0 Z 0 L L
DATA

1 Z 1 H H
X Z X X X LZ or 0
Z Z Z Z Z HZ or 1
• PMOS
CONTROL
0 1 X Z

0 0 Z L L
1 1 Z H H
DATA

X X Z X X LZ or 0
Z Z Z Z Z HZ or 1
 CMOS SWITCHES

• INSTANTIATION

cmos c1(out,data,ncontrol,pcontrol);
or
cmos c2(out,data,pcontrol,ncontrol);
 BIDIRECTIONAL SWITCHES
• INSTANTIATION

tran t1(inout1,inout2);
tranif0(inout1,inout2,control);
tranif1(inout1,inout2,control);
 EXAMPLE1:CMOS NOR GATE
module my_nor(out,a,b);
output out;
input a,b;
wire c;
//set up power & ground lines
supply1 pwr;
supply0 gnd;
//instantiates power switches
pmos(c,pwr,b);
pmos(out,c,a);
//instantiates nmos switches
nmos(out,gnd,a);
nmos(out,gnd,b);
endmodule