Beruflich Dokumente
Kultur Dokumente
• State-of-the-art
• PLL architecture
• Experimental results
• Summary of performance
“Universal” capability:
• Fine frequency resolution .11b/g .11a f
(1 MHz)
Q
a Na
10
.11a
X2
a
PFD Loop 2.5GHz
25MHz CP filter 5GHz
.11b/g
5 2
b
Nb 2
b
S. Pellerano ISSCC 2005 5
Synthesizer Architecture
Na
2.5MHz
10
.11a
X2
PFD Loop 2.5GHz
25MHz CP filter 5GHz
.11b/g
5 2
Nb 2
10
.11a
X2
5MHz
PFD Loop 2.5GHz
25MHz CP filter 5GHz
.11b/g
5 2
0.5MHz
Nb 2
+fin
N+1/2
0 t fin = fref
N+1
–fin
+Tin
Tin findt
0
t
–Tin Qinj Tin
CP1 CP2
lock Iup
I1 lock 1 gmVc
ref
PFD lock VC 1
Filter
Loop
Lock
detect gm
div CI
2 Idown
I1
lock Vref
Standard mode
CP1 CP2
Iup
I1 lock 1
ref
PFD lock VC 1
Filter
Loop
Lock
detect gm
div CI
2 Idown
I1
lock Vref
Averaging mode
CP1 CP2
Iup
I1 lock 1
ref
PFD lock VC 1
Filter
Loop
Lock
detect gm
div CI
2 Idown
I1
lock Vref
2 -
VC CI VDD 1
1
R0
VDD/2
Idown
M1 M2 M3
DIVs
PFD+CPs
5-GHz 2.5-GHz
VCO VCO
5-GHz frequency
pad driver doubler
2.5-GHz
pad driver
-30
-40 35dB
-50
-60
-70
-80
2482.0 2483.0 2482.0 2483.0
Frequency [MHz]
S. Pellerano ISSCC 2005 15
L (f) [d B c /H z ]
Phase Noise
-70
-90
-110 1.09° rms
-130
-150
2.4825GHz
L(f) [d B c /H z ]
-70
-90
-110
1.25° rms
-130
5.825GHz
-150
1k 10k 100k 1M 10M
Frequency [Hz]
3
Standard mode Averaging mode
2
Frequency step [MHz]
0
3
Dual mode
2
Std.
Ave.
1
Ave. 0
0 50 100 150 200
Time [us]