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A Dual-Band Frequency Synthesizer

for 802.11a/b/g with Fractional-Spur


Averaging Technique

Stefano Pellerano, Salvatore Levantino, Carlo Samori,


Andrea L. Lacaita

Politecnico di Milano, Italy


Outline

• LO design issues in universal WLAN radios

• State-of-the-art

• PLL architecture

• Fractional spurs compensation technique

• Experimental results

• Summary of performance

S. Pellerano ISSCC 2005 2


Design Issues
Zero/low-IF architecture:
• BB RF
High LO frequency
(2.4 – 5.9 GHz)
LO

“Universal” capability:
• Fine frequency resolution .11b/g .11a f
(1 MHz)
Q

High spectrum efficiency:


• Low phase noise I
(1 rms)

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State-of-the-Art
• high division ratio ( 2500)
Integer-N
• higher power consumption

Fractional-N • lower division ratio and power consumption


• fractional spurs compensation required

– in-band noise folding


- scrambling
– area and power overhead

DAC, DLL, – not enough spur suppression


Multiphase VCO – low achievable fractionality depth

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Synthesizer Architecture

a Na

10
.11a
X2
a
PFD Loop 2.5GHz
25MHz CP filter 5GHz
.11b/g
5 2
b

Nb 2
b
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Synthesizer Architecture
Na

2.5MHz
10
.11a
X2
PFD Loop 2.5GHz
25MHz CP filter 5GHz
.11b/g
5 2

Nb 2

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Synthesizer Architecture
Na

10
.11a
X2
5MHz
PFD Loop 2.5GHz
25MHz CP filter 5GHz
.11b/g
5 2

0.5MHz

Nb 2

S. Pellerano ISSCC 2005 7


Periodic Phase Error
N+1 L=4
N t N = N+1/2

+fin
N+1/2
0 t fin = fref
N+1
–fin


+Tin
Tin  findt
0
t
–Tin Qinj  Tin

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Averaging Technique
1 TON
L Phases reset
2

CP1 CP2
lock Iup
I1 lock 1 gmVc
ref
PFD lock VC 1

Filter
Loop
Lock
detect gm
div CI
2 Idown
I1
lock Vref

S. Pellerano ISSCC 2005 9


Averaging Technique

Standard mode

CP1 CP2
Iup
I1 lock 1
ref
PFD lock VC 1

Filter
Loop
Lock
detect gm
div CI
2 Idown
I1
lock Vref

S. Pellerano ISSCC 2005 10


Averaging Technique

Averaging mode

CP1 CP2
Iup
I1 lock 1
ref
PFD lock VC 1

Filter
Loop
Lock
detect gm
div CI
2 Idown
I1
lock Vref

S. Pellerano ISSCC 2005 11


Charge Injection
Idown = (VDD/2 – VC)/R0 CP2 VDD
Iup = VDD/(2R0) Iup

Qinj = VC/R0  TON


VDD 1 1
Qinj
From CP1 A1
M4
+

2 -
VC CI VDD 1
1
R0
VDD/2
Idown
M1 M2 M3

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Experimental Results
Chip Microphotograph

DIVs
PFD+CPs

5-GHz 2.5-GHz
VCO VCO

5-GHz frequency
pad driver doubler

2.5-GHz
pad driver

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Fractional Spurs Suppression
10
0
-10
-20
Power [dBm]

-30
-40 35dB
-50
-60
-70
-80
2482.0 2483.0 2482.0 2483.0
Frequency [MHz]
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L (f) [d B c /H z ]
Phase Noise

-70
-90
-110 1.09° rms
-130
-150
2.4825GHz
L(f) [d B c /H z ]

-70
-90
-110
1.25° rms
-130
5.825GHz
-150
1k 10k 100k 1M 10M
Frequency [Hz]

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Frequency Transient

3
Standard mode Averaging mode
2
Frequency step [MHz]

0
3
Dual mode
2
Std.
Ave.
1
Ave. 0
0 50 100 150 200
Time [us]

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Performance Summary
2.5-GHz 5-GHz
Crystal frequency 25 MHz
Frequency range 2405–2550MHz 4180–6120MHz

Frequency resolution 0.5 MHz 5 MHz

Bandwidth 50 kHz 100 kHz


Fractional Ave. OFF -25 dBc -48 dBc
spur Ave. ON -60 dBc -
Integrated noise 1.09° rms 1.25° rms

Current Consumption (2.5V) 15.7 mA 23.8 mA

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