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SOLUTIONS:

QUESTION 1:

HALF ADDER

module half(a,b,out,c);
input a,b;
output out,c;
xor(out,a,b);
and(c,a,b);
endmodule

module testbench();
reg a,b;
wire out,c;
half test(a,b,out,c);
initial
begin
a=0;b=0;
#10 a=0;b=1;
#10 a=1;b=0;
#10 a=1;b=1;
#10 $finish;
end
endmodule
FULL SUBTRACTOR

module fs(a,b,c,d,b0);
input a,b,c;
output d,b0;
assign d=a^b^c;
assign b0=(~a&c)|(~a&b)|(b&c);
endmodule

module testbench();
wire d,b0;
reg a,b,c;
fs test(a,b,c,d,b0);
initial
begin
a=0;b=0;c=0;
#10 a=0;b=0;c=1;
#10 a=0;b=1;c=0;
#10 a=0;b=1;c=1;
#10 a=1;b=0;c=0;
#10 a=1;b=0;c=1;
#10 a=1;b=1;c=0;
#10 a=1;b=1;c=1;
#50 $finish;
end
endmodule
QUESTION 2

HALF SUBTRACTOR

module halfsub(a,b,d,bo);
input a,b;
output d,bo;
wire na;
xor (d,a,b);
not (na,a);
and (bo,b,na);
endmodule

module testbench();
reg a,b;
wire bo,d;
halfsub test(a,b,d,bo);
initial
begin
a=0; b=0;
#10 a=0; b=1;
#10 a=1; b=0;
#10 a=1; b=1;
#10 $finish;
end
endmodule
FULL ADDER

module fa(a,b,c,s,out);
input a,b,c;
output s,out;
wire g,e,d;
xor(d,a,b);
xor(s,c,d);
and(e,a,b);
and(g,c,d);
or(out,g,e);
endmodule

module testbench();
reg a,b,c;
wire s,out;
fa test(a,b,c,s,out);
initial
begin
a=0;b=0;c=0;
#10 a=0;b=0;c=1;
#10 a=0;b=1;c=0;
#10 a=0;b=1;c=1;
#10 a=1;b=0;c=0;
#10 a=1;b=0;c=1;
#10 a=1;b=1;c=0;
#10 a=1;b=1;c=1;
#50 $finish;
end
endmodule
QUESTION 3:

8:1 MUX
module mux(i,s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7);
input s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7;
output i;
reg x;
assign i=(y0&~s0&~s1&~s2)|(y1&~s0&~s1&s2)|(y2&~s0&s1&~s2)|(y3&~s0&s1&s2)|
(y4&s0&~s1&~s2)|(y5&s0&~s1&s2)|(y6&s0&s1&~s2)|(y7&s0&s1&s2);
endmodule

module testbench();
reg s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7;
wire i;
mux test(i,s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7);
initial
begin
s2=0;s1=0;s0=0;y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;
#10 s2=0;s1=0;s0=1;y7=0;y6=1;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;
#10 s2=0;s1=1;s0=0;y7=0;y6=0;y5=1;y4=0;y3=0;y2=0;y1=0;y0=0;
#10 s2=0;s1=1;s0=1;y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;
#10 s2=1;s1=0;s0=0;y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;
#10 s2=1;s1=0;s0=1;y7=0;y6=0;y5=0;y4=0;y3=0;y2=1;y1=0;y0=0;
#10 s2=1;s1=1;s0=0;y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;
#10 s2=1;s1=1;s0=1;y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;
#50 $finish;
end
endmodule

QUESTION 4
8:1 MUX USING 4:1 MUX
module m21(i0,i1,s,o);
input i0,i1,s;
output o;
reg o;
always@(i0 or i1 or s)
case(s)
1'b0:o=i0;
1'b1:o=i1;
endcase
endmodule

module m41(i0,i1,i2,i3,s,o);
input i0,i1,i2,i3;
input [1:0]s;
output o;
reg o;
always@(i0 or i1 or i2 or i3 or s)
case(s)
2'b00:o=i0;
2'b01:o=i1;
2'b10:o=i2;
2'b11:o=i3;
endcase
endmodule

module m81(x,s,o);
input [7:0]x;
input [2:0]s;
output o;
wire t0,t1;
m41 m1(x[0],x[1],x[2],x[3],s[1:0],t0);
m41 m2(x[4],x[5],x[6],x[7],s[1:0],t1);
m21 m3(t0,t1,s[2],o);
endmodule

module testbench();
reg [7:0]x;
reg [2:0]s;
wire o;
m81 mux81(x,s,o);
initial
begin
x=01011001;
s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;
#10 $finish;
end
endmodule

QUESTION 5
3 TO 8 DECODER

module dec(x,d);
input [2:0]x;
output [7:0]d;
reg d;
always@(x)
begin
if(x==3'b000)
d=8'b00000001;
else if(x==3'b001)
d=8'b00000010;
else if(x==3'b010)
d=8'b00000100;
else if(x==3'b011)
d=8'b00001000;
else if(x==3'b100)
d=8'b00010000;
else if(x==3'b101)
d=8'b00100000;
else if(x==3'b110)
d=8'b01000000;
else if(x==3'b111)
d=8'b10000000;
end
endmodule

module testbench();
reg[2:0]x;
wire [7:0]d;
dec test(x,d);
initial
begin
x=3'b000;
#10 x=3'b001;
#10 x=3'b010;
#10 x=3'b011;
#10 x=3'b100;
#10 x=3'b101;
#10 x=3'b110;
#10 x=3'b111;
#10 $finish;
end
endmodule
QUESTION 6

4 TO 16 DECODER

Similar to the 3-to-8 decoder program. Instead of 3 bits use 4 and instead of 8 bits in the
output have 16 bits.

QUESTION 7
1:4 DEMUX
module demux(d,s,y);
input d;
input [1:0]s;
output [3:0]y;
assign y[0]=d&~s[0]&~s[1];
assign y[1]=d&~s[1]&s[0];
assign y[2]=d&s[1]&~s[0];
assign y[3]=d&s[1]&s[0];
endmodule

module testbench();
reg d;
reg [1:0]s;
wire [3:0]y;
demux test(d,s,y);
initial
begin
d=1;
s=2'b00;
#10 s=2'b01;
#10 s=2'b10;
#10 s=2'b11;
#50 $finish;
end
endmodule

1:8 DEMUX
module demux(d,s,y);
input d;
input [2:0]s;
output [7:0]y;
assign y[0]=d&~s[2]&~s[0]&~s[1];
assign y[1]=d&~s[2]&~s[1]&s[0];
assign y[2]=d&~s[2]&s[1]&~s[0];
assign y[3]=d&~s[2]&s[1]&s[0];
assign y[4]=d&s[2]&~s[1]&~s[0];
assign y[5]=d&s[2]&~s[1]&s[0];
assign y[6]=d&s[2]&s[1]&~s[0];
assign y[7]=d&s[2]&s[1]&s[0];
endmodule

module testbench();
reg d;
reg [2:0]s;
wire [7:0]y;
demux test(d,s,y);
initial
begin
d=1;
s=3'b000;
#10 s=3'b001;
#10 s=3'b010;
#10 s=3'b011;
#10 s=3'b100;
#10 s=3'b101;
#10 s=3'b110;
#10 s=3'b111;
#50 $finish;
end
endmodule

QUESTION 8
BCD TO SEVEN SEGMENT-COMMON CATHODE

module seven(b3,b2,b1,b0,a,b,c,d,e,f,g);
input b3,b2,b1,b0;
output a,b,c,d,e,f,g;
assign a=((~b2)&(~b0))|(b3&(~b0))|(b2&b1)|((~b3)&b1)|((~b3)&b2&b0)|
(b3&(~b2)&(~b1));
assign b=((~b2)&(~b0))|((~b3)&(~b2))|((~b3)&(~b1)&(~b0))|(b3&(~b1)&b0)|
(b1&b0&(~b3));
assign c=(b3&(~b2))|((~b3)&b2)|((~b1)&b0)|((~b3)&(~b1))|((~b3)&b0);
assign d=(b3&(~b1))|((~b2)&(~b1)&(~b0))|(b2&(~b1)&b0)|(b3&(~b2)&b0)|
(b2&b1&(~b0))|((~b3)&(~b2)&b1);
assign e=((~b2)&(~b0))|(b3&b1)|(b3&b2)|(b1&(~b0))|(b1&(~b0)&b3);
assign f=(b3&(~b2))|((~b1)&(~b0))|((~b3)&b2&(~b1))|(b3&b1)|(b1&b2&(~b0));
assign g=(b3&(~b2))|(b1&(~b0))|((~b3)&(~b2)&b1)|(b3&b0)|((~b3)&b2&(~b1));
endmodule

module testbench();
reg b3,b2,b1,b0;
wire a,b,c,d,e,f,g;
seven sgmt(b3,b2,b1,b0,a,b,c,d,e,f,g);
initial
begin
b0=0;b1=0;b2=0;b3=0;
#10 b0=1;b1=0;b2=0;b3=0;
#10 b0=0;b1=1;b2=0;b3=0;
#10 b0=1;b1=1;b2=0;b3=0;
#10 b0=0;b1=0;b2=1;b3=0;
#10 b0=1;b1=0;b2=1;b3=0;
#10 b0=0;b1=1;b2=1;b3=0;
#10 b0=1;b1=1;b2=1;b3=0;
#10 b0=0;b1=0;b2=0;b3=1;
#10 b0=1;b1=0;b2=0;b3=1;
#10 $finish;
end
endmodule

QUESTION 9

BCD TO SEVEN SEGMENT-COMMON ANODE


For common anode, replace 0s by 1s, and 1s by 0s in the logic table.

QUESTION 10
WEIGHTED CODE TO CYCLIC CODE(BINARY TO GRAY)

module binary2gray(a,b,c,d,g0,g1,g2,g3);
input a,b,c,d;
output g0,g1,g2,g3;
xor(g0,a,b);
xor(g1,b,c);
xor(g2,c,d);
assign g3=d;
endmodule

module testbench();
reg a,b,c,d;
wire g0,g1,g2,g3;
binary2gray b2g(a,b,c,d,g0,g1,g2,g3);
initial
begin
$monitor($time,"a=%b,b1=%b,c=%b,d=%b,g0=%b,g1=%b,g2=%b,g3=
%b",a,b,c,d,g0,g1,g2,g3);
end
initial
begin
d=0;c=0;b=0;a=0;
#10 d=0;c=0;b=0;a=1;
#10 d=0;c=0;b=1;a=0;
#10 d=0;c=0;b=1;a=1;
#10 d=0;c=1;b=0;a=0;
#10 d=0;c=1;b=0;a=1;
#10 d=0;c=1;b=1;a=0;
#10 d=0;c=1;b=1;a=1;
#10 d=1;c=0;b=0;a=0;
#10 d=1;c=0;b=0;a=1;
#10 d=1;c=0;b=1;a=0;
#10 d=1;c=0;b=1;a=1;
#10 d=1;c=1;b=0;a=0;
#100 $finish;
end
endmodule

QUESTION 11
CYCLIC CODE TO WEIGHTED CODE(GRAY TO BINARY)

module gray2binary(a,b,c,d,g0,g1,g2,g3);
input g0,g1,g2,g3;
output a,b,c,d;
wire s1,s2;
xor(s1,g3,g2);
xor(s2,g1,g0);
xor(a,s1,s2);
xor(b,s1,g1);
assign c=s1;
assign d=g3;
endmodule

module testbench();
reg g0,g1,g2,g3;
wire a,b,c,d;
gray2binary g2b(a,b,c,d,g0,g1,g2,g3);
initial
begin
$monitor($time,"g0=%b,g1=%b,g2=%b,g3=%b,a=%b,b=%b,c=%b,d=
%b",g0,g1,g2,g3,a,b,c,d);
end
initial
begin
g3=0;g2=0;g1=0;g0=0;
#10 g3=0;g2=0;g1=0;g0=1;
#10 g3=0;g2=0;g1=1;g0=0;
#10 g3=0;g2=0;g1=1;g0=1;
#10 g3=0;g2=1;g1=0;g0=0;
#10 g3=0;g2=1;g1=0;g0=1;
#10 g3=0;g2=1;g1=1;g0=0;
#10 g3=0;g2=1;g1=1;g0=1;
#10 g3=1;g2=0;g1=0;g0=0;
#10 g3=1;g2=0;g1=0;g0=1;
#10 g3=1;g2=0;g1=1;g0=0;
#10 g3=1;g2=0;g1=1;g0=1;
#100 $finish;
end
endmodule

QUESTION 12
WEIGHTED CODE TO SELF COMPLEMENTARY CODE(BCD TO EX-3)

module exc(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire e,f,g,y1,x1,x2,x3,w1;
not h1(e,b);
not h12(f,c);
not h3(g,d);
not h4(z,d);
xor h5(y1,c,d);
not h6(y,y1);
and h7(x1,b,f,g);
or h8(x2,c,d);
and h9(x3,x2,e);
or h10(x,x1,x3);
and h11(w1,x2,b);
or h13(w,w1,a);
endmodule

module testbench();
reg a,b,c,d;
wire w,x,y,z;
exc aa(a,b,c,d,w,x,y,z);
initial
begin
a=0;b=0;c=0;d=0;
#10 a=0;b=0;c=0;d=1;
#10 a=0;b=0;c=1;d=0;
#10 a=0;b=0;c=1;d=1;
#10 a=0;b=1;c=0;d=0;
#10 a=0;b=1;c=0;d=1;
#10 a=0;b=1;c=1;d=0;
#10 a=0;b=1;c=1;d=1;
#10 a=1;b=0;c=0;d=0;
#10 a=1;b=0;c=0;d=1;
#10 a=1;b=0;c=1;d=0;
#10 a=1;b=0;c=1;d=1;
#10 a=1;b=1;c=0;d=0;
#10 $finish;
end
endmodule

QUESTION 13
SELF COMPLEMENTARY CODE TO WEIGHTED CODE(EX-3 TO BCD)

module bcd(w,x,y,z,a,b,c,d);
input w,x,y,z;
output a,b,c,d;
wire e,f,g,a1,a2,b1,b2,b3;
not q1(e,x);
not q2(f,y);
not q3(g,z);
and q4(a1,x,w);
and q5(a2,z,y,w);
or q6(a,a1,a2);
and q7(b1,e,f);
and a8(b2,z,y,x);
and a9(b3,y,g,w);
or a10(b,b1,b2,b3);
xor a11(c,z,y);
not a12(d,z);
endmodule

module testbench();
reg w,x,y,z;
wire a,b,c,d;
bcd aaa(w,x,y,z,a,b,c,d);
initial
begin
w=0;x=0;y=1;z=1;
#10 w=0;x=1;y=0;z=0;
#10 w=0;x=1;y=0;z=1;
#10 w=0;x=1;y=1;z=0;
#10 w=0;x=1;y=1;z=1;
#10 w=1;x=0;y=0;z=0;
#10 w=1;x=0;y=0;z=1;
#10 w=1;x=0;y=1;z=0;
#10 w=1;x=0;y=1;z=1;
#10 w=1;x=1;y=0;z=0;
#10 w=1;x=1;y=0;z=1;
#10 w=1;x=1;y=1;z=0;
#10 w=1;x=1;y=1;z=1;
#10 $finish;
end
endmodule

QUESTION 14
FULL ADDER USING HALF ADDER

module halfadder(xi,yi,si,ci);
input xi,yi;
output si,ci;
and A1(ci,xi,yi);
xor A2(si,xi,yi);
endmodule

module fulladder(x,y,c,s,co);
input x,y,c;
output s,co;
wire st,ct,e;
halfadder H1(x,y,st,ct);
halfadder H2(st,c,s,e);
or O1(co,ct,e);
endmodule

module testbench();
reg a,b,c;
wire s,co;
fulladder aa(a,b,c,s,co);
initial
begin
a=0;b=0;c=0;
#10 a=0;b=0;c=1;
#10 a=0;b=1;c=0;
#10 a=0;b=1;c=1;
#10 a=1;b=0;c=0;
#10 a=1;b=0;c=1;
#10 a=1;b=1;c=0;
#10 a=1;b=1;c=1;
#50 $finish;
end
endmodule

QUESTION 15

4 BIT MAGNITUDE COMPARATOR USING TWO 2 BIT MAGNITUDE


COMPARATOR

Will be posted by tonite…

QUESTION 16
4 BIT RIPPLE CARRY ADDER

module rca(a,b,c,c0,s);
input [3:0]a;
input [3:0]b;
input c0;
output [3:0]s,c;
wire c1,c2,c3;
fa f1(a[0],b[0],c0,s[0],c1);
fa f2(a[1],b[1],c1,s[1],c2);
fa f3(a[2],b[2],c2,s[2],c3);
fa f4(a[3],b[3],c3,s[3],c);
endmodule

module fa(a,b,c,s,out);
input a,b,c;
output s,out;
assign s=a^b^c;
assign out=(a&b)|(b&c)|(c&a);
endmodule

module testbench();
reg [3:0]a;
reg [3:0]b
reg c0;
wire [3:0]s,c;
rca test(a,b,c,c0,s);
initial
begin
c0=0;
a=4'b1001;b=4'b0010;
#10 a=4'b1001;b=4'b0110;
#10 a=4'b1001;b=4'b1001;
#20 $finish;
end
endmodule

QUESTION 17
8 TO 3 ENCODER

module enco83(x,d);
input [7:0]x;
output [2:0]d;
or aa(d[0],x[1],x[3],x[5],x[7]);
or bb(d[1],x[2],x[3],x[6],x[7]);
or cc(d[2],x[4],x[5],x[6],x[7]);
endmodule

module testbench();
reg [7:0]x;
wire [2:0]d;
enco83 aaa(x,d);
initial
begin
x=8'b00000100;
#10 x=8'b00100000;
#10 x=8'b00010000;
#10 x=8'b01000000;
#10 $finish;
end
endmodule

QUESTION 18
ASYNCHRONOUS COUNTER USING JK FLIP FLOP(RIPPLE COUNTER)

module ripple(j,k,clk,clr,cnt);
input j,k,clk,clr;
output [3:0]cnt;
wire [3:0]cnt1;
jkff jk1(j,k,clk,clr,cnt1[0]);
jkff jk2(j,k,~cnt1[0],clr,cnt1[1]);
jkff jk3(j,k,~cnt1[1],clr,cnt1[2]);
jkff jk4(j,k,~cnt1[2],clr,cnt1[3]);
assign cnt[0]=~cnt1[0];
assign cnt[1]=~cnt1[1];
assign cnt[2]=~cnt1[2];
assign cnt[3]=~cnt1[3];
endmodule

module jkff(j,k,clk,clr,q);
input j,k,clk,clr;
output q;
reg q=0;
always @ (posedge clk or clr)
begin
if(clr==1)
q=0;
else
begin
if (j==0 && k==0)
begin
assign q=q;
end
else if(j==0 && k==1)
begin
assign q=0;
end
else if(j==1 && k==0)
begin
assign q=1;
end
else if(j==1 && k==1)
begin
assign q=~q;
end
end
end
endmodule
module testbench();
reg j,k,clk,clr;
wire [3:0]cnt;
ripple aa(j,k,clk,clr,cnt);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
j=0;k=0;clr=1;
#10 j=1;k=1;clr=0;
#500 $finish;
end
endmodule

QUESTION 19
SYNCHRONOUS COUNTER USING T FLIP FLOP

module syn(clk,clr,d,q);
input clk,clr,d;
output [3:0]q;
reg [3:0]q;
tff t1(d,clk,clr,q[0]);
tff t2(q[0],clk,clr,q[1]);
tff t3((q[0]&q[1]),clk,clr,q[2]);
tff t4((q[0]&q[1]&q[2]),clk,clr,q[3]);
endmodule

module tff(t,clk,clr,q);
input t,clk,clr;
output q;
reg q=0;
always @ (negedge clk or clr)
begin
if(clr==0)
q=0;
else
begin
if (t==0)
q=q;
else
q=~q;
end
end
endmodule

module testbench();
reg clk,clr,d;
wire [3:0]q;
syn aa(clk,clr,d,q);
initial
begin
clk=1;
forever #10 clk=~clk;
end
initial
begin
clr=0;d=0;
#10 clr=1;d=1;
#700 $finish;
end
endmodule
QUESTION 20

JK FLIP FLOP TO SR FLIP FLOP

Will be posted by tonite…


JK FLIP FLOP TO T FLIP FLOP

module tjk(t,clk,q);
input clk,t;
output q;
jkff f1(t,t,clk,q);
endmodule

module jkff(j,k,clk,q);
input j,k,clk;
output q;
reg q=0;
always @ (posedge clk)
begin
if (j==0 && k==0)
assign q=q;
else if(j==0 && k==1)
assign q=0;
else if(j==1 && k==0)
assign q=1;
else if(j==1 && k==1)
assign q=~q;
end
endmodule

module testbench();
reg clk,t;
wire q;
tjk f1(t,clk,q);
initial
begin
clk=1'b1;
forever #10 clk<=~clk;
end
initial
begin
t=0;
forever #20 t=~t;
#100 $finish;
end
endmodule
JK FLIP FLOP TO D FLIP FLOP

module djk(d,clk,q);
input clk,d;
output q;
jkff f1(d,~d,clk,q);
endmodule

module jkff(j,k,clk,q);
input j,k,clk;
output q;
reg q=0;
always @ (posedge clk)
begin
if (j==0 && k==0)
assign q=q;
else if(j==0 && k==1)
assign q=0;
else if(j==1 && k==0)
assign q=1;
else if(j==1 && k==1)
assign q=~q;
end
endmodule

module testbench();
reg clk,d;
wire q;
djk f1(d,clk,q);
initial
begin
clk=1'b1;
forever #10 clk<=~clk;
end
initial
begin
d=0;
forever #50 d=~d;
#100 $finish;
end
endmodule
QUESTION 21

PIPO

module pipo(d,clk,clr,q);
input clk,clr;
input [3:0]d;
output [3:0]q;
dff t1(d[0],clk,clr,q[0]);
dff t2(d[1],clk,clr,q[1]);
dff t3(d[2],clk,clr,q[2]);
dff t4(d[3],clk,clr,q[3]);
endmodule

module dff(d,clk,clr,y);
input d,clk,clr;
output y;
reg y;
always @(posedge clk or clr)
if(clr==1)
y=0;
else
begin
y=d;
end
endmodule

module testbench();
reg clk,clr;
reg [3:0]d;
wire [3:0]q;
pipo aa(d,clk,clr,q);
initial
begin
clk=1;
forever #5 clk=~clk;
end
initial
begin
clr=1;d=4'b1010;
#10 clr=0;d=4'b1011;
#10 clr=0;d=4'b0010;
#10 clr=0;d=4'b1000;
#10 $finish;
end
endmodule
QUESTION 22

SISO

module siso(sin,clk,clr,sout);
input sin,clk,clr;
output sout;
wire [2:0]y;
wire a,b,c;
dff t1(sin,clk,clr,y[0]);
assign a=y[0];
dff t2(a,clk,clr,y[1]);
assign b=y[1];
dff t3(b,clk,clr,y[2]);
assign c=y[2];
dff t4(c,clk,clr,sout);
endmodule

module dff(d,clk,clr,y);
input d,clk,clr;
output y;
reg y;
always @(posedge clk or clr)
if(clr==1)
y=0;
else
begin
y=d;
end
endmodule

module testbench();
reg sin,clk,clr;
wire sout;
siso aa(sin,clk,clr,sout);
initial
begin
clk=1;
forever #5 clk=~clk;
end
initial
begin
clr=1;sin=0;
#10 clr=0;sin=1;
#10 clr=0;sin=0;
#10 clr=0;sin=1;
#10 clr=0;sin=0;
#10 clr=0;sin=1;
#50 $finish;
end
endmodule
QUESTION 23

SIPO

module sipo(sin,clk,clr,q);
input sin,clk,clr;
output [3:0]q;
wire a,b,c;
dff t1(sin,clk,clr,q[0]);
assign a=q[0];
dff t2(a,clk,clr,q[1]);
assign b=q[1];
dff t3(b,clk,clr,q[2]);
assign c=q[2];
dff t4(c,clk,clr,q[3]);
endmodule

module dff(d,clk,clr,y);
input d,clk,clr;
output y;
reg y;
always @(posedge clk or clr)
if(clr==1)
y=0;
else
begin
y=d;
end
endmodule

module testbench();
reg sin,clk,clr;
wire [3:0]q;
sipo aa(sin,clk,clr,q);
initial
begin
clk=1;
forever #5 clk=~clk;
end
initial
begin
clr=1;sin=0;
#10 clr=0;sin=1;
#10 clr=0;sin=0;
#10 clr=0;sin=1;
#10 clr=0;sin=0;
#10 clr=0;sin=1;
#50 $finish;
end
endmodule
QUESTION 24:

FULL SUBTRACTOR USING HALF SUBTRACTOR

module halfsub(a,b,d,bo);
input a,b;
output d,bo;
wire na;
xor (d,a,b);
not (na,a);
and (bo,b,na);
endmodule

module fullsub(a,b,c,d,bo);
input a,b,c;
output d,bo;
wire dt,bt,e;
halfsub H1(a,b,dt,bt);
halfsub H2(dt,c,d,e);
or O1(bo,bt,e);
endmodule

module testbench();
reg a,b,c;
wire d,bo;
fullsub aa(a,b,c,d,bo);
initial
begin
a=0;b=0;c=0;
#10 a=0;b=0;c=1;
#10 a=0;b=1;c=0;
#10 a=0;b=1;c=1;
#10 a=1;b=0;c=0;
#10 a=1;b=0;c=1;
#10 a=1;b=1;c=0;
#10 a=1;b=1;c=1;
#50 $finish;
end
endmodule

QUESTION 25

REAL TIME CLOCK


Record
QUESTION 26

PARALLEL ADDER

module parallel_AS_verilog(clk,addr,load,clear,data_in,calc,result);
input clk,clear,calc,load;
input [2:0]addr;
input [11:0]data_in;
output reg [11:0]result;
reg [11:0]ram[7:0];
reg [11:0]temp;

always@(posedge clk)
begin
if(~clear)
begin
ram[0]=12'b0;
ram[1]=12'b0;
ram[2]=12'b0;
ram[3]=12'b0;
ram[4]=12'b0;
ram[5]=12'b0;
ram[6]=12'b0;
ram[7]=12'b0;
end
else if(~load)
ram[addr]=data_in;
temp=ram[0]+ram[1]+ram[2]+ram[3]+ram[4]+ram[5]+ram[6]+ram[7];
end

always@(posedge clk)
begin
if(~load)
result=data_in;
else if(~calc)
result=temp;
else
result=ram[addr];
end
endmodule
QUESTION 27

MULTIPLIER

module mul_new_verilog(clk,addr,load,clear,data_in,calc,result);
input clk,clear,calc,load;
input addr;
input [7:0]data_in;
output reg [15:0]result;
reg [7:0]ram[1:0];

always@(posedge clk)
begin
if(~clear)
begin
ram[0]=8'b0;
ram[1]=8'b0;
end
else if(~load)
ram[addr]=data_in;
end

always@(posedge clk)
begin
if(~load)
result={8'b0,data_in};
else if(~calc)
result= multiply_8x8_2sC (ram[0],ram[1]);
else
result={8'b0,ram[addr]};
end
function[15:0] multiply_8x8_2sC;
input[7:0] a,b;
reg[7:0] a_mag,b_mag;
reg[14:0] y_mag;
reg[14:0] y_neg;
begin
case (a[7])
0: a_mag = a[6:0];
1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bits
endcase
case (b[7])
0: b_mag = b[6:0];
1: b_mag = 128 - b[6:0];
endcase
y_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bits
if ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zero
begin
// y_mag >=1, <= 16256, thus need only 14 bits
y_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bits
multiply_8x8_2sC = {1'b1,y_neg};
end
else
multiply_8x8_2sC = y_mag;
end
endfunction
endmodule
QUESTION 28

EVEN PARITY CHECKER 4 BIT(INCLUDING PARITY BIT)

module pge(e,a,b,c,d);
input a,b,c,d;
output e;
assign e=a^b^c^d;
endmodule

module testbench();
reg a,b,c,d;
wire e;
pge test(e,a,b,c,d);
initial
begin
a=0;b=0;c=0;d=0;
#10 a=0;b=0;c=0;d=1;
#10 a=0;b=0;c=1;d=0;
#10 a=0;b=0;c=1;d=1;
#10 a=0;b=1;c=0;d=0;
#10 a=0;b=1;c=0;d=1;
#10 a=0;b=1;c=1;d=0;
#10 a=0;b=1;c=1;d=1;
#10 a=1;b=0;c=0;d=0;
#10 a=1;b=0;c=0;d=1;
#10 a=1;b=0;c=1;d=0;
#10 a=1;b=0;c=1;d=1;
#10 a=1;b=1;c=0;d=0;
#10 a=1;b=1;c=0;d=1;
#10 a=1;b=1;c=1;d=0;
#10 a=1;b=1;c=1;d=1;
#10 $finish;
end
endmodule
QUESTION 29

ODD PARITY CHECKER 4 BIT(INCLUDING PARITY BIT)

module pge(o,a,b,c,d);
input a,b,c,d;
output o;
wire e;
assign e=a^b^c^d;
assign o=~e;
endmodule

module testbench();
reg a,b,c,d;
wire o;
pge test(o,a,b,c,d);
initial
begin
a=0;b=0;c=0;d=0;
#10 a=0;b=0;c=0;d=1;
#10 a=0;b=0;c=1;d=0;
#10 a=0;b=0;c=1;d=1;
#10 a=0;b=1;c=0;d=0;
#10 a=0;b=1;c=0;d=1;
#10 a=0;b=1;c=1;d=0;
#10 a=0;b=1;c=1;d=1;
#10 a=1;b=0;c=0;d=0;
#10 a=1;b=0;c=0;d=1;
#10 a=1;b=0;c=1;d=0;
#10 a=1;b=0;c=1;d=1;
#10 a=1;b=1;c=0;d=0;
#10 a=1;b=1;c=0;d=1;
#10 a=1;b=1;c=1;d=0;
#10 a=1;b=1;c=1;d=1;
#10 $finish;
end
endmodule
QUESTION 30

4 BIT EVEN PARITY GENERATOR

module pge(e,a,b,c,d);
input a,b,c,d;
output e;
assign e=a^b^c^d;
endmodule

module testbench();
reg a,b,c,d;
wire e;
pge test(e,a,b,c,d);
initial
begin
a=0;b=0;c=0;d=0;
#10 a=0;b=0;c=0;d=1;
#10 a=0;b=0;c=1;d=0;
#10 a=0;b=0;c=1;d=1;
#10 a=0;b=1;c=0;d=0;
#10 a=0;b=1;c=0;d=1;
#10 a=0;b=1;c=1;d=0;
#10 a=0;b=1;c=1;d=1;
#10 a=1;b=0;c=0;d=0;
#10 a=1;b=0;c=0;d=1;
#10 a=1;b=0;c=1;d=0;
#10 a=1;b=0;c=1;d=1;
#10 a=1;b=1;c=0;d=0;
#10 a=1;b=1;c=0;d=1;
#10 a=1;b=1;c=1;d=0;
#10 a=1;b=1;c=1;d=1;
#10 $finish;
end
endmodule
QUESTION 31

4 BIT ODD PARITY GENERATOR

module pge(o,a,b,c,d);
input a,b,c,d;
output o;
wire e;
assign e=a^b^c^d;
assign o=~e;
endmodule

module testbench();
reg a,b,c,d;
wire o;
pge test(o,a,b,c,d);
initial
begin
a=0;b=0;c=0;d=0;
#10 a=0;b=0;c=0;d=1;
#10 a=0;b=0;c=1;d=0;
#10 a=0;b=0;c=1;d=1;
#10 a=0;b=1;c=0;d=0;
#10 a=0;b=1;c=0;d=1;
#10 a=0;b=1;c=1;d=0;
#10 a=0;b=1;c=1;d=1;
#10 a=1;b=0;c=0;d=0;
#10 a=1;b=0;c=0;d=1;
#10 a=1;b=0;c=1;d=0;
#10 a=1;b=0;c=1;d=1;
#10 a=1;b=1;c=0;d=0;
#10 a=1;b=1;c=0;d=1;
#10 a=1;b=1;c=1;d=0;
#10 a=1;b=1;c=1;d=1;
#10 $finish;
end
endmodule
QUESTION 32

JOHNSON COUNTER

module johnson(clk,cnt);
input clk;
output [3:0]cnt;
reg [3:0]d;
reg [3:0]cnt;
always@(posedge clk)
begin
d=cnt;
assign cnt[3:1]=cnt[2:0];
assign cnt[0]=~d[3];
end
endmodule

module testbench();
wire [3:0]cnt;
reg clk;
assign cnt=0;
johnson test(clk,cnt);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
#200 $finish;
end
endmodule
QUESTION 33

RING COUNTER

module ring(clk,cnt);
input clk;
output [3:0]cnt;
reg [3:0]d;
reg [3:0]cnt;
always@(posedge clk)
begin
d=cnt;
assign cnt[3:1]=cnt[2:0];
assign cnt[0]=d[3];
end
endmodule

module testbench();
wire [3:0]cnt;
reg clk;
assign cnt=4'b0001;
ring test(clk,cnt);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
#200 $finish;
end
endmodule
QUESTION 34

3 BIT UP/DOWN COUNTER

module counter(clk,cnt,k);
input clk,k;
output [2:0]cnt;
reg cnt=3'b000;
always@(posedge clk)
if(k==0)
begin
cnt=cnt+1;
end
else
begin
cnt=cnt-1;
end
endmodule

module testbench();
wire [2:0]cnt;
reg clk,k;
counter test(clk,cnt,k);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
k=0;
#150 k=1;
#150 $finish;
end
endmodule
QUESTION 35

D FLIP FLOP

module dff(d,clk,q);
input d,clk;
output q;
reg q;
always@(posedge clk)
begin
q<=d;
end
endmodule

module testbench();
reg d,clk;
wire q;
dff test(d,clk,q);
initial
begin
clk=1'b1;
forever #10 clk=~clk;
end
initial
begin
d=1'b0;
forever #50 d=~d;
#200 $finish;
end
endmodule
QUESTION 36

JK FLIP FLOP

module jkff(j,k,clk,clr,q);
input j,k,clk,clr;
output q;
reg q=0;
always @ (posedge clk, clr)
begin
if(clr==1)
q=0;
else
begin
if (j==0 && k==0)
assign q=q;
else if(j==0 && k==1)
assign q=0;
else if(j==1 && k==0)
assign q=1;
else if(j==1 && k==1)
assign q=~q;
end
end
endmodule

module testbench();
reg j,k,clk,clr;
wire q;
jkff test(j,k,clk,clr,q);
initial
begin
clk=1;
forever #5 clk<=~clk;
end
initial
begin
clr=1; j=0; k=0;
#10 clr=0;j=0;k=0;
#10 clr=0;j=1;k=0;
#10 clr=0;j=0;k=1;
#10 clr=0;j=1;k=1;
#10 $finish;
end
endmodule
QUESTION 37

MOD 7 COUNTER

module m7(clk,cnt);
input clk;
output [3:0]cnt;
reg [3:0]cnt;
always@(posedge clk)
if(cnt!=4'd6)
assign cnt=cnt+1;
else
assign cnt=0;
endmodule

module testbench();
wire [3:0]cnt;
reg clk;
m7 test(clk,cnt);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
#400 $finish;
end
endmodule
QUESTION 38

MOD 10 COUNTER

module m10(clk,cnt);
input clk;
output [3:0]cnt;
reg [3:0]cnt;
always@(posedge clk)
if(cnt!=4'd9)
assign cnt=cnt+1;
else
assign cnt=0;
endmodule

module testbench();
wire [3:0]cnt;
reg clk;
m10 test(clk,cnt);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
#400 $finish;
end
endmodule
QUESTION 39

BCD TO EX-3 CONVERTER

module exc(a,b,c,d,w,x,y,z);
input a,b,c,d;
output w,x,y,z;
wire e,f,g,y1,x1,x2,x3,w1;
not h1(e,b);
not h12(f,c);
not h3(g,d);
not h4(z,d);
xor h5(y1,c,d);
not h6(y,y1);
and h7(x1,b,f,g);
or h8(x2,c,d);
and h9(x3,x2,e);
or h10(x,x1,x3);
and h11(w1,x2,b);
or h13(w,w1,a);
endmodule

module testbench();
reg a,b,c,d;
wire w,x,y,z;
exc aa(a,b,c,d,w,x,y,z);
initial
begin
a=0;b=0;c=0;d=0;
#10 a=0;b=0;c=0;d=1;
#10 a=0;b=0;c=1;d=0;
#10 a=0;b=0;c=1;d=1;
#10 a=0;b=1;c=0;d=0;
#10 a=0;b=1;c=0;d=1;
#10 a=0;b=1;c=1;d=0;
#10 a=0;b=1;c=1;d=1;
#10 a=1;b=0;c=0;d=0;
#10 a=1;b=0;c=0;d=1;
#10 a=1;b=0;c=1;d=0;
#10 a=1;b=0;c=1;d=1;
#10 a=1;b=1;c=0;d=0;
#10 $finish;
end
endmodule
QUESTION 40

EX-3 TO BCD COUNTER

module bcd(w,x,y,z,a,b,c,d);
input w,x,y,z;
output a,b,c,d;
wire e,f,g,a1,a2,b1,b2,b3;
not q1(e,x);
not q2(f,y);
not q3(g,z);
and q4(a1,x,w);
and q5(a2,z,y,w);
or q6(a,a1,a2);
and q7(b1,e,f);
and a8(b2,z,y,x);
and a9(b3,y,g,w);
or a10(b,b1,b2,b3);
xor a11(c,z,y);
not a12(d,z);
endmodule

module testbench();
reg w,x,y,z;
wire a,b,c,d;
bcd aaa(w,x,y,z,a,b,c,d);
initial
begin
w=0;x=0;y=1;z=1;
#10 w=0;x=1;y=0;z=0;
#10 w=0;x=1;y=0;z=1;
#10 w=0;x=1;y=1;z=0;
#10 w=0;x=1;y=1;z=1;
#10 w=1;x=0;y=0;z=0;
#10 w=1;x=0;y=0;z=1;
#10 w=1;x=0;y=1;z=0;
#10 w=1;x=0;y=1;z=1;
#10 w=1;x=1;y=0;z=0;
#10 w=1;x=1;y=0;z=1;
#10 w=1;x=1;y=1;z=0;
#10 w=1;x=1;y=1;z=1;
#10 $finish;
end
endmodule
QUESTION 41

4 TO 16 DECODER(BEHAVIORAL MODEL)

QUESTION 42

3 BIT MAGNITUDE COMPARATOR

QUESTION 43

T FLIP FLOP

module tff(t,clk,q);
input t,clk;
output q;
reg q=0;
always@(posedge clk)
begin
if(t==0)
q<=q;
else
q<=~q;
end
endmodule

module testbench();
reg t,clk;
wire q;
tff test(t,clk,q);
initial
begin
clk=1'b0;
forever #50 clk=~clk;
end
initial
begin
t=1'b1;
forever #500 t=~t;
end
endmodule
QUESTION 44

3 BIT UP COUNTER

module counter(clk,cnt,clr);
input clk,clr;
output [2:0]cnt;
reg cnt=3'b000;
always@(posedge clk)
if(clr==1)
cnt=cnt+1;
else
cnt=3'b000;
endmodule

module testbench();
wire [2:0]cnt;
reg clk,clr;
counter test(clk,cnt,clr);
initial
begin
clk=0;
forever #10 clk=~clk;
end
initial
begin
clr=0;
#10 clr=1;
#150 $finish;
end
endmodule

QUESTION 45

8:1 MUX (BEHAVIORAL MODEL)

module mux(i,s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7);
input s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7;
output i;
reg x;
always@(s2 or s1 or s0 or y0 or y1 or y2 or y3or y4 or y5 or y6 or y7)
begin
case(s2,s1,s0)
2’b000: i=y0;
2’b001: i=y1;
2’b010: i=y2;
2’b011: i=y3;
2’b100: i=y4;
2’b101: i=y5;
2’b110: i=y6;
2’b111: i=y7;
endcase
end
endmodule

module testbench();
reg s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7;
wire i;
mux test(i,s0,s1,s2,y0,y1,y2,y3,y4,y5,y6,y7);
initial
begin
s2=0;s1=0;s0=0;y7=1;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;
#10 s2=0;s1=0;s0=1;y7=0;y6=1;y5=0;y4=0;y3=0;y2=0;y1=0;y0=0;
#10 s2=0;s1=1;s0=0;y7=0;y6=0;y5=1;y4=0;y3=0;y2=0;y1=0;y0=0;
#10 s2=0;s1=1;s0=1;y7=0;y6=0;y5=0;y4=1;y3=0;y2=0;y1=0;y0=0;
#10 s2=1;s1=0;s0=0;y7=0;y6=0;y5=0;y4=0;y3=1;y2=0;y1=0;y0=0;
#10 s2=1;s1=0;s0=1;y7=0;y6=0;y5=0;y4=0;y3=0;y2=1;y1=0;y0=0;
#10 s2=1;s1=1;s0=0;y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=1;y0=0;
#10 s2=1;s1=1;s0=1;y7=0;y6=0;y5=0;y4=0;y3=0;y2=0;y1=0;y0=1;
#50 $finish;
end
endmodule

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