IC and ECAD Lab

DEPARTMENT OF ELECTRONICS & COMMUNICATION IC & ECAD LAB
1. OP AMP Applications – Adder, Subtractor,

Comparator Circuits
Aim: To design adder, subtractor and comparator for the given signals by using
operational amplifier.
Apparatus required:
S.No Equipment/Component name Specifications/Value Quantity
1 IC 741 Refer page no 2 1
2 Resistor 1kΩ 4
3 Diode 0A79 2
4 Regulated Power supply (0 – 30V),1A 2
5 Function Generator (.1 – 1MHz), 20V p-p 1
6 Cathode Ray Oscilloscope (0 – 20MHz) 1
7 Multimeter 3 ½ digit display 1
Theory:
Adder: A two input summing amplifier may be constructed using the inverting mode.
The adder can be obtained by using either non-inverting mode or differential amplifier.
Here the inverting mode is used. So the inputs are applied through resistors to the
inverting terminal and non-inverting terminal is grounded. This is called “virtual ground”,
i.e. the voltage at that terminal is zero. The gain of this summing amplifier is 1, any
scale factor can be used for the inputs by selecting proper external resistors.
Subtractor: A basic differential amplifier can be used as a subtractor as shown in the
circuit diagram. In this circuit, input signals can be scaled to the desired values by
selecting appropriate values for the resistors. When this is done, the circuit is referred to
as scaling amplifier. However in this circuit all external resistors are equal in value. So
the gain of amplifier is equal to one. The output voltage Vo is equal to the voltage
applied to the non-inverting terminal minus the voltage applied to the inverting terminal;
hence the circuit is called a subtractor.
Comparator: The circuit diagram shows an op-amp used as a comparator. A fixed

reference voltage Vref is applied to the (-) input, and the other time – varying signal
voltage Vin is applied to the (+) input; Because of this arrangement, the circuit is called
the non-inverting comparator. Depending upon the levels of Vin and Vref, the circuit
1
V.K.R, V.N.B & A.G.K COLLEGE OF ENGINEERING
produces output. In short, the comparator is a type of analog-to-digital converter. At any

given time the output waveform shows whether Vin is greater or less than Vref. The
comparator is sometimes also called a voltage-level detector because, for a desired
value of Vref, the voltage level of the input Vin can be detected.
Circuit Diagrams:
Fig 1: Adder
Fig 2: Subtractor
2
Fig 3: Comparator
Procedures:
A) Adder:
1. Connect the circuit as per the diagram shown in Fig 1.
2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.
3. Apply the inputs V1 and V2 as shown in Fig 1.
4. Apply two different signals (DC/AC ) to the inputs
5. Vary the input voltages and note down the corresponding output at pin 6 of the IC
741 adder circuit.
6. Notice that the output is equal to the sum of the two inputs.
B) Subtractor:
1. Connect the circuit as per the diagram shown in Fig 2.
2. Apply the supply voltages of +15V to pin7 and pin4 of IC741 respectively.
3 Apply the inputs V1 and V2 as shown in Fig 2.
4. Apply two different signals (DC/AC ) to the inputs
5. Vary the input voltages and note down the corresponding output at pin 6 of the IC
741 subtractor circuit.
6. Notice that the output is equal to the difference of the two inputs.
3
C) Comparator:
1. A fixed reference voltage Vref is applied to the (-) input, and to the other input a
varying voltage Vin is applied as shown in Fig 3.
2. Vary the input voltage above and below the Vref and note down the output at pin 6 of
741 IC.
3. Observe that,
when Vin is less than Vref, the output voltage is -Vsat ( ≅ - VEE)
when Vin is greater than Vref, the output voltage is +Vsat (≅ +VCC)
Observations:
Adder:
V1(V) V2(V) Vo(V)
Subtractor:
V1(V) V2(V) Vo(V)
Comparator:
Vin(V) Vref(V) Vo(V)
Model Calculations:
4
a) Adder
Vo = - (V1 + V2)
If V1 = 2.5V and V2 = 2.5V, then
Vo = - (2.5+2.5) = -5V.
b) Subtractor
Vo = V2 – V1
If V1=2.5 and V2 = 3.3, then
Vo = 3.3 – 2.5 = 0.8V
c) Comparator
If Vin < Vref, Vo = -Vsat ≅ - VEE
Vin > Vref, Vo = +Vsat = +VCC
Precautions:
Check the connections before giving the power supply.
Readings should be taken carefully.
Result:
For adder, subtractor and comparator circuits, the practical values are compared
with the theoretical values and they are nearly equal.
Inference:
Different applications of opamp are observed.
5
2. Active Filter Applications – LPF, HPF (first order)

Aim: To design and obtain the frequency response of
i) First order Low Pass Filter (LPF)

ii) First order High Pass Filter (HPF)
Apparatus required:
2 Resistors 10k ohm 3
Variable Resistor 20kΩ pot 1
3 capacitors 0.01μf 1
6 Function Generator (1Hz – 1MHz) 1
Theory:
a) LPF:
A LPF allows frequencies from 0 to higher cut of frequency, fH. At fH the gain is
0.707 Amax, and after fH gain decreases at a constant rate with an increase in frequency.
The gain decreases 20dB each time the frequency is increased by 10. Hence the rate at
which the gain rolls off after fH is 20dB/decade or 6 dB/ octave, where octave signifies a
two fold increase in frequency. The frequency f=fH is called the cut off frequency
because the gain of the filter at this frequency is down by 3 dB from 0 Hz. Other
equivalent terms for cut-off frequency are -3dB frequency, break frequency, or corner
frequency.
b) HPF:
The frequency at which the magnitude of the gain is 0.707 times the maximum
value of gain is called low cut off frequency. Obviously, all frequencies higher than fL are
pass band frequencies with the highest frequency determined by the closed –loop band
width all of the op-amp.
6
Circuit diagrams:
Fig 1: Low pass filter
Fig 2: High pass filter
Design:
First Order LPF: To design a Low Pass Filter for higher cut off frequency fH = 4 KHz
and pass band gain of 2
fH = 1/( 2πRC )
Assuming C=0.01 µF, the value of R is found from
R= 1/(2πfHC) Ω =3.97KΩ
7
The pass band gain of LPF is given by AF = 1+ (RF/R1)= 2

Assuming R1=10 KΩ, the value of RF is found from
RF=( AF-1) R1=10KΩ
First Order HPF: To design a High Pass Filter for lower cut off frequency fL =
4 KHz and pass band gain of 2
fL = 1/( 2πRC )
Assuming C=0.01 µF,the value of R is found from
R= 1/(2πfLC) Ω =3.97KΩ
The pass band gain of HPF is given by AF = 1+ (RF/R1)= 2
Assuming R1=10 KΩ, the value of RF is found from
RF=( AF-1) R1=10KΩ
Procedure:
First Order LPF
1. Connections are made as per the circuit diagram shown in Fig 1.
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not
go into saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown
in Table (a).
4. Plot the frequency response as shown in Fig 3 .
First Order HPF

1. Connections are made as per the circuit diagrams shown in Fig 2.
2. Apply sinusoidal wave of constant amplitude as the input such that op-amp does not
go into saturation.
3. Vary the input frequency and note down the output amplitude at each step as shown
in Table (b).
4. Plot the frequency response as shown in Fig 4.
Tabular Form and Sampled Values:
8
a)LPF b) HPF
Input voltage Vin = 0.5V
Frequenc O/P Voltage Gain Frequency O/P Voltage Gain

y Voltage(V) Gain indB Voltage(V) Gain indB
Vo/Vi Vo/Vi
100Hz 500Hz
200Hz 700Hz
300Hz 800Hz
500Hz 1KHz
750Hz 2KHz
900Hz 3KHz
1KHz 4KHz
2KHz 5KHz
3KHz 6KHz
4KHz 7KHz
5KHz 8KHz
6KHz 9KHz
7KHz 10KHz
8KHz
9KHz Model graphs :
10KHz
Fig (3)
Fig(4)
Frequency response characteristics Frequency response characteristics
of LPF of HPF
Precautions:
Result: First order low-pass filter and high-pass filter are designed and frequency
response characteristics are obtained.
9
Inferences: By interchanging R and C in a low-pass filter, a high-pass filter can be

obtained.
3. Function Generator using OPAMPs
Aim: To generate square wave and triangular wave form by using OPAMPs.
Apparatus required:
10
1 741 IC Refer page no 2 2

2 Capacitors 0.01μf,0.001μf Each one
3 Resistors 86kΩ ,68kΩ ,680kΩ Each one
Resistors 100kΩ 2
5 Cathode Ray Oscilloscope (0 -20MHz) 1
Theory: Function generator generates waveforms such as sine, triangular, square

waves and so on of different frequencies and amplitudes. The circuit shown in Fig1 is a
simple circuit which generates square waves and triangular waves simultaneously. Here
the first section is a square wave generator and second section is an integrator. When
square wave is given as input to integrator it produces triangular wave.
Circuit Diagram:
Fig1: Function generator
Design:
Square wave Generator:
T= 2RfC ln (2R2 +R1/ R1)
Assume R1 = 1.16 R2
Then T= 2RfC
Assume C and find Rf
Assume R1 and find R2
Integrator:
11
Take R3 Cf >> T
R3 Cf = 10T
Assume Cf find R3
Take R3Cf = 10T
Assume Cf = 0.01μf
R3 = 10T/C
= 20KΩ
Procedure:
1. Connect the circuit as per the circuit diagram shown above.
2. Obtain square wave at A and Triangular wave at Vo2 as shown in Fig 1.
3. Draw the output waveforms as shown in Fig 2(a) and (b).
Model Calculations:
For T= 2 m sec
T = 2 Rf C
Assuming C= 0.1μf
Rf = 2.10-3/ 2.01.10-6
= 10 KΩ
Assuming R1 = 100 K
R2 = 86 KΩ
Sample readings:
Square Wave:
Vp-p = 26 V(p-p)
T = 1.8 msec
Triangular Wave:
Vp-p = 1.3 V
T= 1.8 msec
Wave Forms:
12
Fig 2 (a): Output at ‘A’

(b): Output at V02
Precautions:
.
Result: Square wave and triangular wave are generated and the output waveforms
are observed.
Inferences: Various waveforms can be generated.
4. IC 555 Timer-Monostable Operation Circuit

Aim: To generate a pulse using Monostable Multivibrator by using IC555
Apparatus required:
13
S.No Equipment/Component Specifications/Value Quantity

name
3 Resistor 10kΩ 1
5 Function Generator (1HZ – 1MHz) 1
6 Cathode ray oscilloscope (0 – 20MHz) 1
Theory: A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-

generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand by mode the output of the
circuit is approximately Zero or at logic-low level. When an external trigger pulse is
obtained, the output is forced to go high ( ≅ VCC). The time for which the output remains
high is determined by the external RC network connected to the timer. At the end of the
timing interval, the output automatically reverts back to its logic-low stable state. The
output stays low until the trigger pulse is again applied. Then the cycle repeats. The
Monostable circuit has only one stable state (output low), hence the name monostable.
Normally the output of the Monostable Multivibrator is low.
14
Circuit Diagram:
Fig1: Monostable Circuit using IC555

Design:
Consider VCC = 5V, for given tp
Output pulse width tp = 1.1 RA C
Assume C in the order of microfarads & Find RA
15
Typical values:
If C=0.1 µF , RA = 10k then tp = 1.1 mSec
Trigger Voltage =4 V
Procedure:
1. Connect the circuit as shown in the circuit diagram.
2. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
3. Observe the output waveform and measure the pulse duration.
4. Theoretically calculate the pulse duration as Thigh=1.1. RAC
5. Compare it with experimental values.
Waveforms:
Fig 2 (a): Trigger signal

(b): Output Voltage
(c): Capacitor Voltage
Sample Readings:
16
Trigger Output wave Capacitor output

0 to 5V range 0 to 5V range 0 to 3.33 V range
1)1V,0.09msec 4.6V, 0.5msec 3V, 0.88 msec
Precautions:
Result: The input and output waveforms of 555 timer monostable Multivibrator are
observed as shown in Fig 2(a), (b), (c).
Inferences: Output pulse width depends only on external components RA and C
connected to IC555.
17
5. IC 555 Timer - Astable Operation Circuit
Aim: To generate unsymmetrical square and symmetrical square waveforms using

IC555.
Apparatus required:
2 Resistors 3.6kΩ,7.2kΩ Each one
4 Diode OA79 1
Theory:
When the power supply V CC is connected, the external timing capacitor ‘C”
charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(≈VCC) as Reset R=0, Set S=1 and this combination makes Q =0 which has unclamped
the timing capacitor ‘C’.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q =1. It makes Q1 ON and capacitor ‘C’ starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this current
18
and prevent damage to the discharge transistor Q1. The minimum value of RA is
approximately equal to VCC/0.2 where 0.2A is the maximum current through the ON
transistor Q1.
During the discharge of the timing capacitor C, as it reaches VCC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0
unclamps the external timing capacitor C. The capacitor C is thus periodically charged
and discharged between 2/3 VCC and 1/3 VCC respectively. The length of time that the
output remains HIGH is the time for the capacitor to charge from 1/3 VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of V CC
volts is given by VC = VCC [1- exp (-t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f= 1/T = 1.44/ (RA + 2RB) C
Circuit Diagram:
19
Fig.1 555 Astable Circuit
Design:
Formulae: f= 1/T = 1.44/ (RA+2RB) C
Duty cycle (D) = tc/T = RA + RB/(RA+2RB)
Procedure:
I) Unsymmetrical Square wave
1. Connect the circuit as per the circuit diagram shown without connecting the diode
OA 79.
2. Observe and note down the waveform at pin 6 and across timing capacitor.
3. Measure the frequency of oscillations and duty cycle and then compare with the
given values.
4. Sketch both the waveforms to the same time scale.
II) Symmetrical square waveform generator:
1. Connect the diode OA79 as shown in Figure to get D=0.5 or 50%.

2. Choose Ra=Rb = 10KΩ and C=0.1μF
3. Observe the output waveform, measure frequency of oscillations and the duty cycle
and then sketch the o/p waveform.
20
Model calculations:
Given f=1 KHz. Assuming c=0.1μF and D=0.25
∴ 1 KHz = 1.44/ (RA+2RB) x 0.1x10-6 and 0.25 =( RA+RB)/ (RA+2RB)
Solving both the above equations, we obtain RA & RB as
RA = 7.2K Ω
RB = 3.6K Ω
Waveforms:
Fig 2(a): Unsymmetrical square wave output

(b): Capacitor voltage of Unsymmetrical square wave output
(c): Symmetrical square wave output
Sample Readings:
Parameter Unsymmetrical Symmetrical
21
Voltage VPP 5V 5V
Tc=0.8ms Tc = 0.5ms
td=0.2ms td = 0.5ms
Time period T 1 ms 1 ms
Duty cycle 80% 50%
Precautions:
Result: Both unsymmetrical and symmetrical square waveforms are obtained and time
period at the output is calculated.
Inferences: Unsymmetrical square wave of required duty cycle and symmetrical

square waveform can be generated.
22
6. IC 566 – VCO Applications
Aim: i) To observe the applications of VCO-IC 566

ii) To generate the frequency modulated wave by using IC 566
Apparatus required:
S.No Equipment/Component Name Specifications/Value Quantity
2 Resistors 10KΩ 2
1.5KΩ 1
3 Capacitors 0.1 μF 1
100 pF 1
4 Regulated power supply 0-30 V, 1 A 1
5 Cathode Ray Oscilloscope 0-20 MHz 1
6 Function Generator 0.1-1 MHz 1
Theory: The VCO is a free running Multivibrator and operates at a set frequency fo
called free running frequency. This frequency is determined by an external timing
capacitor and an external resistor. It can also be shifted to either side by applying a d.c
control voltage vc to an appropriate terminal of the IC. The frequency deviation is directly
proportional to the dc control voltage and hence it is called a “voltage controlled
oscillator” or, in short, VCO.
The output frequency of the VCO can be changed either by R1, C1 or the
voltage VC at the modulating input terminal (pin 5). The voltage VC can be varied by
connecting a R1R2 circuit. The components R1 and C1 are first selected so that VCO
output frequency lies in the centre of the operating frequency range. Now the
modulating input voltage is usually varied from 0.75 VCC which can produce a frequency
variation of about 10 to 1.
23
Circuit Diagram:
Fig1: Voltage Controlled Oscillator

Design:
1. Maximum deviation time period =T.
2. fmin = 1/T.
where fmin can be obtained from the FM wave
3. Maximum deviation, ∆f= fo - fmin
4. Modulation index β = ∆f/fm
5. Band width BW = 2(β+1) fm = 2 (∆f+fm)
24
6. Free running frequency,fo = 2(VCC -Vc) / R1C1VCC

Procedure:
1. The circuit is connected as per the circuit diagram shown in Fig1.
2. Observe the modulating signal on CRO and measure the amplitude and
frequency of the signal.
3. Without giving modulating signal, take output at pin 4, we get the carrier wave.
4. Measure the maximum frequency deviation of each step and evaluate the
modulating Index.
mf = β = ∆f/fm
Waveforms:
Fig 2 (a): Input wave of VCO

(b): Output of VCO at pin3
(c): Output of VCO at pin4
25
Sample readings:
VCC=+12V; R1=R3=10KΩ; R2=1.5KΩ; fm=1KHz
Free running frequency, fo = 26.1KHz
fmin = 8.33KHz
∆f= 17.77 KHz
β = ∆f/fm = 17.77
Band width BW ≈ 36 KHz
Precautions:
Result:
Frequency modulated waveforms are observed and modulation Index, B.W
required for FM is calculated for different amplitudes of the message signal.
Inferences:
During positive half-cycle of the sine wave input, the control voltage will increase,
the frequency of the output waveform will decrease and time period will increase. Exactly
opposite action will take place during the negative half-cycle of the input as shown in Fig
(b).
26
7. Voltage Regulator using IC723

Aim: To design a low voltage variable regulator of 2 to 7V using IC 723.
Apparatus required:

1 IC 723 Refer appendix A 1
2 Resistors 3.3KΩ,4.7KΩ, Each one

100 Ω
3 Variable Resistors 1KΩ, 5.6KΩ Each one
4 Regulated Power supply 0 -30 V,1A 1
5 Multimeter 3 ½ digit display 1
Theory:
A voltage regulator is a circuit that supplies a constant voltage regardless of

changes in load current and input voltage variations. Using IC 723, we can design both
low voltage and high voltage regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of voltages
Vo < Vref, where as for high voltage regulator, it is VO > Vref. The voltage Vref is generally
about 7.5V. Although voltage regulators can be designed using Op-amps, it is quicker
and easier to use IC voltage Regulators.
IC 723 is a general purpose regulator and is a 14-pin IC with internal short circuit
current limiting, thermal shutdown, current/voltage boosting etc. Furthermore it is an
adjustable voltage regulator which can be varied over both positive and negative voltage
ranges. By simply varying the connections made externally, we can operate the IC in
27
the required mode of operation. Typical performance parameters are line and load
regulations which determine the precise characteristics of a regulator. The pin
configuration and specifications are shown in the Appendix-A.
Circuit Diagram:
Fig1: Voltage Regulator
Design of Low voltage Regulator :-

Assume Io= 1mA,VR=7.5V
RB = 3.3 KΩ
For given Vo
R1 = ( VR – VO ) / Io
R2 = VO / Io
Procedure:
a) Line Regulation:
1. Connect the circuit as shown in Fig 1.
2. Obtain R1 and R2 for Vo=5V
3. By varying Vn from 2 to 10V, measure the output voltage Vo.
4. Draw the graph between Vn and Vo as shown in model graph (a)
28
5. Repeat the above steps for Vo=3V
b) Load Regulation: For Vo=5V

1. Set Vi such that VO= 5 V
2. By varying RL, measure IL and Vo
3. Plot the graph between IL and Vo as shown in model graph (b)
4. Repeat above steps 1 to 3 for VO=3V.
Sample Readings:
a) Line Regulation:
Vo set to 5V Vo set to 3V
Vi(V) Vo(V) Vi(V) Vo(V)

0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
29
IL (mA) Vo(V) IL (mA) Vo(V)

46 24
44 b) 22
40 20
35 Load 18
28 16
20 14
18 12
16 10
12 8
8 6
6 4
4 2
2
Regulation:
Vo set to 5V Vo set to 3V
Model graphs:
a) Line Regulation: b) Load Regulation:

30
Precautions:
Results:
Low voltage variable Regulator of 2V to 7V using IC 723 is designed. Load and Line
Regulation characteristics are plotted.
Inferences:
Variable voltage regulators can be designed by using IC 723.
.
31
8. 4 bit DAC using OP AMP
Aim: To design 1) weighted resistor DAC

2) R-2R ladder Network DAC
Apparatus required:
S.No Equipment/Component Specifications/Value Quantity
name
2 Resistors 1KΩ,2KΩ,4KΩ, 8KΩ Each one
3 Regulated Power supply 0-30 V , 1A 1
4 Multimeter(DMM) 3 ½ digit display 1
5 connecting wires
6 Digital trainer Board 1
Theory: Digital systems are used in ever more applications, because of their
increasingly efficient, reliable, and economical operation with the development of the
microprocessor, data processing has become an integral part of various systems Data
processing involves transfer of data to and from the micro computer via input/output
devices. Since digital systems such as micro computers use a binary system of ones
and zeros, the data to be put into the micro computer must be converted from analog to
digital form. On the other hand, a digital-to-analog converter is used when a binary
32
output from a digital system must be converted to some equivalent analog voltage or
current. The function of DAC is exactly opposite to that of an ADC.
A DAC in its simplest form uses an op-amp and either binary weighted resistors
or R-2R ladder resistors. In binary-weighted resistor op-amp is connected in the
inverting mode, it can also be connected in the non inverting mode. Since the number of
inputs used is four, the converter is called a 4-bit binary digital converter.
Circuit Diagrams:
Fig 1: Binary weighted resistor DAC
33
Fig 2: R – 2R Ladder DAC
Design:
1. Weighted Resistor DAC
b b b b
Vo = -Rf 
A
+ B + c + D ]
8 R 4R 2R R
For input 1111, Rf = R = 4.7KΩ

1 1 1 Rf
Vo = -  + + + 1 ] x5
8 4 2 R
Vo = - 9.375 V
2.R-2R Ladder Network:

b b b b
Vo = -Rf 
A
+ B + c + D ] X5
16 R 8 R 4 R 2 R
For input 1111, Rf = R= 1KΩ
Procedure:
1. Connect the circuit as shown in Fig 1.
34
2. Vary the inputs A, B, C, D from the digital trainer board and note down the output at
pin 6. For logic ‘1’, 5 V is applied and for logic ‘0’, 0 V is applied.
3. Repeat the above two steps for R – 2R ladder DAC shown in Fig 2.
Observations:
Weighted resistor DAC
S.No D C B A Theoretical Voltage(V) Practical Voltage(V)
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
35
R-2R Ladder Network:

S.No D C B A Theoretical Voltage(V) Practical Voltage(V)
1 0 0 0 0
2 0 0 0 1
3 0 0 1 0
4 0 0 1 1
5 0 1 0 0
6 0 1 0 1
7 0 1 1 0
8 0 1 1 1
9 1 0 0 0
10 1 0 0 1
11 1 0 1 0 -
12 1 0 1 1
13 1 1 0 0
14 1 1 0 1
15 1 1 1 0
16 1 1 1 1
Model Graph:
Decimal Equivalent of Binary inputs
36
Precautions:
Results:
Outputs of binary weighted resistor DAC and R-2R ladder DAC are observed.
Inferences:
Different types of digital-to-analog converters are designed.
.
37
1.D FLIP-FLOP
AIM: To Simulate internal structure of D FLIP FLOP(IC 7474) using VHDL and verify
Its operation.
APPARATUS:
S.NO COMPONENT QUANTITY

1. IC 7474 1
2. Digital Trainer Board 1
SOFTWARE USED: Active-HDL

THEORY:
The IC7474 contains two independent positive-edge-triggered D-type flip-flops with
complementary outputs. The information on the D input is accepted by the flip-flops on
the positive going edge of the clock pulse. The triggering occurs at a voltage level and is
not directly related to the transition time of the rising edge of the clock. The data on the
D input may be changed while the clock is low or HIGH without affecting the outputs as
long as the data setup and hold times are not violated. A LOW logic level on the preset
or clear inputs will set or reset the outputs regardless of the logic levels of the other
inputs. 74LS74 is a dual positive edge triggered D-type FF. It’s features are individual
data Clock Set and reset inputs and Complementary Q and Q΄outputs .The clock input is
38
level-sensitive. The positive transition of clock pulse between 0.8V and 2.0V should be
equal.
D-FLIP FLOP DETAILS:
PIN DIAGRAM:
TRUTH TABLE:
INPUTS OUTP
UTS
PR CL CL D Q Q*
R K
L H X X H L
H L X X L H
L L X X H H
H H H H L
H H L L H
H H L X Q0 Q0
*
H = HIGH Logic Level X = Either LOW or HIGH Logic Level Clear
L = LOW Logic Level ↑ = Positive-going transition of the clock.
Q0 = The output logic level of Q before the indicated input conditions were and
established.
39
INTERNAL DIAGRAM:
D FLIP- FLOP Output Equations:
D = Qt+1
40
VHDL CODE:
EXPECTED RESULTS (HARDWARE):
INPUTS OUTPUTS
PR CLR CLK D Q Q*
0 1 X X 5V 0V
1 0 X X 0V 5V
0 0 X X 5V 5V
1 1 1 5V 0V
1 1 0 0V 5V
1 1 0 X Q0 Q0*
EXPECTED RESULTS (SOFTWARE):
When pr = 0, clr = 1 irrespective of clock and D input Q = 1, Q* = 0.

When pr = 1, clr = 1, clock transition is positive and D = 1, Q = 1, Q* = 0.

When pr = 1, clr = 1, clock transition is positive and D = 0, Q = 0, Q* = 1.
When pr = 1, clr = 1, clock = 0, irrespective of D input Q = Q0, Q* = Q0*
Q0 = The output logic level of Q before the indicated input conditions were and
established.
41
RESULTS (HARDWARE):
INPUTS OUTPUTS
PR CLR CLK D Q LED Q* LED
0 1 X X
1 0 X X
0 0 X X
1 1 1
1 1 0
1 1 0 X
RESULTS (SOFTWARE):
RESULT:
D FLIP-FLOP Internal Structure is Simulated and Verified Using Active HDL

Software and in Hardware Lab Respectively.
INFERENCE:
Theoretical and Practical Results are according to the expected results both for Software
and Hardware.
PRECAUTIONS (SOFTWARE):
1) Follow Getting Started Procedure for the Software you are using.
2) Don’t Forget to instantiate IEEE Libraries at the starting of
the code
1) Follow Syntax and Semantics of the VHDL code throughout
42
PRECAUTIONS (HARDWARE):
1) Apply the voltages to the IC as per the details given in the data
Sheets.
2) Apply the inputs to the respective pins.
3) First decide which one is MSB and LSB.
4)Take the outputs at appropriate pins.
PROCEDURE (SOFTWARE):
1)Follow Getting Started Procedure for the Software you are

using.
2) Don’t forget to instantiate IEEE Libraries at the starting of
the code.
PROCEDURE (HARDWARE):
1) Connect the circuit as per the pin diagram.

2) Give proper VCC voltage to the IC.
3) Supply the inputs according to truth table and verify outputs.
2.DECADE COUNTER
43
AIM: To Simulate internal structure of Decade Counter(IC 7490) using VHDL and verify
Its operation.
APPARATUS:
HARDWARE:

1. IC 7490 1
SOFTWARE: Active-HDL
THEORY:
7490 is a 4-bit ripple type decade counter.
Features are:
Output QA is connected to input B for BCD count. Output QD is connected
to input A for qi-binary count. This counter has a gated ‘O’ reset. This
counter contains 4 master-slave FF’s and additional gating to provide a
divide by two counter.
TRUTH TABLE:
44
COUNT OUTPUT
QD QC QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
H = HIGH; L = LOW
INTERNAL DIAGRAM:
Decade Counter Output Equations:
OUTPUT Q = 0000 when INPUTS ro(1)= 1, ro(2) = 1 and rg(1)= 0 ;
45
OUTPUT Q = 1001 when INPUTS rg(1)= 1 and rg(2) = 1;

OUTPUT Q = Q + 1 when clock is HIGH
VHDL CODE:
COUNT OUTPUT
QD QC QB QA
0
1
2
3
4
5
6
7
8
9
Reset inputs Output

RO(1) RO(2) RG(1) RG(2) QD QC QB QA
H H L X L L L L
H H X L L L L L
X X H H H L L H
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT
46
Fig: Compilation Report of Decade Counter
RESULTS (HARDWARE):
COUNT OUTPUT
QD LED QC LED QB LED QA LED
0
1
2
3
4
5
6
7
8
9
RESULTS (SOFTWARE):
RESULT:
Decade Counter internal structure is Simulated and verified using Active-HDL

INFERENCE:
Theoretical and Practical Results are according to the expected results both for Software
and Hardware.
47
the code.
3) Follow Syntax and Semantics of the VHDL code throughout.
1) Apply the voltages to the IC as per the details given in the data sheets.
4) Take the outputs at appropriate pins.
2) Don’t forget to instantiate IEEE Libraries at the starting of the code.

48
3.SHIFT REGISTER
AIM: To Simulate Internal structure of Shift Register(IC 7495) using VHDL and verify
Its operation.
APPARATUS:

1. IC 7495 1
49
THEORY:
- IC 7495 is a 4-bit shift register with serial and parallel synchronous operating modes.
- It has serial data (DS) and 4 parallel data (D0-D3) inputs and 4 parallel outputs (Q0-
Q3).
TRUTH TABLE:
50
INTERNAL DIAGRAM:
51
SHIFT REGISTER OUTPUT EQUATIONS:

QA = (A(MC) + (MC) (SI))`
QB = (B(MC) + (MC) (QA))`
QC = (C(MC) + (MC) (QB))`
QD = (D(MC) + (MC) (QC))`
MC = Mode Control
SI = Serial Input
52
VHDL CODE:
DATAIN inputs are “011010000” in that order.
0 0 0 0
1 0 0 0
1 1 0 0
0 1 1 0
1 0 1 1
0 1 0 1
0 0 1 0
0 0 0 1
0 0 0 0
S = 00 then Parallel load

S = 01 then Serial out
S = 10 then Left Shift
S = 11 then Parallel Out
RESULTS (HARDWARE):
DATAIN inputs are “011010000” in that order.
53
QALED QBLED QCLED QDLED

OFF OFF OFF OFF
ON OFF OFF OFF
ON ON OFF OFF
OFF ON ON OFF
ON OFF ON ON RESULTS
OFF ON OFF ON
OFF OFF ON OFF (SOFTWARE):
OFF OFF OFF ON
OFF OFF OFF OFF
RESULT:
Shift Register internal structure is simulated and verified using Active-HDL Software
and in Hardware Lab Respectively.
INFERENCE:
Theoretical and Practical results are according to the expected results both for Software
and Hardware.
2) Don’t forget to instantiate IEEE Libraries At the starting of the code.
1) Apply the voltages to the IC as per the details given in the data Sheets.
54
1) Follow Getting Started Procedure for the Software you are

using.
2) Don’t Forget to instantiate IEEE Libraries at the starting of
the code.

55
4. 3-to-8 DECODER
AIM: To Simulate the internal structure of a 3- to-8 decoder (IC 74138) using VHDL
and verify its operation.
APPARATUS:

1. IC 74LS138 1
THEORY:
These Schottky-clamped circuits are designed to be used in high-performance memory-

decoding or data-routing applications, requiring very short propagation delay times. In
high-performance memory systems these decoders can be used to minimize the effects
of system decoding. When used with high-speed memories, the delay times of these
decoders are usually less than the typical access time of the memory. This means that
the effective system delay introduced by the decoder is negligible. The DM74LS138
decodes one-of-eight lines; based upon the conditions at the three binary select inputs
and the three enable inputs. Two active-low and one active-high enable inputs reduce
the need for external gates or inverters when expanding. A 24-line decoder can be
implemented with no external inverters, and a 32-line decoder requires only one inverter.
An enable input can be used as a data input for demultiplexing applications. The
DM74LS139 comprises two separate two-line-to-four line decoders in a single package.
The active-low enable input can be used as a data line in demultiplexing applications. All
of these decoders/demultiplexers feature fully buffered inputs, presenting only one
normalized load to its driving circuit. All inputs are clamped with high-performance
Schottky diodes to suppress line-ringing and simplify system design.
56
Absolute Maximum Ratings:
The “Absolute Maximum Ratings” are those values beyond which the safety of the
device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the Electrical Characteristics tables are not guaranteed at
the absolute maximum ratings. The “Recommended Operating Conditions” table will
define the conditions for actual device operation. An N-bit decoder has 2N outputs, only
one of which may be activated at a given time. If the device is active-HIGH, then only
one output may be HIGH at any time. If the device is active-LOW, then only one output
may be LOW at any time.
DECODER DETAILS:
TRUTH TABLE:
INPUTS OUTPUTS
G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X L X X X H H H H H H H H
H X X X X H H H H H H H H
L H L L L H L L L L L L L
L H L L H L H L L L L L L
L H L H L L L H L L L L L
L H L H H L L L H L L L L
L H H L L L L L L H L L L
L H H L H L L L L L H L L
L H H H L L L L L L L H L
L H H H H L L L L L L L H
H = high level , L = low level, X = Don’t Care

G2* = G2*A + G2*B
INTERNAL DIAGRAM:
57
3- 8 Decoder Output Equations:
Y0 = X2` X1` X0` Y4 = X2 X1` X0`
Y1 = X2 ` X1 `X0 Y5 = X2 X1 `X0
Y2 = X2 ` X1 X0` Y6 = X2 X1X0`
Y3 = X2 ` X1X0 Y7 = X2 X1X0
VHDL CODE:
58
INPUTS OUTPUTS
C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Z7 Should be 1 when Sel = 000

RESULTS (HARDWARE):
INPUTS OUTPUTS
G1 G2* C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LED LED LED LED LED LED LED LED
X L X X X
H X X X X
59
L H L L L
L H L L H
L H L H L
L H L H H
L H H L L
L H H L H
L H H H L
L H H H H
H = high level , L = low level, X = Don’t Care

G2* = G2*A + G2*B
RESULTS (SOFTWARE):
RESULT:
3-to-8 DECODER internal structure is Simulated and verified using Active-HDL

INFERENCE:
60
and Hardware.
the code.
3) Follow Syntax and Symantics of the VHDL code throughout.

61
5. 4 BIT COMPARATOR
AIM: To Simulate internal structure of 4 Bit Comparator(IC 7485) using VHDL and
Verify its operation.
APPARATUS:

1. IC 7485 1
62
THEORY:
This four-bit magnitude comparator performs comparison of straight binary or BCD
codes. Three fully-decoded decisions about two, 4-bit words {A, B} are made and are
externally available at three outputs. This device is fully expandable to any number of
bits without external gates. Words of greater length may be compared by connecting
comparators in cascade. The A>B, A<B, and A=B outputs of a stage handling less
significant bits are connected to the corresponding inputs of the next stage handling
more-significant bits. The stage handling the least-significant bits must
have a high level voltage applied to the A=B input.
FOUR BIT COMPARATOR DETAILS:
TRUTH TABLE:
63
COMPARING INPUTS CASCADING OUTPUTS

INPUTS
A3>B3 A2>B2 A1>B1 AO>BO A>B A<B A=B A>B A<B A=B
A3>B3 X X X X X X X X X H L L
A3<B3 X X X X X X X X X L H L
A3=B3 A2>B2 X X X X X X X H L L
A3=B3 A2<B2 X X X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X X L H L
A3=B3 A2=B2 A1=B1 AO>BO X X X H L L
A3=B3 A2=B2 A1=B1 AO<BO X X X L H L
A3=B3 A2=B2 A1=B1 AO=BO H L L H L L
A3=B3 A2=B2 A1=B1 AO=BO L H L L H L

A3=B3 A2=B2 A1=B1 AO=BO L L H L L H
A3=B3 A2=B2 A1=B1 AO=BO H H L L L L
A3=B3 A2=B2 A1=B1 AO=BO L L L H H L
INTERNAL DIAGRAM:
64
65
FOUR BIT COMPARATOR OUTPUT EQUATIONS:
A<B = (A3(A3B3)`)` ((A0B0)À0 + (A0B0)`B0)` (CIAGB) ((A1B1)À1 + (A1B1)`B1)` (A2B2)À2 +

(A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0B0)À0 + (A0B0)`B0)` (CIAEQB) ((A1B1)À1
66
+(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0) (A0B0)`

((A1B1)À1 +(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`
((A1B1)À1(A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` )( (A3B3)À3 +
(A3B3)`B3)`(A2B2)À2)`.
A>B = (B3(A3B3)`)` ((A0B0)À0 + (A0B0)`B0)` (CIALB) ((A1B1)À1 + (A1B1)`B1)` (A2B2)À2 +

(A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((A0B0)À0 + (A0B0)`B0)` (CIAEQB) ((A1B1)À1
+(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)` ((B0) (A0B0)`
((A1B1)À1 +(A1B1)`B1)` (A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`
((A1B1)`B1(A2B2)À2 + (A2B2)`B2)` (A3B3)À3 + (A3B3)`B3)`) ((A3B3)À3 + (A3B3)`B3)`
(A2B2)`B2)`.
(A=B) = (A3B3)À3 + (A3B3)`B3)` (A2B2)À2 + (A2B2)`B2)` ((A1B1)À1 +(A1B1)`B1)`
((A0B0)À0 + (A0B0)`B0)` (CIAEQB).
CIAGB = Cascading Input A Greater than B
CIAEQB = Cascading Input A Equal to B
CIALB = Cascading Input A Less than B
VHDL CODE:

INPUTS
A3>B3 A2>B2 A1>B1 AO>BO A>B A<B A=B
A3>B3 X X X X X X X X X
A3<B3 X X X X X X X X X
A3=B3 A2>B2 X X X X X X X
A3=B3 A2<B2 X X X X X X X
A3=B3 A2=B2 A1>B1 X X X X X
A3=B3 A2=B2 A1<B1 X X X X X
A3=B3 A2=B2 A1=B1 AO>BO X X X
67
A3=B3 A2=B2 A1=B1 AO<BO X X X
A3=B3 A2=B2 A1=B1 AO=BO 1 0 0
A3=B3 A2=B2 A1=B1 AO=BO 0 1 0

A3=B3 A2=B2 A1=B1 AO=BO 0 0 1
A3=B3 A2=B2 A1=B1 AO=BO 1 1 0
A3=B3 A2=B2 A1=B1 AO=BO 0 0 0
Agb should be HIGH when data A is Greater than data B

Alb should be HIGH when data A is less than data B
Aeb should be HIGH when data A is Equal data B
RESULTS (HARDWARE):

INPUTS
A3>B3 A2>B2 A1>B1 AO>BO A>B A<B A=B
A3>B3 X X X X X X X X X
A3<B3 X X X X X X X X X
68
A3=B3 A2>B2 X X X X X X X
A3=B3 A2<B2 X X X X X X X
A3=B3 A2=B2 A1>B1 X X X X X
A3=B3 A2=B2 A1<B1 X X X X X
A3=B3 A2=B2 A1=B1 AO>BO X X X
A3=B3 A2=B2 A1=B1 AO<BO X X X
A3=B3 A2=B2 A1=B1 AO=BO 1 0 0
A3=B3 A2=B2 A1=B1 AO=BO 0 1 0

A3=B3 A2=B2 A1=B1 AO=BO 0 0 1
A3=B3 A2=B2 A1=B1 AO=BO 1 1 0
A3=B3 A2=B2 A1=B1 AO=BO 0 0 0
RESULTS (SOFTWARE):
RESULT:
Four bit Comparator internal structure is Simulated and verified using Active-HDL
INFERENCE:
and Hardware.
69
the code.
Sheets.

using.
the code.
70
6. 8X1 MULTIPLEXER
AIM: To Simulate internal structure of 8X1 MULTIPLEXER (IC 74151) using VHDL and
verify its operation.
APPARATUS:

1. IC 74151 1
71
THEORY:
74LS51 is a logical implementation of a single-pole, 8-position switch with Switch

position controlled by the state of three select inputs S0,S1,S2.
- Multi function capability.
- Complementary outputs.
DETAILS:
TRUTH TABLE:
INPUT OUTPUT
SELECT STROBE W Y
C B A S
X X X H H L
L L L L DO’ DO
L L H L D1΄ D1
L H L L D2΄ D2
L H H L D3΄ D3
H L L L D4΄ D4
H L H L D5΄ D5
H H L L D6΄ D6
H H H L D7΄ D7
72
INTERNAL DIAGRAM:
OUTPUT EQUATIONS:
D0 = A`B`C` D1 = AB`C` D2 = A`BC` D3 = ABC` D4 = A`B`C
D5 = AB`C D6 = A`BC D7 = ABC
VHDL CODE:
INPUT OUTPUT
SELECT STROBE
C B A S
W Y
X X X 1
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
73
1 1 1 0
a='0' and b='0' and c='0' y=d(0);

a='0' and b='0' and c='1' y=d(1);
a='0' and b='1' and c='0' y=d(2);
a='0' and b='1' and c='1' y=d(3);
a='1' and b='0' and c='0' y=d(4);
a='1' and b='0' and c='1' y=d(5);
a='1' and b='1' and c='0' y=d(6);
a='1' and b='1' and c='1' y=d(7);
RESULTS (HARDWARE):
INPUT OUTPUT
SELECT STROBE
C B A S
W Y
X X X 1
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0 `
74
1 1 1 0
RESULTS (SOFTWARE):
RESULT:
8X1 MULTIPLEXER internal structure is simulated and verified using Active-HDL

INFERENCE:
and Hardware.
1)Follow Getting Started Procedure for the Software you are using.
2)Don’t forget to instantiate IEEE Libraries at the starting of
the code.
3)Follow Syntax and Semantics of the VHDL code throughout.
75
using.
the code.
76
6. 2X4 DEMULTIPLEXER
AIM: To Simulate internal structure of 2X4 DEMULTIPLEXER (IC 74155) using VHDL
and Verify its operation.
APPARATUS:

1. IC 74155 1
THEORY:
The LS155 and LS156 are Dual 1-of-4 Decoder/Demultiplexers with common Address
inputs and separate gated Enable inputs. When enabled, each decoder section accepts
the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active
77
LOW outputs (O0–O3). If the Enable requirements of each decoder are not met, all
outputs of that decoder are HIGH.
Each decoder section has a 2-input enable gate. The enable gate for Decoder “a”
requires one active HIGH input and one active LOW input (Ea•Ea). In demultiplexing
applications, Decoder “a” can accept either true or complemented data by using the Ea
or Ea inputs respectively. The enable gate for Decoder “b” requires two active LOW
inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by
tying Ea to Eb and relabeling the common connection
as (A2). The other Eb and Ea are connected together to form the common enable.The
LS155 and LS156 can be used to generate all four minterms of two variables. These
four minterms are useful in some applications replacing multiple gate functions.
2X4 DEMULTIPLEXER DETAILS:

TRUTH TABLE:
ADDRESS ENABLE a OUTPUT a ENABLE b OUTPUT b

A0 A1 Ea Ea` O0` O1` O2` O3` Eb` Eb` O0` O1` O2` O3`
X X L X H H H H H X H H H H
X X X H H H H H X H H H H H
L L H L L H H H L L L H H H
H L H L H L H H L L H L H H
L H H L H H L H L L H H L H
H H H L H H H L L L H H H L
INTERNAL DIAGRAM:
78
OUTPUT EQUATIONS:
VHDL CODE:
ADDRESS ENABLE a OUTPUT a ENABLE b OUTPUT b

A0 A1 Ea Ea` Eb` Eb`
X X 0 X 1 X
X X X 1 X 1
0 0 1 0 0 0
1 0 1 0 0 0
0 1 1 0 0 0
1 1 1 0 0 0
79
When SELECT = 00
A =1; B = '0'; C = '0'; D = '0';
When SELECT = 01
B =1; A ='0'; C ='0'; D ='0';
when SELECT =10
C <=1; A = 0; B = 0; D = 0;
When SELECT = 11
D =1; A = 0; B = 0; C = 0;
RESULTS (HARDWARE):
ADDRESS ENABLE OUTPUT a ENABLE OUTPUT b

a b
A0 A1 Ea Ea` Eb` Eb`

X X 0 X 1 X
X X X 1 X 1
0 0 1 0 0 0
1 0 1 0 0 0
0 1 1 0 0 0
1 1 1 0 0 0
RESULTS (SOFTWARE):
80
RESULT:
2X4 DEMULTIPLEXER internal structure is simulated and verified using Active-HDL

INFERENCE:
and Hardware.
2) Don’t forget to instantiate IEEE Libraries At the starting of
the code.
Sheets.
1. Follow Getting Started Procedure for the Software you are
using.
the code.
81

7. RAM (16x4)
AIM: To Simulate Internal structure of 16X4 RAM(IC 74189) using VHDL and
Verify its operation.
APPARATUS:

1. IC 74189 1
THEORY:
The CY7C189 and CY7C190 are extremely high performance 64-bit static RAM’s
organized as 16 words by 4 bits. Easy memory expansion n is provided by an active low
82
chip select (CS) input and three- state outputs. The devices are provided with inverting
(CY7C189) and non inverting (CY7C190) outputs. Writing to the device is accomplished
when the chip select (CS) and write enable (WE) inputs are both low. Data on the four
data inputs (D0 through D3) is written into the memory location specified on the address
pins(A0 through A3). The outputs are preconditioned such that the correct data is present
at the data outputs (O0 through O3) when the write cycle is complete. This precondition
operation insures minimum write recovery times by eliminating the “write recovery
glitch.” Reading the device is accomplished by taking chip select (CS) LOW, while write
enable(WE) remains HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear on the four output pins (O0 through O3) in
inverted (CY7C189) or non-inverted (CY7C190) format. The four output pins remain in
high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW.
16x4 RAM DETAILS:

TRUTH TABLE:
83
INPUT OPERATION CONDITION

OF OUTPUT
CS΄ WE΄
L L WRITE HIGH
IMPEDENCE
L H READ COMPLEMENT
OF STORED
DATA
H X INHIBIT HIGH
IMPENDENCE
INTERNAL DIAGRAM:
RAM OUTPUT EQUATIONS:
Write = CS`WE`
READ = CS`WE
84
INHIBIT = CS WE
VHDL CODE:
INPUT OPERATION CONDITION OF

OUTPUT
CS΄ WE΄
0v 0v
0v +5v
+5v X
X = don’t care
cs ='0'and we ='1'and re ='0'

memory read ='0'
memory write = '1'
cs ='0'and we='0'and re='1'
memory read ='1'
memory write = '0'
85
RESULTS (HARDWARE):
INPUT OPERATION CONDITION

OF OUTPUT
CS΄ WE΄
0v 0v
0v +5v
+5v X
X = don’t care
86
RESULTS (SOFTWARE):
RESULT:
16X4 RAM internal structure is simulated and verified using Active-HDL Software
and in Hardware Lab Respectively.
INFERENCE:
and Hardware.
1)Apply the voltages to the IC as per the details given in the data sheets.
2)Apply the inputs to the respective pins.
3)First decide which one is MSB and LSB.
4)Take the outputs at appropriate pins.
87

88

IC and ECAD Lab

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

IC and ECAD Lab

Hochgeladen von

Copyright:

Verfügbare Formate

DEPARTMENT OF ELECTRONICS & COMMUNICATION IC & ECAD LAB

1. OP AMP Applications – Adder, Subtractor,

Comparator: The circuit diagram shows an op-amp used as a comparator. A fixed

produces output. In short, the comparator is a type of analog-to-digital converter. At any

V1(V) V2(V) Vo(V)

V1(V) V2(V) Vo(V)

Vin(V) Vref(V) Vo(V)

2. Active Filter Applications – LPF, HPF (first order)

i) First order Low Pass Filter (LPF)

Fig 1: Low pass filter

Fig 2: High pass filter

The pass band gain of LPF is given by AF = 1+ (RF/R1)= 2

First Order HPF

Tabular Form and Sampled Values:

Frequenc O/P Voltage Gain Frequency O/P Voltage Gain

Inferences: By interchanging R and C in a low-pass filter, a high-pass filter can be

3. Function Generator using OPAMPs

1 741 IC Refer page no 2 2

Theory: Function generator generates waveforms such as sine, triangular, square

Fig1: Function generator

Fig 2 (a): Output at ‘A’

4. IC 555 Timer-Monostable Operation Circuit

S.No Equipment/Component Specifications/Value Quantity

Theory: A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-

Fig1: Monostable Circuit using IC555

Fig 2 (a): Trigger signal

Trigger Output wave Capacitor output

5. IC 555 Timer - Astable Operation Circuit

Aim: To generate unsymmetrical square and symmetrical square waveforms using

Total time period T = 0.69 (RA + 2 RB) C

f= 1/T = 1.44/ (RA + 2RB) C

Fig.1 555 Astable Circuit

Formulae: f= 1/T = 1.44/ (RA+2RB) C

Duty cycle (D) = tc/T = RA + RB/(RA+2RB)

I) Unsymmetrical Square wave

II) Symmetrical square waveform generator:

1. Connect the diode OA79 as shown in Figure to get D=0.5 or 50%.

Fig 2(a): Unsymmetrical square wave output

Parameter Unsymmetrical Symmetrical

Inferences: Unsymmetrical square wave of required duty cycle and symmetrical

6. IC 566 – VCO Applications

Aim: i) To observe the applications of VCO-IC 566

Fig1: Voltage Controlled Oscillator

6. Free running frequency,fo = 2(VCC -Vc) / R1C1VCC

Fig 2 (a): Input wave of VCO

7. Voltage Regulator using IC723

S.No Equipment/Component name Specifications/Value Quantity

2 Resistors 3.3KΩ,4.7KΩ, Each one

A voltage regulator is a circuit that supplies a constant voltage regardless of

Fig1: Voltage Regulator

Design of Low voltage Regulator :-

5. Repeat the above steps for Vo=3V

b) Load Regulation: For Vo=5V

Vi(V) Vo(V) Vi(V) Vo(V)

IL (mA) Vo(V) IL (mA) Vo(V)

a) Line Regulation: b) Load Regulation:

8. 4 bit DAC using OP AMP

Aim: To design 1) weighted resistor DAC

Fig 1: Binary weighted resistor DAC

Fig 2: R – 2R Ladder DAC

For input 1111, Rf = R = 4.7KΩ

2.R-2R Ladder Network: