1.3. OVERLOADED OPERATORS 2.4.

CONVERSION FUNCTIONS
Description Left Operator Right From To Function
bitwise-and u/l,uv,lv and, nand u/l,uv,lv un,lv sg SIGNED(from)
sg,lv un UNSIGNED(from)
bitwise-or u/l,uv,lv or, nor u/l,uv,lv un,sg lv STD_LOGIC_VECTOR(from)
bitwise-xor u/l,uv,lv xor, xnor u/l,uv,lv un,sg in TO_INTEGER(from)
bitwise-not not u/l,uv,lv na un TO_UNSIGNED(from, size)
in sg TO_SIGNED(from, size)
1.4. CONVERSION FUNCTIONS
From To Function 3. IEEE’S NUMERIC_BIT
1164 PACKAGES QUICK u/l b TO_BIT(from[, xmap]) 3.1. PREDEFINED TYPES
uv,lv bv TO_BITVECTOR(from[, xmap]) UNSIGNED(na to | downto na) Array of BIT
REFERENCE CARD b u/l TO_STDULOGIC(from) SIGNED(na to | downto na) Array of BIT
Revision 2.1 bv,uv lv TO_STDLOGICVECTOR(from) 3.2. OVERLOADED OPERATORS
() Grouping [] Optional bv,lv uv TO_STDULOGICVECTOR(from) Left Op Right Return
{} Repeated | Alternative abs sg sg
bold As is CAPS User Identifier 2. IEEE’S NUMERIC_STD - sg sg
italic VHDL-93 commutative un +,-,*,/,rem,mod un un
c
2.1. PREDEFINED TYPES sg +,-,*,/,rem,mod sg sg
b ::= BIT un +,-,*,/,rem,mod c na un
UNSIGNED(na to | downto na) Array of STD_LOGIC
bv ::= BIT_VECTOR sg +,-,*,/,rem,mod c in sg
SIGNED(na to | downto na) Array of STD_LOGIC
u/l ::= STD_ULOGIC/STD_LOGIC un <,>,<=,>=,=,/= un bool
uv ::= STD_ULOGIC_VECTOR 2.2. OVERLOADED OPERATORS sg <,>,<=,>=,=,/= sg bool
lv ::= STD_LOGIC_VECTOR un <,>,<=,>=,=,/= c na bool
Left Op Right Return
un ::= UNSIGNED sg <,>,<=,>=,=,/= c in bool
abs sg sg
sg ::= SIGNED
- sg sg 3.3. PREDEFINED FUNCTIONS
in ::= INTEGER
un +,-,*,/,rem,mod un un
na ::= NATURAL SHIFT_LEFT(un, na) un
sg +,-,*,/,rem,mod sg sg
sm ::= SMALL_INT SHIFT_RIGHT(un, na) un
un +,-,*,/,rem,mod c na un
(subtype INTEGER range 0 to 1) SHIFT_LEFT(sg, na) sg
sg +,-,*,/,rem,mod c in sg
un <,>,<=,>=,=,/= un bool SHIFT_RIGHT(sg, na) sg
1. IEEE’S STD_LOGIC_1164 sg <,>,<=,>=,=,/= sg bool ROTATE_LEFT(un, na) un
un <,>,<=,>=,=,/= c na bool ROTATE_RIGHT(un, na) un
1.1. LOGIC VALUES ROTATE_LEFT(sg, na) sg
sg <,>,<=,>=,=,/= c In bool
‘U’ Uninitialized ROTATE_RIGHT(sg, na) sg
‘X’/’W’ Strong/Weak unknown 2.3. PREDEFINED FUNCTIONS RESIZE(sg, na) sg
‘0’/’L’ Strong/Weak 0 SHIFT_LEFT(un, na) un RESIZE(un, na) un
‘1’/’H’ Strong/Weak 1 SHIFT_RIGHT(un, na) un
‘Z’ High Impedance 3.4. CONVERSION FUNCTIONS
SHIFT_LEFT(sg, na) sg
‘-’ Don’t care SHIFT_RIGHT(sg, na) sg From To Function
ROTATE_LEFT(un, na) un un,bv sg SIGNED(from)
1.2. PREDEFINED TYPES sg,bv un UNSIGNED(from)
ROTATE_RIGHT(un, na) un
STD_ULOGIC Base type ROTATE_LEFT(sg, na) sg un,sg bv BIT_VECTOR(from)
Subtypes: ROTATE_RIGHT(sg, na) sg un,sg in TO_INTEGER(from)
STD_LOGIC Resolved STD_ULOGIC RESIZE(sg, na) sg na un TO_UNSIGNED(from)
X01 Resolved X, 0 & 1 RESIZE(un, na) un in sg TO_SIGNED(from)
X01Z Resolved X, 0, 1 & Z STD_MATCH(u/l, u/l) bool
UX01 Resolved U, X, 0 & 1 STD_MATCH(ul, ul) bool
UX01Z Resolved U, X, 0, 1 & Z STD_MATCH(lv, lv) bool © 1995-1998 Qualis Design Corporation. Permission to
STD_MATCH(un, un) bool reproduce and distribute strictly verbatim copies of this
STD_ULOGIC_VECTOR(na to | downto na) STD_MATCH(sg, sg) bool document in whole is hereby granted.
Array of STD_ULOGIC
STD_LOGIC_VECTOR(na to | downto na) See reverse side for additional information.
Array of STD_LOGIC
© 1995-1998 Qualis Design Corporation © 1995-1998 Qualis Design Corporation
4. SYNOPSYS’ STD_LOGIC_ARITH 6. SYNOPSYS’ STD_LOGIC_SIGNED 9. MENTOR’S STD_LOGIC_ARITH
4.1. PREDEFINED TYPES 6.1. OVERLOADED OPERATORS 9.1. PREDEFINED TYPES
UNSIGNED(na to | downto na) Array of STD_LOGIC Left Op Right Return UNSIGNED(na to | downto na) Array of STD_LOGIC
SIGNED(na to | downto na) Array of STD_LOGIC abs lv lv SIGNED(na to | downto na) Array of STD_LOGIC
SMALL_INT Integer subtype, 0 or 1 +,- lv lv
lv +,-,* lv lv 9.2. OVERLOADED OPERATORS
4.2. OVERLOADED OPERATORS lv +,-c in lv Left Op Right Return
Left Op Right Return lv +,- c u/l lv abs sg sg
abs sg sg,lv lv <,>,<=,>=,=,/= lv bool - sg sg
- sg sg,lv lv <,>,<=,>=,=,/= c in bool u/l +,- u/l u/l
un +,-,*,/ un un,lv uv +,-,*,/,mod,rem,** uv uv
sg +,-,*,/ sg sg,lv 6.2. CONVERSION FUNCTIONS lv +,-,*,/,mod,rem,** lv lv
sg +,-,*,/ c un sg,lv From To Function un +,-,*,/,mod,rem,** un un
un +,- c in un,lv lv in CONV_INTEGER(from) sg +,-,*,/,mod,rem,** sg sg
sg +,- c in sg,lv un <,>,<=,>=,=,/= un bool
un +,- c u/l un,lv 7. SYNOPSYS’ STD_LOGIC_MISC sg <,>,<=,>=,=,/= sg bool
sg +,- c u/l sg,lv not un un
un <,>,<=,>=,=,/= un bool 7.1. PREDEFINED FUNCTIONS not sg sg
sg <,>,<=,>=,=,/= sg bool AND_REDUCE(lv | uv) u/l un and,nand,or,nor,xor un un
un <,>,<=,>=,=,/= c in bool OR_REDUCE(lv | uv) u/l sg and,nand,or,nor,xor,xnor sg sg
sg <,>,<=,>=,=,/= c in bool XOR_REDUCE(lv | uv) u/l uv sla,sra,sll,srl,rol,ror uv uv
lv sla,sra,sll,srl,rol,ror lv lv
4.3. PREDEFINED FUNCTIONS un sla,sra,sll,srl,rol,ror un un
8. CADENCE’S STD_LOGIC_ARITH
SHL(un, un) un SHR(un, un) un sg sla,sra,sll,srl,rol,ror sg sg
SHL(sg, un) sg SHR(sg, un) sg 8.1. OVERLOADED OPERATORS
EXT(lv, in) lv zero-extend 9.3. PREDEFINED FUNCTIONS
Left Op Right Return
SEXT(lv, in) lv sign-extend u/l +,-,*,/ u/l u/l ZERO_EXTEND(uv | lv | un, na) same
lv +,-,*,/ lv lv ZERO_EXTEND(u/l, na) lv
4.4. CONVERSION FUNCTIONS SIGN_EXTEND(sg, na) sg
lv +,-,*,/c u/l lv
From To Function lv +,-c in lv AND_REDUCE(uv | lv | un | sg) u/l
un,lv sg SIGNED(from) uv +,-,* uv uv OR_REDUCE(uv | lv | un | sg) u/l
sg,lv un UNSIGNED(from) uv +,-,*c u/l uv XOR_REDUCE(uv | lv | un | sg) u/l
sg,un lv STD_LOGIC_VECTOR(from) uv +,-c in uv
un,sg in CONV_INTEGER(from) 9.4. CONVERSION FUNCTIONS
lv <,>,<=,>=,=,/= c in bool
in,un,sg,u un CONV_UNSIGNED(from, size) uv <,>,<=,>=,=,/= c in bool From To Function
in,un,sg,u sg CONV_SIGNED(from, size) u/l,uv,lv,un,sg in TO_INTEGER(from)
in,un,sg,u lv 8.2. PREDEFINED FUNCTIONS u/l,uv,lv,un,sg in CONV_INTEGER(from)
CONV_STD_LOGIC_VECTOR(from, size) SH_LEFT(lv, na) lv bool u/l TO_STDLOGIC(from)
SH_LEFT(uv, na) uv na un TO_UNSIGNED(from,size)
5. SYNOPSYS’ STD_LOGIC_UNSIGNED SH_RIGHT(lv, na) lv na un CONV_UNSIGNED(from,size)
SH_RIGHT(uv, na) uv in sg TO_SIGNED(from,size)
5.1. OVERLOADED OPERATORS in sg CONV_SIGNED(from,size)
ALIGN_SIZE(lv, na) lv
Left Op Right Return ALIGN_SIZE(uv, na) uv na lv TO_STDLOGICVECTOR(from,size)
+ lv lv ALIGN_SIZE(u/l, na) lv,uv na uv TO_STDULOGICVECTOR(from,size)
lv +,-,* lv lv
C-like ?: replacements: © 1995-1998 Qualis Design Corporation. Permission to
lv +,-c in lv
COND_OP(bool, lv, lv) lv reproduce and distribute strictly verbatim copies of this
lv +,- c u/l lv
COND_OP(bool, uv, uv) uv document in whole is hereby granted.
lv <,>,<=,>=,=,/= lv bool
COND(bool, u/l, u/l) u/l
lv <,>,<=,>=,=,/= c in bool
Qualis Design Corporation
8.3. CONVERSION FUNCTIONS Elite Consulting and Training in High-Level Design
5.2. CONVERSION FUNCTIONS
From To Function
From To Function Phone: +1-503-670-7200 FAX: +1-503-670-0809
lv,uv,u/l in TO_INTEGER(from)
lv in CONV_INTEGER(from) E-mail: info@qualis.com Web: http://www.qualis.com
in lv TO_STDLOGICVECTOR(from, size)
in uv TO_STDULOGICVECTOR(from, size) Also available: VHDL Quick Reference Card
Verilog HDL Quick Reference Card

© 1995-1998 Qualis Design Corporation © 1995-1998 Qualis Design Corporation