Beruflich Dokumente
Kultur Dokumente
ENGINEERING COLLEGE
SIVAKASI – 626 140.
DEPARTMENT OF EEE
LAB MANUAL
PREPARED BY
R.MAHENDRAN M.E.,
T.BALASUBRAMANIAN M.E.,
LECTURER/EEE
APPROVED BY
HOD/EEE
R.MAHENDRAN
1 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
INSTRUCTIONS TO THE STUDENTS
1. Candidates should come to the lab with proper Uniform and Good quality Leather
shoes.
2. Punctuality and strict Discipline should be maintained.
3. Study and prepare well before entering into the lab.
4. Complete the observation after completion of the experiment in the lab itself.
5. Be alert till the experiment is completed.
6. Make sure that supply is OFF before touching any terminals.
7. Use proper rating equipments carefully, for which you are duly responsible.
8. Handle the equipments carefully, for which you are duly responsible.
9. Return all the components and make sure that nothing is left on the worktable.
10. In case of any wrong observations you have to switch off the power
supply related with it.
11. Don’t use meter terminals as junctions and place them to read
Conveniently.
R.MAHENDRAN
2 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
SYLLABUS
EC 1314 INTEGRATED CIRCUITS LABORATORY 0 0 3 100
AIM:
To study various digital & linear integrated circuits used in simple
system configuration.
LIST OF EXPERIMENTS:
6. Multiplex/ De-multiplex : Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8
demultiplexer
7. Timer IC application.
Study of NE/SE 555 timer in Astable, Monostable operation.
8. Application of Op-Amp-I
Slew rate verifications, inverting and non-inverting amplifier, Adder,
comparator,
Integrator and Differentiator.
R.MAHENDRAN
3 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
10. Study of VCO and PLL ICs
i. Voltage to frequency characteristics of NE/ SE 566 IC.
ii. Frequency multiplication using NE/SE 565 PLL IC.
P = 45 Total = 45
DETAILED SYLLABUS
Aim
To test of ICs by using verification of truth table of basic ICs.
Exercise
Aim
Minimization of functions using K-map implementation and combination
Circuit.
Exercise
1. Realization of functions using SOP, POS, form.
2. Addition, Subtraction of at least 3 bit binary number using basic gate IC’s.
Aim
Realizing code conversion of numbers of different bar.
Exercise
3b) Encoders and Decoders: Decimal and Implementation of 4-bit shift registers
SISO, SIPO, PISO, PIPO modes using suitable IC’s.
R.MAHENDRAN
4 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Exercise
1. Decimal to binary Conversion using dedicated IC’s.
2. BCD – 7 Segment display decoder using dedicated decoder IC&
display.
4. Counters: Design and implementation of 4-bit modulo counters as
synchronous and asynchronous types using FF IC’s and specific counter IC
Aim
Design and implementation of 4 bit modulo counters.
Exercise
1. Using flip-flop for up-down count synchronous count.
2. Realization of counter function using dedicated ICs.
5. Shift Registers
Design and implementation of 4-bit shift registers in SISO, SIPO, PISO,
PIPO
modes using suitable IC’s.
Aim
Design and implementation of shift register.
Exercise
1. Shift Register function realization of the above using dedicated IC’s
For SISO, SIPO, PISO, PIPO, modes of atleast 3 bit binary word.
6. Multiplex/ De-multiplex
Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer
Aim
To demonstrate the addressing way of data channel selection for
multiplex De-multiplex operation.
Exercise
1. Realization of mux-demux functions using direct IC’s.
2. Realization of mux-demux using dedicated IC’s for 4:1, 8:1, and vice
versa.
Aim
R.MAHENDRAN
5 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
To design a multi vibrator circuit for square wave and pulse
generation.
Exercise
1. Realization of Astable multivibrator & monostable multivibrator
circuit
using Timer IC.
2. Variation of R, C, to vary the frequency, duty cycle for signal
generator.
8. Application of Op-Amp-I
Aim
Design and Realization of Op-Amp application.
Exercise
1. Verification of Op-Amp IC characteristics.
2. Op-Amp IC application for simple arithmetic circuit.
3. Op-Amp IC application for voltage comparator wave generator and
wave shifting circuits.
Aim
Realization of circuit for digital conversions.
Exercise
1. Design of circuit for analog to digital signal conversion using
dedicated
IC’s.
2. Realization of circuit using dedicated IC for digital analog conversion.
Aim
Demonstration of circuit for communication application
Exercise
1. To realize V/F conversion using dedicated IC’s vary the frequency of
the generated signal.
2. To realize PLL IC based circuit for frequency multiplier, divider.
R.MAHENDRAN
6 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LIST OF EXPERIMENTS
CYCLE I :
3. Astable Multivibrator
4. Monostable Multivibrator
CYCLE II:
2. Code converters.
4. Multiplexer / Demultiplexer
6. Shift Register.
7. Study of Flip-Flops
R.MAHENDRAN
7 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No.1 INVERTING AND NON – INVERTING AMPLIFIER
1. a. INVERTING AMPLIFIER
AIM:
To design an Inverting Amplifier for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
THEORY:
The input signal Vi is applied to the inverting input terminal through R1 and the
non-inverting input terminal of the op-amp is grounded. The output voltage Vo is
fed back to the inverting input terminal through the R f - R1 network, where Rf is
the feedback resistor. The output voltage is given as,
Vo = - ACL Vi
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal.
PROCEDURE:
PIN DIAGRAM:
R.MAHENDRAN
8 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:
DESIGN:
OBSERVATIONS:
Output
S.No Input
Practical Theoretical
Amplitude
1. ( No. of div x Volts per
div )
Time period
2. ( No. of div x Time per
div )
R.MAHENDRAN
9 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
MODEL GRAPH:
Vi
+1V
Vo
+V
-V
RESULT:
The design and testing of the inverting amplifier is done and the input and output
waveforms were drawn.
i).output voltage of the inverting amplifier is …………
R.MAHENDRAN
10 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
1. b. NON - INVERTING AMPLIFIER
AIM:
APPARATUS REQUIRED:
THEORY:
The input signal Vi is applied to the non - inverting input terminal of the op-amp.
This circuit amplifies the signal without inverting the input signal. It is also called
negative feedback system since the output is feedback to the inverting input
terminals. The differential voltage Vd at the inverting input terminal of the op-amp
is zero ideally and the output voltage is given as,
Vo = ACL Vi
Here the output voltage is in phase with the input signal.
PROCEDURE:
PIN DIAGRAM:
R.MAHENDRAN
11 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:
DESIGN:
OBSERVATIONS:
Output
S.No Input
Practical Theoretical
Amplitude
1. ( No. of div x Volts per
div )
Time period
2. ( No. of div x Time per
div )
MODEL GRAPH:
R.MAHENDRAN
12 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
RESULT:
The design and testing of the Non-inverting amplifier is done and the input and
output waveforms were drawn.
i).output voltage of the non-inverting amplifier is …………
R.MAHENDRAN
13 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No.2 DIFFERENTIATOR AND INTEGRATOR
2. a. DIFFERENTIATOR
AIM:
To design a Differentiator circuit for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
THEORY:
Vo = - Rf C1 ( dVi /dt )
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal. A resistor Rcomp = Rf is normally connected to the non-inverting input
terminal of the op-amp to compensate for the input bias current. A workable
differentiator can be designed by implementing the following steps:
PIN DIAGRAM:
R.MAHENDRAN
14 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM OF DIFFERENTIATOR:
DESIGN :
Given fa = 1 KHz
We know the frequency at which the gain is 0 dB, fa = 1 / (2π Rf C1)
Let us assume C1 = 0.1 µF ; then
Rf = _________
Since fb = 20 fa , fb = 20 KHz
We know that the gain limiting frequency fb = 1 / (2π R1 C1)
Hence R1 = _________
Also since R1C1 = Rf Cf ; Cf = _________
R.MAHENDRAN
15 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Hence Vo = - Rf C1 ( dVi /dt )
= - 0.94 cos ωt
PROCEDURE:
OBSERVATIONS:
MODEL GRAPH:
RESULT:
The design of the Differentiator circuit was done and the input and output
waveforms were obtained.
a).amplitude…………
b). frequency………….
R.MAHENDRAN
16 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
2. b. INTEGRATOR
AIM:
To design an Integrator circuit for the given specifications using Op-Amp IC 741.
APPARATUS REQUIRED:
THEORY:
A circuit in which the output voltage waveform is the integral of the input voltage
waveform is the integrator. Such a circuit is obtained by using a basic inverting
amplifier configuration if the feedback resistor Rf is replaced by a capacitor Cf . The
expression for the output voltage is given as,
Vo = - (1/Rf C1 ) ∫ Vi dt
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input signal. Normally between fa and fb the circuit acts as an integrator.
Generally, the value of fa < fb . The input signal will be integrated properly if the
Time period T of the signal is larger than or equal to Rf Cf . That is,
T ≥ Rf Cf
The integrator is most commonly used in analog computers and ADC and signal-
wave shaping circuits.
R.MAHENDRAN
17 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
PIN DIAGRAM:
DESIGN:
[ To obtain the output of an Integrator circuit with component values R 1Cf = 0.1ms ,
Rf = 10 R1 and Cf = 0.01 µF and also if 1 V peak square wave at 1000Hz is applied as
input.]
R.MAHENDRAN
18 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
PROCEDURE:
OBSERVATIONS:
MODEL GRAPH:
vin
2
1
vo
0 0.5 2.5 4.5
0
1.5 3.5 t (ms)
-1
-2
RESULT:
The design of the Integrator circuit was done and the input and output waveforms
were obtained.
a).Input Sine wave ,Output ……………….
b).Input triangular,Output………………..
R.MAHENDRAN
19 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No.3 ASTABLE MULTIVIBRATOR
AIM:
To design an Astable multivibrator circuit for the given specifications using 555
Timer IC.
APPARATUS REQUIRED:
THEORY:
Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3 Vcc is
equal to the time the output is low and is given by,
td = 0.69 (R2) C
The term duty cycle is often used in conjunction with the astable multivibrator. The
duty cycle is the ratio of the time tc during which the output is high to the total time
period T. It is generally expressed in percentage. In equation form,
R.MAHENDRAN
20 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
PIN DIAGRAM:
R.MAHENDRAN
21 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
DESIGN:
Given f= 4 KHz,
Therefore, Total time period, T = 1/f = ____________
PROCEDURE:
OBSERVATIONS:
Time period
Amplitude ( No. of div x
( No. of div x Time per div )
S.No Particulars
Volts per div )
tc td
1. Output Voltage , Vo
2. Capacitor voltage , Vc
R.MAHENDRAN
22 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
MODEL GRAPH:
RESULT:
The design of the Astable multivibrator circuit was done and the output voltage and
capacitor voltage waveforms were obtained.
R.MAHENDRAN
23 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
AIM:
To design a monostable multivibrator for the given specifications using 555 Timer
IC.
APPARATUS REQUIRED:
THEORY:
tp = 1.1 R1 C
At the end of the timing interval, the output automatically reverts back to its logic
low state. The output stays low until a trigger pulse is applied again. Then the cycle
repeats.
Thus the monostable state has only one stable state hence the name monostable.
PIN DIAGRAM:
R.MAHENDRAN
24 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:
DESIGN:
PROCEDURE:
R.MAHENDRAN
25 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
OBSERVATIONS:
Time period
Amplitude ( No. of div x
( No. of div x Time per div )
S.No Particulars
Volts per div )
ton toff
1. Trigger input
2. Output Voltage , Vo
3. Capacitor voltage , Vc
MODEL GRAPH:
RESULT:
The design of the Monostable multivibrator circuit was done and the input and
output waveforms were obtained.
R.MAHENDRAN
26 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
AIM:
To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR, EX-
OR gates.
APPARATUS REQUIRED:
THEORY:
a. AND gate:
b. OR gate:
c. NOT gate:
AND GATE
R.MAHENDRAN
27 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A B Y=A.B
1. 0 0 0
2. 0 1 0
3. 1 0 0
4. 1 1 1
OR GATE
R.MAHENDRAN
28 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A B Y=A+B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 1
NOT GATE
R.MAHENDRAN
29 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A Y = A’
1. 0 1
2. 1 0
NAND GATE
R.MAHENDRAN
30 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LOGIC DIAGRAM:
CIRCUIT DIARAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A B Y = (A . B)’
1. 0 0 1
2. 0 1 1
3. 1 0 1
4. 1 1 0
NOR GATE
R.MAHENDRAN
31 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LOGIC DIAGRAM:
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A B Y = (A + B)’
1. 0 0 1
2. 0 1 0
3. 1 0 0
4. 1 1 0
EX-OR GATE
R.MAHENDRAN
32 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
LOGIC DIAGRAM
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A B Y=A B
1. 0 0 0
2. 0 1 1
3. 1 0 1
4. 1 1 0
R.MAHENDRAN
33 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
d. NAND gate:
A NAND gate is a complemented AND gate. The output of the NAND gate
will be ‘0’ if all the input signals are ‘1’ and will be ‘1’ if any one of the input
signal is ‘0’.
e. NOR gate:
f. EX-OR gate:
A B = ( A . B’ ) + ( A’ . B )
PROCEDURE:
RESULT:
The truth table of all the basic digital ICs were verified.
R.MAHENDRAN
34 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No.6 IMPLEMENTATION OF BOOLEAN FUNCTIONS
AIM:
To design the logic circuit and verify the truth table of the given Boolean expression,
F (A,B,C,D) = Σ (0,1,2,5,8,9,10)
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. AND gate IC 7408
3. OR gate IC 7432
4. NOT gate IC 7404
5. NAND gate IC 7400
6. NOR gate IC 7402
7. EX-OR gate IC 7486
8. Connecting wires As required
DESIGN:
The output function F has four input variables hence a four variable Karnaugh Map
is used to obtain a simplified expression for the output as shown,
R.MAHENDRAN
35 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM:
TRUTH TABLE:
INPUT OUTPUT
S.No
A B C D F=D’B’+C’(B’+A’D)
1. 0 0 0 0 1
2. 0 0 0 1 1
3. 0 0 1 0 1
4. 0 0 1 1 0
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 0
8. 0 1 1 1 0
9. 1 0 0 0 1
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 0
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 0
R.MAHENDRAN
36 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
PROCEDURE:
RESULT:
R.MAHENDRAN
37 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No. 8 IMPLEMENTATION OF HALF ADDER & FULL ADDER
AIM:
To design and verify the truth table of the Half Adder & Full Adder circuits.
APPARATUS REQUIRED:
THEORY:
The most basic arithmetic operation is the addition of two binary digits. There are
four possible elementary operations, namely,
0+0=0
0+1=1
1+0=1
1 + 1 = 102
The first three operations produce a sum of whose length is one digit, but when the
last operation is performed the sum is two digits. The higher significant bit of this
result is called a carry and lower significant bit is called the sum.
HALF ADDER:
A combinational circuit which performs the addition of two bits is called half adder.
The input variables designate the augend and the addend bit, whereas the output
variables produce the sum and carry bits.
FULL ADDER:
A combinational circuit which performs the arithmetic sum of three input bits is
called full adder. The three input bits include two significant bits and a previous
carry bit. A full adder circuit can be implemented with two half adders and one OR
gate.
R.MAHENDRAN
38 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
HALF ADDER
TRUTH TABLE:
INPUT OUTPUT
S.No
A B S C
1. 0 0 0 0
2. 0 1 1 0
3. 1 0 1 0
4. 1 1 0 1
DESIGN:
From the truth table the expression for sum and carry bits of the output can be
obtained as,
Sum, S = A B
Carry, C = A . B
CIRCUIT DIAGRAM:
FULL ADDER
TRUTH TABLE:
INPUT OUTPUT
S.No
A B C SUM CARRY
1. 0 0 0 0 0
2. 0 0 1 1 0
3. 0 1 0 1 0
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 1
7. 1 1 0 0 1
8. 1 1 1 1 1
R.MAHENDRAN
39 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
DESIGN:
From the truth table the expression for sum and carry bits of the output can be
obtained as,
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
SUM
CARRY
CARRY = AB + AC + BC
CIRCUIT DIAGRAM:
R.MAHENDRAN
40 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
PROCEDURE:
RESULT:
The design of the half adder and full adder circuits was done and their truth tables
were verified.
R.MAHENDRAN
41 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No. 8 IMPLEMENTATION OF HALF SUBTRACTOR &
FULL SUBTRACTOR
AIM:
To design and verify the truth table of the Half Subtractor & Full Subtractor
circuits.
APPARATUS REQUIRED:
THEORY:
The arithmetic operation, subtraction of two binary digits has four possible
elementary operations, namely,
0-0=0
0 - 1 = 1 with 1 borrow
1-0=1
1-1=0
In all operations, each subtrahend bit is subtracted from the minuend bit. In case of
the second operation the minuend bit is smaller than the subtrahend bit, hence 1 is
borrowed.
HALF SUBTRACTOR:
A combinational circuit which performs the subtraction of two bits is called half
subtractor. The input variables designate the minuend and the subtrahend bit,
whereas the output variables produce the difference and borrow bits.
FULL SUBTRACTOR:
A combinational circuit which performs the subtraction of three input bits is called
full subtractor. The three input bits include two significant bits and a previous
borrow bit. A full subtractor circuit can be implemented with two half subtractors
and one OR gate.
R.MAHENDRAN
42 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
HALF SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT
S.No
A B DIFF BORR
1. 0 0 0 0
2. 0 1 1 1
3. 1 0 1 0
4. 1 1 0 0
DESIGN:
From the truth table the expression for difference and borrow bits of the output can
be obtained as,
Difference, DIFF = A B
Borrow, BORR = A’ . B
CIRCUIT DIAGRAM:
R.MAHENDRAN
43 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
FULL SUBTRACTOR
TRUTH TABLE:
INPUT OUTPUT
S.No
A B C DIFF BORR
1. 0 0 0 0 0
2. 0 0 1 1 1
3. 0 1 0 1 1
4. 0 1 1 0 1
5. 1 0 0 1 0
6. 1 0 1 0 0
7. 1 1 0 0 0
8. 1 1 1 1 1
DESIGN:
From the truth table the expression for difference and borrow bits of the output can
be obtained as,
Using Karnaugh maps the reduced expression for the output bits can be obtained as,
DIFFERENCE
BORROW
R.MAHENDRAN
44 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM:
PROCEDURE:
RESULT:
The design of the half subtractor and full subtractor circuits was done and their
truth tables were verified.
R.MAHENDRAN
45 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No. 9 CODE CONVERTERS
AIM:
To design and verify the truth table of a three bit binary to gray code converter.
APPARATUS REQUIRED:
THEORY:
Code converter is a circuit that makes two systems compatible even though each
uses different binary codes. There is a wide variety of binary codes used in digital
systems. Some of these codes are Binary Coded Decimal, Gray code, Excess- 3 code ,
ASCII code, etc.
The Gray code is also called as reflective code. The gray coded number
corresponding to the decimal number 2n – 1, for any n, differs from gray coded 0
(0000) in one bit position only.
DESIGN:
TRUTH TABLE:
R.MAHENDRAN
46 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
From the truth table the expression for the output gray bits are,
X (A, B, C) = Σ (4, 5, 6, 7)
Y (A, B, C) = Σ (2, 3, 4, 5)
Z (A, B, C) = Σ (1, 2, 5, 6)
Hence obtain the reduced SOP expression using Karnaugh maps as follows,
For X:
X=A
For Y:
Y=A B
For Z:
Z=B C
R.MAHENDRAN
47 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
CIRCUIT DIAGRAM:
PROCEDURE:
RESULT:
The design of the three bit Binary to Gray code converter circuit was done and its
truth table was verified.
R.MAHENDRAN
48 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
Expt. No. 10 PARITY GENERATOR & CHECKER
AIM:
To design and verify the truth table of a three bit Odd Parity generator and checker.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1. Digital IC trainer kit 1
2. EX-OR gate IC 7486
3. NOT gate IC 7404
4. Connecting wires As required
THEORY:
A parity bit is used for the purpose of detecting errors during transmission of binary
information. A parity bit is an extra bit included with a binary message to make the
number of 1’s either odd or even. The message including the parity bit is
transmitted and then checked at the receiving end for errors. An error is detected if
the checked parity does not correspond with the one transmitted. The circuit that
generates the parity bit in the transmitter is called a parity generator and the circuit
that checks the parity in the receiver is called a parity checker.
In even parity the added parity bit will make the total number of 1’s an even
amount and in odd parity the added parity bit will make the total number of 1’s an
odd amount.
In a three bit odd parity generator the three bits in the message together with the
parity bit are transmitted to their destination, where they are applied to the parity
checker circuit. The parity checker circuit checks for possible errors in the
transmission.
Since the information was transmitted with odd parity the four bits received must
have an odd number of 1’s. An error occurs during the transmission if the four bits
received have an even number of 1’s, indicating that one bit has changed during
transmission. The output of the parity checker is denoted by PEC (parity error
check) and it will be equal to 1 if an error occurs, i.e., if the four bits received has an
even number of 1’s.
R.MAHENDRAN
49 T.BALA SUBRAMANIAN
DEPT OF EEE/PSREC
ODD PARITY GENERATOR
TRUTH TABLE:
INPUT OUTPUT
S.No ( Three bit message) ( Odd Parity bit)
A B C P
1. 0 0 0 1
2. 0 0 1 0
3. 0 1 0 0
4. 0 1 1 1
5. 1 0 0 0
6. 1 0 1 1
7. 1 1 0 1
8. 1 1 1 0
From the truth table the expression for the output parity bit is,
P( A, B, C) = Σ (0, 3, 5, 6)
CIRCUIT DIAGRAM:
ODD PARITY GENERATOR
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DEPT OF EEE/PSREC
ODD PARITY CHECKER
TRUTH TABLE:
INPUT OUTPUT
( four bit message (Parity error
S.No
Received ) check)
A B C P X
1. 0 0 0 0 1
2. 0 0 0 1 0
3. 0 0 1 0 0
4. 0 0 1 1 1
5. 0 1 0 0 0
6. 0 1 0 1 1
7. 0 1 1 0 1
8. 0 1 1 1 0
9. 1 0 0 0 0
10. 1 0 0 1 1
11. 1 0 1 0 1
12. 1 0 1 1 0
13. 1 1 0 0 1
14. 1 1 0 1 0
15. 1 1 1 0 0
16. 1 1 1 1 1
From the truth table the expression for the output parity checker bit is,
X = (A B C P) ‘
CIRCUIT DIAGRAM:
ODD PARITY CHECKER
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PROCEDURE:
RESULT:
The design of the three bit odd Parity generator and checker circuits was done and
their truth tables were verified.
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Expt. No. 11 MULTIPLEXER & DEMULTIPLEXER
AIM:
To design and verify the truth table of a 4X1 Multiplexer & 1X4 Demultiplexer.
APPARATUS REQUIRED:
THEORY:
Multiplexer is a digital switch which allows digital information from several sources
to be routed onto a single output line. The basic multiplexer has several data input
lines and a single output line. The selection of a particular input line is controlled by
a set of selection lines. Normally, there are 2 n input lines and n selector lines whose
bit combinations determine which input is selected. Therefore, multiplexer is ‘many
into one’ and it provides the digital equivalent of an analog selector switch.
DESIGN:
4 X 1 MULTIPLEXER
LOGIC SYMBOL:
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TRUTH TABLE:
SELECTION
OUTPUT
S.No INPUT
S1 S2 Y
1. 0 0 I0
2. 0 1 I1
3. 1 0 I2
4. 1 1 I3
CIRCUIT DIAGRAM:
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1X4 DEMULTIPLEXER
LOGIC SYMBOL:
TRUTH TABLE:
INPUT OUTPUT
S.No
S1 S2 Din Y0 Y1 Y2 Y3
1. 0 0 0 0 0 0 0
2. 0 0 1 1 0 0 0
3. 0 1 0 0 0 0 0
4. 0 1 1 0 1 0 0
5. 1 0 0 0 0 0 0
6. 1 0 1 0 0 1 0
7. 1 1 0 0 0 0 0
8. 1 1 1 0 0 0 1
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CIRCUIT DIAGRAM:
PROCEDURE:
RESULT:
The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done and their
truth tables were verified.
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Expt. No. 12 STUDY OF FLIP FLOPS
AIM:
APPARATUS REQUIRED:
THEORY:
A Flip Flop is a sequential device that samples its input signals and changes its
output states only at times determined by clocking signal. Flip Flops may vary in
the number of inputs they possess and the manner in which the inputs affect the
binary states.
RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state
with respect to the input on application of clock pulse. When the clock pulse is high
the S and R inputs reach the second level NAND gates in their complementary form.
The Flip Flop is reset when the R input high and S input is low. The Flip Flop is set
when the S input is high and R input is low. When both the inputs are high the
output is in an indeterminate state.
D FLIP FLOP:
JK FLIP FLOP:
RS FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:
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D FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:
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JK FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:
CLOCK INPUT PRESENT NEXT STATUS
PULSE J K STATE (Q) STATE(Q+1)
1 0 0 0 0
2 0 0 1 1
3 0 1 0 0
4 0 1 1 0
5 1 0 0 1
6 1 0 1 1
7 1 1 0 1
8 1 1 1 0
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T FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
CHARACTERISTIC TABLE:
RESULT:
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Expt. No. 13 ASYNCHRONOUS DECADE COUNTER
AIM:
APPARATUS REQUIRED:
THEORY:
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CIRCUIT DIAGRAM:
TRUTH TABLE:
CLOCK OUTPUT
S.No
PULSE D(MSB) C B A(LSB)
1 - 0 0 0 0
2 1 0 0 0 1
3 2 0 0 1 0
4 3 0 0 1 1
5 4 0 1 0 0
6 5 0 1 0 1
7 6 0 1 1 0
8 7 0 1 1 1
9 8 1 0 0 0
10 9 1 0 1 0
11 10 0 0 0 0
PROCEDURE:
RESULT:
The truth table of the Asynchronous decade counter was hence verified.
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Expt. No. 14 IMPLEMENTATION OF SHIFT REGISTERS
AIM:
To implement and verify the truth table of a serial in serial out shift register.
APPARATUS REQUIRED:
THEORY:
A register capable of shifting its binary information either to the left or to the right
is called a shift register. The logical configuration of a shift register consists of a
chain of flip flops connected in cascade with the output of one flip flop connected to
the input of the next flip flop. All the flip flops receive a common clock pulse which
causes the shift from one stage to the next.
The Q output of a D flip flop is connected to the D input of the flip flop to the left.
Each clock pulse shifts the contents of the register one bit position to the right. The
serial input determines, what goes into the right most flip flop during the shift. The
serial output is taken from the output of the left most flip flop prior to the
application of a pulse. Although this register shifts its contents to its left, if we turn
the page upside down we find that the register shifts its contents to the right. Thus a
unidirectional shift register can function either as a shift right or a shift left register.
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CIRCUIT DIAGRAM:
TRUTH TABLE:
PROCEDURE:
RESULT:
The truth table of a serial in serial out left shift register was hence verified.
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