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EC 1354 VLSI DESIGN http://sureshvlsi.hpage.



(As per trichy Annauniversity Syallabus)

for VI th Semester EEE Branch

Assistant Professor (gr-II)
ECE Department
Roever Engineering College
Elambalur, Perambalur.

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NMOS and PMOS transistors – Threshold voltage – Body effect – Design equations–
Second order effects – MOS models and small signal AC characteristics – Basic CMOS


NMOS and CMOS inverters – Stick diagram – Inverter ratio – DC and transient
characteristics – Switching times – Super buffers – Driving large capacitance loads –
CMOS logic structures – Transmission gates – Static CMOS design – Dynamic CMOS


Resistance estimation – Capacitance estimation – Inductance – Switching characteristics
− Transistor sizing – Power dissipation and design margining – Charge sharing – Scaling


Multiplexers – Decoders – Comparators – Priority encoders – Shift registers – Arithmetic
circuits – Ripple carry adders – Carry look ahead adders – High-speed adders –
Multipliers – Physical design – Delay modeling – Cross talk – Floor planning – Power
distribution – Clock distribution – Basics of CMOS testing


Introduction to FPGA – Xilinx FPGA – Xilinx 2000 – Xilinx 3000 – Overview of Digital
Design with Verilog HDL – Hierarchical modeling concepts – Modules and Port definitions –
Gate level modeling – Data flow modeling – Behavioral modeling

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NMOS and PMOS transistors – Threshold voltage – Body effect – Design equations–

Second order effects – MOS models – Small signal AC characteristics – Basic CMOS technology



1.What are four generations of Integration Circuits? [APRIL-2009]

(a) SSI (Small Scale Integration)
(b) MSI (Medium Scale Integration)
(c) LSI (Large Scale Integration)
(d) VLSI (Very Large Scale Integration)

2. Give the advantages of IC[APRIL-2008]?

(a) Size is less
(b) High Speed
(c) Less Power Dissipation

3. Give the variety of Integrated Circuits? [Nov-2004]

More Specialized Circuits
Application Specific Integrated Circuits(ASICs)

4. Give the basic process for IC fabrication [Nov-2005]

(a) Silicon wafer Preparation
(b) Epitaxial Growth
(c) Oxidation
(d) Photolithography

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(e) Diffusion
(f) Ion Implantation
(g) Isolation technique
(h) Metallization
(i) Assembly processing & Packaging

5. What are the various Silicon wafer Preparation? [APRIL-2007]

(a) Crystal growth & doping
(b) Ingot trimming & grinding
(c) Ingot slicing
(d) Wafer polishing & etching
(e) Wafer cleaning.

6. Different types of oxidation? [APRIL-2008]

Dry & Wet Oxidation

7. What is the transistors CMOS technology provides?

n-type transistors & p-type transistors.

8. What are the different layers in MOS transistors?

Drain , Source & Gate

9. What is Enhancement mode transistor? [APRIL-2009]

The device that is normally cut-off with zero gate bias.

10. What is Depletion mode Device?

The Device that conduct with zero gate bias.

11. When the channel is said to be pinched –off? [APRIL-2008]

If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage
effectively pinches off the channel near the drain.

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12. Give the different types of CMOS process? [APRIL-2009]

(a) p-well process
(b) n-well process
(c) Silicon-On-Insulator Process
(d) Twin- tub Process

13. What are the steps involved in twin-tub process?[ Nov-2006]

(a) Tub Formation
(b) Thin-oxide Construction
(c) Source & Drain Implantation
(d) Contact cut definition
(e) Metallization.

14. What are the advantages of Silicon-on-Insulator process? [APRIL-2009]

(a) No Latch-up
(b) Due to absence of bulks transistor structures are denser than bulk silicon.

15. Define Short Channel devices?

Transistors with Channel length less than 3- 5 microns are termed as Short channel
devices. With short channel devices the ratio between the lateral & vertical dimensions
are reduced.
(a) Non- Saturated Region
(b) Saturated Region

16. Define Threshold voltage in CMOS?[ Nov-2005]

The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied
between the gate and the source of the MOS transistor below which the drain to
source current, IDS effectively drops to zero.

17. What is Body effect?

The threshold volatge VT is not a constant w. r. to the voltage difference between the
substrate and the source of MOS transistor. This effect is called substrate-bias effect or

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body effect.

18. What is CMOS Technology?

The fabrication of an IC using CMOS transistors is known as CMOS Technology. CMOS

transistor is nothing but an inverter, made up of an n-MOS and p-MOS transistor connected
in series.

19. Why NMOS technology is preferred more than PMOS technology?

N-channel transistors have greater switching speed when compared to PMOS transistors. Hence,
NMOS is preferred than PMOS.

20.What are the different MOS layers?

(a) n-diffusion
(b) p-diffusion
(c) Polysilicon
(d) Metal

21. What are the different layers in MOS transistor?

The layers are Substrate, diffused Drain & Source, Insulator (SiO2) & Gate.

22.what are the different operating regions for an MOS transistor?

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(a) Cutoff Region

(b) Non- Saturated (Linear) Region
(c) Saturated Region

23. What is Enhancement mode transistor?

The device that is normally cut-off with zero gate bias is called Enhancement
mode transistor.

24. What is Depletion mode device?

The Device that conducts with zero gate bias is called Depletion mode device.

25. When the channel is said to be pinched off?

If a large Vds is applied, this voltage will deplete the inversion layer. This Voltage effectively
pinches off the channel near the drain.

26. What is meant by Epitaxy?

Epitaxy means arranging atoms in single crystal fashion upon a single crystal substrate.

27. What are the processes involved in photo lithography?

These are important processes involved in photolithography.
(a) Masking process
(b) Photo etching process.

28. What is the purpose of masking in fabrication of IC?

Masking is used to identify the location in which Ion-Implantation should not take place.

29. What lire the materials used for masking?

Photo resist, Si02, SiN, Poly Silicon.

30. What are the types of Photo etching?

Wet etching and dry etching are the types of photo etching.

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31. What is diffusion process? What are doping impurities?

Diffusion is a process in which impurities are diffused into the Silicon chip at 1000˚C
temperature. B203 and P205 are used as impurities used.

32. What is Ion-Implantation process?

It is process in which the Si material is doped with an impurity by making the
accelerated impurity atoms to strike the Si layer at high temperature.

33. What is Isolation?

It is a process used to provide electrical isolation between different components and

1. Explain MOS Transistors in detail with neat Diagram
Basic MOSFET Structure In the introduction to a system, we got an overview of various levels of
design, viz. Architectural level design, Program level design, Functional level design and Logic
level design. However we can't understand the levels of design unless we are exposed to the basics
of operation of the devices currently used to realize the logic circuits, viz., MOSFET (Metal Oxide
Semiconductor Field Effect Transistor). So in this section, we'll study the basic structure of
MOSFET. The cross-sectional and top/bottom view of MOSFET are as in figures

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An n-type MOSFET consists of a source and a drain, two highly conducting n-type semiconductor
regions which are separated from the p-type substrate by reverse-biased p-n diodes. A metal or poly
crystalline gate covers the region between the source and drain, but is isolated from the
semiconductor by the gate oxide.
Types of MOSFET MOSFETs are divided into two types viz. p-MOSFET and n-MOSFET
depending upon its type of source and drain.

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2. Explain in detail the MOS Transistor Definitions
• n-type MOS: Majority carriers are electrons.
• p-type MOS: Majority carriers are holes.

• Positive/negative voltage applied to the gate (with respect to substrate) enhances

the number of electrons/holes in the channel and increases conductivity between
source and drain.

•V tdefines the voltage at which a MOS transistor begins to conduct. For voltages
less than V t (threshold voltage), the channel is cut off.

MOS Transistor Definitions

• In normal operation, a positive voltage applied between source and drain (V ds ).
• No current flows between source and drain (I ds = 0) with V gs = 0 because of back
to back pn junctions.

• For n-MOS, with V gs > V tn , electric field attracts electrons creating channel.
• Channel is p-type silicon which is inverted to n-type by the electrons attracted by
the electric field.

n-MOS Enhancement Transistor Physics

• Three modes based on the magnitude of V gs : accumulation, depletion and
n-MOS Enhancement Transistor Physics

n-MOS Enhancement Transistor

• With V ds non-zero, the channel becomes smaller closer to the drain.

• When V ds <= V gs - V t (e.g. V ds = 3V, V gs = 5V and V t = 1V), the channel reaches

the drain (since V gd > V t ).
• his is termed linear , resistive or nonsaturated region. I ds is a function of both V gs
and V ds .
n-MOS Enhancement Transistor
• When V ds > V gs - V t (e.g. V ds = 5V, V gs = 5V and V t = 1V), the channel is
pinched off close to the drain (since V gd < V t ).

• This is termed saturated region. I ds is a function of V gs , almost independent of V ds


MOS Enhancement Transistor

• MOS transistors can be modeled as a voltage controlled switch. I ds is an important
parameter that determines the behavior, e.g., the speed of the switch.

• What are the parameters that effect the magnitude of I ds ? (Assume V gs and V ds are
fixed, e.g. 5V).
• The distance between source and drain (channel length).
• The channel width.
• The threshold voltage.
• The thickness of the gate oxide layer.
• The dielectric constant of the gate insulator.
• The carrier (electron or hole) mobility.

Summary of normal conduction characteristics:

1. Cut-off : accumulation, I ds is essentially zero.
2. Nonsaturated : weak inversion, I ds dependent on both V gs and V ds .
3. Saturated : strong inversion, I ds is ideally independent of V ds .

3. Explain in detail about the Threshold Voltage

V t is also an important parameter. What effects its value?

Most are related to the material properties. In other words, V t is largely determined
at the time of fabrication, rather than by circuit conditions, like I ds .

For example, material parameters that effect V t include:

The gate conductor material (poly vs. metal).
The gate insulation material (SiO 2 ).
The thickness of the gate material.
The channel doping concentration.

However, V t is also dependent on

V sb (the voltage between source and substrate), which is normally 0 in digital devices.
Temperature: changes by -2mV/degree C for low substrate doping levels.

Threshold Voltage
• The expression for threshold voltage is given as:
Threshold Voltage
• Threshold voltage (cont.):

4. Explain in detail the Body Effect

• In digital circuits, the substrate is usually held at zero.
o The sources of n-channel devices, for example, are also
held at zero, except in cases of series connections, e.g.,

• The source-to-substrate (V sb ) may increase at this connections, e.g. V sbN1 = 0 but

V sbN2 /= 0.
• V sb adds to the channel-substrate potential:

5. Explain in detail Basic DC Equations

• Ideal first order equation for cut-off region:

• Ideal first order equation for linear region:

• Ideal first order equation for saturation region:

• with the following definitions:

Basic DC Equations

• Process dependent factors: .

• Geometry dependent factors: W and L.

• Voltage-current characteristics of the n- and p-transistors.

Beta calculation
(e) Transistor beta calculation example: Typical values for an n-transistor in 1
micron technology:

(1) Compute beta:

o How does this beta compare with p-devices:

• n-transistor gains are approximately 2.8 times larger than p-transistors.

Inverter voltage transistor characteristics
• Inverter DC characteristics

Beta Ratios
• Region C is the most important region. A small change in the input voltage, V in ,
results in a LARGE change in the output voltage, V out .

• Thisbehavior describes an amplifier, the input is amplified at the output. The

amplification is termed transistor gain, which is given by beta.

• Boththe n and p-channel transistors have a beta. Varying their ratio will change the
characteristics of the output curve.
Beta Ratios
• Therefore, the

• does NOT affect switching performance.

• What factor would argue for a ratio of 1 for ?

o Load capacitance !

9. The time required to charge or discharge a capacitive load is equal when

• Sincebeta is dependent W and L, we can adjust the ratio by changing the sizes of
the transistor channel widths, by making p-channel transistors wider than n-
channel transistors.



NMOS and CMOS Inverters – Stick diagram – Inverter ratio – DC and transient characteristics
– Switching times – Super buffers – Driving large Capacitance loads – CMOS logic
structures – Transmission gates – Static CMOS design – Dynamic CMOS design



1. What is pull down device?[ Nov-2008]

A device connected so as to pull the output voltage to the lower supply voltage usually
0V is called pull down device.

2. What is pull up device?[ Nov-2006]

A device connected so as to pull the output voltage to the upper supply voltage usually
VDD is called pull up device.

3.What is Stick Diagram? [APRIL-2008]

It is used to convey information through the use of color code. Also it is the cartoon of
a chip layout.

4.What are the uses of Stick diagram?

It can be drawn much easier and faster than a complex layout.
These are especially important tools for layout built from large cells.

5. Give the various color coding used in stick diagram? [APRIL-2009]

Green – n-diffusion
Red- polysilicon
Blue –metal
Yellow- implant
Black-contact areas.

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6. Compare between CMOS and bipolar technologies [Nov-2004]

CMOS Technology Bipolar technology

Low static power dissipation High power dissipation

(e) High input impedance (low drive 4. Low input impedance (high drive
current) current)
(f) Scalable threshold voltage 5. Low voltage swing logic
(g) High noise margin 6. Low packing density
(h) High packing density 7. Low delay sensitivity to load
(i) High delay sensitivity to load 8. High output drive current
(fanout limitations) 9. High gm (gm eVin)
(d) Low output drive current 10. High ft at low current
(e) Low gm (gm Vin) 11. Essentially unidirectional
(f) Bidirectional capability
(g) A near ideal switching device

7.Define Rise time

Rise time,r is the time taken for a waveform to rise from 10% to 90% of its steady- state

8. Define Fall time [Nov-2005]

Fall time, f is the time taken for a waveform to fall from 90% to 10% of its steady-state

9. Define Delay time

Delay time, d is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output.

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10. Give the different symbols for transmission gate. [APRIL-2008]

11. What is Channel-length modulation?

The current between drain and source terminals is constant and independent of the
applied voltage over the terminals. This is not entirely correct. The effective length of the
conductive channel is actually modulated by the applied VDS, increasing VDS causes the
depletion region at the drain junction to grow, reducing the length of the effective

12. What is Latch – up? [Nov-2006]

Latch up is a condition in which the parasitic components give rise to the establishment
of low resistance conducting paths between VDD and VSS with disastrous results. Careful
control during fabrication is necessary to avoid this problem.

13. What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
N Collector area
Buried Sub collector (SCCD)
Processing steps in CMOS process

14. What are the advantages of CMOS process? [Nov-2005]

Low power Dissipation

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High Packing density

Bi directional capability

15. What are the advantages of CMOS process? [APRIL-2007]

Low Input Impedance
Low delay Sensitivity to load.

16. What is the fundamental goal in Device modeling? [APRIL-2009]

To obtain the functional relationship among the terminal electrical variables of the
device that is to be modeled.
17. Define a superbuffer.
A superbuffer is a symmetric inverting or noninverting gate that can
supply or remove large currents and switch large capacitive loads faster
than a standard inverter.

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1.Explain tristate transmission buffer

Input Output
g = 0, gb = 1 g = 1, gb = 0
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1

g g g
a b a b a b
gb gb gb
Pass transistors produce
degraded outputs Transmission gates pass both 0 and 1 well

Tristate buffer produces Z when not enabled

0 0 Z
0 1 Z
1 0 0
1 1 1 A Y


Transmission gate acts as tristate buffer Only two transistors But nonrestoring
Noise on A is passed on to Y

2. Explain the complimentary CMOS inverter DC characteristics.[Nov-2004

CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and
adaptable MOSFET inverters used in chip design. They operate with very little power loss and at
relatively high speed. Furthermore, the CMOS inverter has good logic buffer characteristics, in that,
its noise margins in both low and high states are large.

This short description of CMOS inverters gives a basic understanding of the how a CMOS inverter
works. It will cover input/output characteristics, MOSFET states at different input voltages, and
power losses due to electrical current.

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A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the
NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the
drain terminals.(See diagram). It is important to notice that the CMOS does not contain any
resistors, which makes it more power efficient that a regular resistor-MOSFET inverter.As the
voltage at the input of the CMOS device varies between 0 and 5 volts, the state of the NMOS and
PMOS varies accordingly. If we model each transistor as a simple switch activated by VIN, the
inverter’s operations can be seen very easily:

Transistor "switch model"

The switch model of the MOSFET transistor is defined as follows:

MOSFET Condition on State of


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When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to
logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT
to logic low.

This model of the CMOS inverter helps to describe the inverter conceptually, but does not
accurately describe the voltage transfer characteristics to any extent. A more full description
employs more calculations and more device states.

Multiple state transistor model

The multiple state transistor model is a very accurate way to model the CMOS inverter. It reduces
the states of the MOSFET into three modes of operation: Cut-Off, Linear, and Saturated: each of
which have a different dependence on Vgs and Vds. The formulas which govern the state and the
current in that given state is given by the following tabel:

NMOS Characteristics
Condition on Condition on Mode of
VGS VDS Operation

ID = 0 VGS < VTN All Cut-off

ID = kN [2(VGS - VTN ) VDS - VGS > VTN VDS < VGS -VTN Linear
VDS2 ]

ID = kN (VGS - VTN )2 VGS > VTN VDS > VGS -VTN Saturated

PMOS Characteristics
Condition on Condition on Mode of
VSG VSD Operation

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ID = 0 VSG < -VTP All Cut-off

ID = kP [2(VSG + VTP ) VSD - VSG > -VTP VSD < VSG +VTP Linear
VSD2 ]

ID = kP (VSG + VTP )2 VSG > -VTP VSD > VSG +VTP Saturated

In order to simplify calculations, I have made use of an internet circuit simulation device called
"MoHAT." This tool allows the user to simulate circuits containing a few transistors in a simple and
visually appealing way. The circuits shown below show the state of each transistor (black for cut-
off, red for linear, and green for saturation) accompanied by the voltage transfer characteristic curve
(VOUT vs. VIN). The vertical line plotted on the VTC corresponds to the value of VIN on the
circuit diagram. The following series of diagrams depict the CMOS inverter in varying input
voltages ranging from low to high in ascending order.

Table of figures
figure mode of operation Logic output level
1 VIN < VIL High
2 VIN < VIL High
3 VIL < VIN <VIH <undetermined>
4 VIN > VIH Low
5 VIN > VIH Low

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4. Explain Power dissapation analysis of CMOS inverter?

As I mentioned before, the CMOS inverter shows very low power dissipation when in
proper operation. In fact, the power dissipation is virtually zero when operating close to VOH and
VOL. The following graph shows the drain to source current (effectively the overall current of the
inverter) of the NMOS as a function of input voltage. dissipation).

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The CMOS inverter is an important circuit device that provides quick transition time, high buffer
margins, and low power dissipation: all three of these are desired qualities in inverters for most
circuit design. It is quite clear why this inverter has become as popular as it is.

• Therefore, the shape of the transfer characteristic and the V OL of the inverter is

affected by the ratio .

• In general, the low noise margin is considerably worse than the high noise margin
for Pseudo-nMOS.

Pseudo-nMOS was popular for high-speed circuits, static ROMs and PLAs.

5. Explain Pseudo-nMOS
• Example: Calculation of noise margins:

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• The
transfer curve for the pseudo-nMOS inverter can be used to calculate the noise
margins of identical pseudo-nMOS inverters

6. Write short notes on[APRIL-2009]

• Noise Margin, (ii) Rise Time, (iii) Fall Time.

(i) Noise Margins

(f) A parameter that determines the maximum noise voltage on the input of a gate
that allows the output to remain stable.

10. Two parameters, Low noise margin (NM L ) and High noise margin (NM H

16. NM L = difference in magnitude between the max LOW output voltage of

the driving gate and max LOW input voltage recognized by the driven gate.

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Noise Margins
• Ideal characteristic: V IH = V IL = (V OH +V OL )/2.

• This implies that the transfer characteristic should switch abruptly (high gain in the
transition region).

•V IL found by determining unity gain point from V OH .

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The time needed for Vout to fall from 0.9 VDD to 0.1 VDD is known as Fall time.


The time needed for Vout to rise from 0.1 VDD to 0.9 VDD is known as Rise time.

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Resistance estimation – Capacitance estimation – Inductance – Switching characteristics –

Transistor sizing – Power dissipation and design margining – Charge sharing – Scaling

1. What are two components of Power dissipation.[ Nov-2004]

There are two components that establish the amount of power dissipated in a
CMOS circuit. These are:
− Static dissipation due to leakage current or other current drawn
− continuously from the power supply.
− Dynamic dissipation due to Switching transient current Charging and discharging of
− load capacitances.

2. Give some of the important CAD tools. [APRIL-2009]

Some of the important CAD tools are:
(j) Layout editors
(k) Design Rule checkers (DRC)
(l) Circuit extraction

3. What are the dependent factors that the switching speed of MOS system depends on?
Parasitic capacitance
Interconnect capacitance of wires
Resistance of transistors and wires

4. What is the total capacitance of CMOS gate?

The total capacitance on the output of a CMOS gate is sum of gate capacitance diffusion or
depletion source, routing capacitance of substrate and other wires.

5. What is fall time?(May 2010)

fall time= time for a waveform to fall from 90% to 10% of its steady state value

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tr = 2CL/βpVDD(1-n)[(n-0.1)/(1-n)+1/2ln(19-20n)]

6. What is delay time?

Delay time is equal to the time difference between input transition (50%) and the 50%
output level. this is the time for a logic transition to pass from input to output.

7. What is static power dissipation?(May 2010)

The power dissipation due the leakage current through normally of transistor is called static
power dissipation.

8. What is dynamic power dissipation?

Power dissipation occurs when the MOS. Transistor switches to charge and discharge the
output load capacitance at a particular node at operating frequency.

9. What are the three sources of design margin?

Supply voltage , operating temperature, process variation.

10. Write down the yield expression to identify good chips?

Where A= chip area
D= defect density

11. What is charge sharing?

A parameter pertinent to analog switches as an analog switch turns ON and OFF , a small
amount of charge can be effectively coupled from the digital control line to the analog signal path.

12. What is the parasitic capacitance of MOS device?

Cgd=gate to drain capacitance
Cgs= Gate to source capacitance
Cgb= Gate to substrate capacitance
Csb= Source to substrate capacitance

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Cdb= Drain to substrate capacitance

13. What is rise time?

Rise time= time for a waveform to rise from 10% to 90% of its steady state value
tr = 2CL/βpVDD(1-p)[(p-0.1)/(1-p)+1/2ln(19-20n)]

1.Explain in detail about scaling

Gate area Ag = L W
' '
Ag  scaled =  L ×W
 ×
α α
 2g

Gate capacitance per unit area

Co= 
C o  scaled  =
D/ β
βC o

C g =C o × Ag
C g  scaled =C o  scaled ×A g  scaled 
Gate capacitance
A β
βC o× 2g =C g 2
α α

Charge in channel (when MOSFET is turned on)

Qon (charge/unit area) = Co  Vgs
Q on  scaled =βC o × gs =Q on

Channel resistance Ron

L 1
Ron = .
W σt
 is the conductivity
t is the channel thickness

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L 1 L 1
. = .
W σt W Q on μ
L /α 1
R on  scaled = .
W / α Q on μ
R on

Transistor delay
T d =R on×C g
T d  scaled  =Ron C g
 Td

Maximum operating frequency

f max ∝
f max  scaled = f
β max

Transistor current
C o μW 2
I ds =
2L  V gs −V t 
 βC o  μ  W /α  V gs V t
I ds  scaled  =
2  L/α   β

β 
I ds


Switching energy
E= C g V 2DD
1 β V 2DD
E  scaled = C
2 α2 g β2
 2 E
α β

2.Explain in detail about power dissipation

Power dissipation per gate
- static power
- dynamic (switching) power

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P s = DD
V 2DD 1 P s
P s  scaled = 2 . = 2
β R β

P sw =f × C g V 2DD
α2 1 β V 2DD
dynamic P sw  scaled = f × 2 Cg 2
β 2α β
 2 P sw

Power dissipation per unit area

P / β2
scales to
Ag /α 2
scaling factor is
1 β 1
Power-delay product scales by 2 . 2 = 2
β α α β

2.explain the Scaling Factors

In our discussions we will consider 2 scaling factors, α and β

1/ β is the scaling factor for VDD and oxide thickness D

1/ α is scaling factor for all other linear dimensions
We will assume electric field is kept constant
Scaling Factors for Device Parameters
It is important that you understand how the following parameters are effected by scaling

Gate Area
Gate Capacitance per unit area
Gate Capacitance
Charge in Channel
Channel Resistance
Transistor Delay
Maximum Operating Frequency
Transistor Current
Switching Energy

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Power Dissipation Per Gate (Static and Dynamic)

Power Dissipation Per Unit Area
Power - Speed Product

3.Explain resistance estimation?

Resistance of a square slab of material

RAB = ρL/A

=> R = ρL/t*W
Let L = W (square slab)
=> RAB = ρ/t = Rs ohm / square

Layer Rs (Ohm / Sq
Aluminium 0.03
N Diffusion 10 – 50
Silicide 2–4
Polysilicon 15 - 100
N-transistor Channel 104
P-transistor Channel 2.5 x 104

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12. The Charge Sharing Model

• The reduction of the threshold voltage with a reduction in the channel length can be
explained by the charge sharing model.

Fig The depletion charge profiles for (a) a long channel device, and (b) a short channel device.
• For a long channel device, the depletion layer thickness at the source end of the channel and
at the drain end of the channel are much less than the channel length L, and, thus, the
depletion charge enclosed by these sections are much smaller than the total depletion charge
under the gate.
• However, for a short channel device, the widths of these depletion regions are a non-
negligible fraction of the total depletion charge under the gate.
• Note: essentially, the depletion regions near the source and the drain are contributed by the
source-substrate and the drain-substrate bias, and gate has no role to play.
• Under an applied drain-source bias, the depletion region thickness near the drain will
obviously be larger than that at the source side.
• The net effect is that the gate now has to compensate for a lower depletion charge density
than that for a long channel device, which qualitatively explains the reduction of the
threshold voltage with a reduction in the channel length.
• The exact analysis of the charge sharing effects requires a two-dimensional analysis,
however, to the first order, it is assumed that the effect of the depletion width at the drain
side of the channel is to reduce the effective channel length in the saturation region from L
to where

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Multiplexers – Decoders – Comparators – Priority Encoders – Shift Registers – Arithmetic Circuits–
Ripple Carry Adders – Carry Look Ahead Adders – High-Speed Adders –Multipliers – Physical
design – Delay modeling – Cross Talk – Floor planning – Power distribution – Clock distribution –
Basics of CMOS testing

1.What are the categories of testing?

a) Functionality tests
b) Manufacturing tests

2. Write notes on functionality tests?

Functionality tests verify that the chip performs its intended function. These tests assert that
all the gates in the chip, acting in concert, achieve a desired function. These tests are usually used
early in the design cycle to verify the functionality of the circuit.

3. Write notes on manufacturing tests?

Manufacturing tests verify that every gate and register in the chip functions correctly. These
tests are used after the chip is manufactured to verify that the silicon is intact.

4. Mention the defects that occur in a chip?

• layer-to-layer shorts
• discontinous wires
• thin-oxide shorts to substrate or well

5. Give some circuit maladies to overcome the defects?

i. nodes shorted to power or ground

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ii. nodes shorted to each other

iii. inputs floating/outputs disconnected

6. What are the tests for I/O integrity?

i. I/O level test
ii. Speed test
iii. IDD test

7 .What is meant by fault models?

Fault model is a model for how faults occur and their impact on circuits.

8. Give some examples of fault models?

i. Stuck-At Faults
ii. Short-Circuit and Open-Circuit Faults

9. What is stuck – at fault?

With this model, a faulty gate input is modeled as a “stuck at zero” or “stuck at one”. These
faults most frequently occur due to thin-oxide shorts or metal-to-metal shorts.

10. What is meant by observability?

The observability of a particular internal circuit node is the degree to which one can observe
that node at the outputs of an integrated circuit.

11. What is meant by controllability?

The controllability of an internal circuit node within a chip is a measure of the ease of
setting the node to a 1 or 0 state.

12. What is known as percentage-fault coverage?

The total number of nodes that, when set to 1 or 0, do result in the detection of the fault,
divided by the total number of nodes in the circuit, is called the percentage-fault coverage.

13. What is fault grading?

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Fault grading consists of two steps. First, the node to be faulted is selected. A simulation is
run with no faults inserted, and the results of this simulation are saved. Each node or line to be
faulted is set to 0 and then 1 and the test vector set is applied. If and when a discrepancy is detected
between the faulted circuit response and the good circuit response, the fault is said to be detected
and the Simulation is stopped.

14. Mention the ideas to increase the speed of fault simulation?

a. parallel simulation
b. concurrent simulation

15. What is fault sampling?

An approach to fault analysis is known as fault sampling. This is used inc ircuits where it is
impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting
fault detection rate may be statistically inferred from the number of faults that are detected in the
fault set and the size of the set. The randomly selected faults are unbiased. It will determine whether
the fault coverage exceeds a desired level.

16. What are the approaches in design for testability?

a. ad hoc testing
b. scan-based approaches
c. self-test and built-in testing
d. partitioning large sequential circuits
e. adding test points
f. adding multiplexers
g. providing for easy state reset

17. What are the scan-based test techniques?

a) Level sensitive scan design
b) Serial scan
c) Partial serial scan
d) Parallel scan

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18. What are the self-test techniques?

a. Signature analysis and BILBO
b. Memory self-test
c. Iterative logic array testing

19. What is known as BILBO?

Signature analysis can be merged with the scan technique to create a structure known as
BILBO- for Built In Logic Block Observation.

20. What are the applications of chip level test techniques?

a. Regular logic arrays
b. Memories c. Random logic

21. What is boundary scan?

The increasing complexity of boards and the movement to technologies like multichip modules and
surface-mount technologies resulted in system designers agreeing on a unified scan-based
methodology for testing chips at the board. This is called boundary scan.

22. What is the test access port?

The Test Access Port (TAP) is a definition of the interface that needs to be included in an IC
to make it capable of being included in a boundary-scan architecture. The port has four or five
single bit connections, as follows:
TCK(The Test Clock Input)
TMS(The Test Mode Select)
TDI(The Test Data Input)
TDO(The Test Data Output)
It also has an optional signal
TRST*(The Test Reset Signal)

23. What is the TAP controller?

The TAP controller is a 16-state FSM that proceeds from state to state based on the TCK and

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TMS signals. It provides signals that control the test data registers, and the instruction register.
These include serial-shift clocks and update clocks.

24.Define Decoder?
A decoder is a multiple - input multiple output logic circuit that converts coded inputs into
coded outputs where the input and output codes are different.

25.What is priority Encoder?

A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if 2 or more inputs are equal to 1 at the same time, the input having the highest priority
will take precedence.

26.What do you mean by comparator

A comparator is a special combinational circuit designed primarily to compare the relative
magnitude of two binary numbers.

27.Define multiplexer?
Multiplexer is a digital switch. If allows digital information from several sources to be
routed onto a single output line.

28.Define power dissipation?

Power dissipation is measure of power consumed by the gate when fully driven by all its

29. What is propagation delay?

Propagation delay is the average transition delay time for the signal to propagate from
input to output when the signals change in value. It is expressed in ns.

30.Define cross talk.

Whenever in terconnect line is placed close proximity to any other interconnect line,the
conductors are coupled by a parasitic capacitance,pulsing a voltage on one of the lines induces a
stray signal on all lines that are coupled to it. This is known as cross talk.

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31. what is local-skew, global-skew,useful-skew mean?

Local skew : The difference between the clock reaching at the launching flop vs the clock reaching
the destination flip-flop of a timing-path.
Global skew : The difference between the earliest reaching flip-flop and latest reaching
flip-flop for a same clock-domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach
helps in meeting setup requirement with in the launch and capture timing path.

1.Explain the algorithms of automatic test pattern generation.
The objective is to automatically generate a test for faults in the circuit-under-test
Major classes of methods:
FAN and related algorithms

Pseudorandom Test Generation

Simply generate an input vector using a pseudorandom number generator and

perform fault simulation to determine if it detects the target fault. The characteristics of the
fault greatly influence how well pseudorandom test generation will work Easy-to-detect
faults, Hard-to-detect faults. Typically used in the beginning of the test generation process to
remove easy-to-detect faults from the fault list.
Uses functional test vectors developed by designers for functional verification and design
debugging by:
Fault simulating to determine fault coverage
Determining locations of undetected faults

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Adding additional functional tests to exercise areas of design with undetected faults
Re-fault simulating and repeating until desired fault coverage is achieved.
No special test generation system is required, only fault simulator.Utilizes existing vectors
and designer expertise.Achieving high fault coverage may be difficult and time consuming -
especially for synthesized designs
D Algorithm
First algorithm proved “complete” - developed by Roth at IBM in 1966
Complete - can be proven that the algorithm will generate a test for a fault if it
exists.Introduced D notation D - “1” in the good circuit “0” in the faulty, D’ - “0” in
the good circuit “1” in the faulty (Dbar)
PDCF - Primitive D cube of failure - a set of inputs to a module that will sensitize a specific
fault within the module. PDC - Propagation D cube - a set of inputs to a module that will
propagate a D from the inputs to the outputs.

Path Oriented DEcision Making - developed in 1981 by Goel to address the problem D
algorithm had with XOR gates. D algorithm is exponentially complex to the number of
internal circuit nodes - XOR gates make the complexity of the D algorithm approach this
limit PODEM expresses the search space in terms of assignments to the primary inputs only.
PODEM is also a branch-and-bound algorithm which is exponentially complex to the
number for circuit inputs - usually a much smaller number than circuit nodes.

2. Explain in detail Boundary-Scan testing.

It Consists of adding scan registers to the inputs and outputs of ICs. It Allows for efficient
testing at the board level Testing of board-level interconnect,Isolation and testing of chips
via chip-level BIST or the application of chip-level tests via the test bus. It Requires the
addition four I/O ports to the chip - Test Access Port (TAP)
TCK - test clock
TMS - test mode signal
TDI - serial test data in
TDO - serial test data out
ItAlso requires the addition of logic to control the testing process - TAP Controller
Boundary-Scan Cell

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This figure show the basic structure of a boundary-scan cell. One of these cells is
added to each I/O port on the chip. One reason that boundary scan may be popular is that the
relative cost of adding the scan cells to the I/O pads is low compared to the cost of adding
full scan. For example, only a mux is added to the normal I/O path, which does add some
delay, but it’s in the context of the already large I/O pad delay. Second, there is some
additional logic that has to be added to the Pad buffer, but most of the pad area is dominated
by the size of the physical pad, and the additional logic doesn’t increase it by much.

Boundary-Scan Cell Modes

Normal Mode: Mode_Control = ‘0’
Data passes from IN to OUT
Scan Mode: ShiftDR = ‘1’, ClockDR = scan clock
Serial data is shifted in from SIN and out to SOUT
Capture Mode: ShiftDR = ‘0’, ClockDR = 1 clock pulse
Data on the IN line is clocked into QA
Update Mode: with QA loaded, Mode_Control = ‘1’, UpdateDR = 1 clock pulse
Data clock into QA is applied to OUT
There are four major modes for the boundary-scan cell. The normal mode simply passes inputs to
outputs. The scan mode passes data from SIN to Qa and from Qa to Sout. Capture mode loads the
value on the input to Qa. Finally, update mode loads values from Qa to the output.To shift in and
apply data, the scan mode would be selected until the data is shifted in and then one cycle of update
mode would be selected. To capture data and scan it out, one cycle of capture mode would be
selected followed by the required number of scan cycles.

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Boundary-Scan Chip Architecture

This figure shows the architecture of a boundary-scan-complaint chip. Note that the application
logic of the chip itself may include DFT or BIST techniques (scan, BILBO, etc.) and this test logic
is controlled by the boundary-scan TAP controller.
Boundary-Scan Advantages/Disadvantages
Boundary-scan has a lower overhead than scan design because, in terms of speed, the increase in
normal on/off chip time is much less a percentage increase than is true for scan design. Also, in
terms of area, the additional logic is small compared to an I/O pad.
Another major advantage to using boundary scan is that it can also be used to scan in/out functional
vectors and responses. This can be useful in a number of design verification tasks.
Boundary-scan does have non-zero area, speed, and testing overheads, and that needs to be
considered when adding it.

3. Explain in detail Built-In Self Test.

Thus far, Design for Testability techniques have been discussed. Generic DFT can be
considered a passive technique where logic is added to make a design easier for an external tester to
Built-In Self Test is an active technique where the device is designed to test itself (with a little help).
The capability of a chip, board, or system to test itself .The goal of Built-In Self Test is to add
devices to a design that will allow it to test itself.
Built-In-Test Equipment (BITE)
The hardware/software incorporated into a unit to provide DFT or BIST
On-Line BIST
BIST in which testing occurs during normal operation
Concurrent On-Line BIST

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A form of on-line BIST in which testing occurs simultaneously with normal function
Nonconcurrent On-Line BIST
A form of on-line BIST where testing is carried out while the system is in an idle state
Off-Line BIST
BIST in which testing occurs when the system is not in its normal operation
Functional Off-Line BIST
Off-line BIST that uses tests based on the functional description of the circuit-under-test
Structural Off-Line BIST
Off-line BIST that uses tests based on the structure of the circuit-under-test
Pseudo Random Pattern Generator (PRPG)
a multi-output device that generates pseudorandom output patterns - usually implemented with a
Linear Feedback Shift Register (LFSR)
Multiple-Input Signature Register (MISR)
a multi-input device that compresses a series of input patterns into a (pseudo) unique signature
Test-Pattern Generation for BIST
There are several ways that test patterns for BIST can be generated. Remember that the device itself
is generating the test patterns, so they have to be generated or stored (rarely used) in hardware on
Exhaustive Testing –
apply all 2n input patterns to a combinational circuit with n inputs,Binary counter can be
used as a TPG
Pseudorandom testing –
It generate patterns that appear to be random but are in fact deterministic (repeatable)
LFSR used as a TPG
Weighted Pseudorandom Test Generation
LFSR used as TPG with combinational circuit to modify the probability of a "1" or "0" so they
are nonuniform
Adaptive Pseudorandom Test Generation –
weighted random testing with the weights being modified using output of fault simulation -
more than one weight used
Pseudoexhaustive Testing - segment device and test each portion exhaustively
Pseudorandom Test Generation LFSRs

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Pseudorandom (likelihood of "1" or "0" is 50%, but patterns are deterministic/repeatable) patterns
may be generated by a linear feedback shift register (LFSR).
LFSRs are constructed from:
- unit delays or D flip-flops
- modulo-2 adders
- modulo-2 scalar multipliers
The devices are linear because they preserve the principle of superposition; i.e., its response to a
linear combination of inputs is the linear combination of the responses of the circuit to the
individual stimuli.

Maximal Length LFSR

The all zeros case is not possible in this type of LFSR, but notice that the probability of any bit
being "1" or "0" is 50% except for that. Therefore, the sequence is pseudorandom in the sense that
the probability of a "1" or "0" is approx. 50%, but the sequence is repeatable. Like a binary counter,
all 2n - 1 states are generated, but in a “random” order that is repeatable.

Signature Analysis
Once the test patterns are automatically applied, the responses must be gathered. The only way to
do this practically for true BIST is to compress the responses into a single (we hope) unique value.
Signature analysis attempts to perform this function.
Signature analysis uses an LFSR to compress the input stream to a single value. The basic

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principal is that the input polynomial (stream) gets divided by the characteristic polynomial of the
LFSR, resulting in a quotient (output stream) and a remainder. Because this is basically a “lossy”
compression scheme, there is more than one input stream that can generate a specific signature. The
occurrence of an erroneous input stream that generates a correct signature is called aliasing. The
probability of aliasing as show here is very small, but it is also circuit dependent; i.e., the types of
errors generated by faults in the circuit may make aliasing more probable.
4. Explain the design of CMOS Adder Circuit.
For 1-Bit Full Adder logic function sum and carry equations are given by
Sum = A XOR B XOR C = ABC + AB’C’ + A’BC’ + A’B’C
Carry_out = AB + AC + BC
Sum function can be written as Sum = ABC + (A + B + C) · Carry_out’.
The alternate representation of the sum function allows the 1-bit full adder to
beimplemented in complex CMOS with 28 transistors, is shown in figure.


Complementary Pass Transistor Logic (CPL)

− Slightly faster, but more area

Carry Propagate Adders

N-bit adder called CPA. Each sum bit depends on all previous carries

AN...1 BN...1 Cout Cin Cout Cin

00000 11111 carries
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1111 1111 A4...1
SN...1 +0000 +0000 B4...1
1111 0000 S4...1

Carry-Ripple Adder
Simplest design: cascade full adders
o Critical path goes from Cin to Cout
o Design full adder to have fast carry delay

A4 B4 A3 B3 A2 B2 A1 B1

Cout Cin
C3 C2 C1
S4 S3 S2 S1

Generate / Propagate
Equations often factored into G and P
Generate and propagate for groups spanning i:j

Gi:j =
Gi:k+Pi:k Gk 1g
:j −

Pi:j =
Pi:k Pkg1:j −

Base case

Gii: G
 =
i Ai Bi g
Pii: P
i A
i =

Sum: Si = Pi G
− 1:0i

PG Logic
A4 B4 A3 B3 A2 B2 A1 B1 Cin

1: Bitwise PG logic
G4 P4 G3 P3 G2 P2 G1 P1 G0 P0

2: Group PG logic

G3:0 G2:0 G1:0 G0:0

C3 C2 C1 C0
3: Sum logic


Cout S4 S3 S2 S1

Carry-Ripple Revisited A4 B4 A3 B3 A2 B2 A1 B1 Cin

G4 P4 G3 P3 G2 P2 G1 P1 G0 P0

iPi Gi 1
:0 g −

G3:0 G2:0 G1:0 G0:0

C3 C2 C1 C0

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S4 S3 S2 S1

Carry-Skip Adder
Carry-ripple is slow through all N stages
Carry-skip allows carry to skip over groups of n bits
o Decision based on n-bit propagate signal

A16:13 B16:13 A12:9 B12:9 A8:5 B8:5 A4:1 B4:1

P16:13 P12:9 P8:5 P4:1

1 C12 1 C8 1 C4 1
Cout Cin
0 + 0 + 0 + 0 +

S16:13 S12:9 S8:5 S4:1

Carry-Lookahead Adder
Carry-lookahead adder computes Gi:0 for many bits in parallel.
Uses higher-valency cells with more than two inputs.

A16:13 B16:13 A12:9 B12:9 A8:5 B8:5 A4:1 B4:1

Cout G16:13 C12 G12:9 C8 G8:5 C4 G4:1

P16:13 P12:9 P8:5 P4:1

+ + + + Cin

S16:13 S12:9 S8:5 S4:1

Carry-Select Adder
Trick for critical paths dependent on late input X
4. Precompute two possible outputs for X = 0, 1
5. Select proper output when X arrives
Carry-select adder precomputes n-bit sums
6. For both possible carries into n-bit group

A16:13 B16:13 A12:9 B12:9 A8:5 B8:5 A4:1 B4:1

0 0 0
+ + +

Cout C12 C8 C4
1 1 1 Cin
+ + + +


S16:13 S12:9 S8:5 S4:1

5. Explain the design of CMOS MUX Circuit.

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2:1 multiplexer chooses between two inputs

D0 0
D1 1

• Gate-Level
Y = SD1 + Mux Design
SD0 (too many transistors) 
20 transistors are needed 20


D1 4 2
S 4 2 Y
D0 4 2

Transmission Gate Mux

Nonrestoring mux uses two transmission gates
7. Only 4 transistors
Inverting Mux
Inverting multiplexer
• Use compound AOI22
• Or pair of tristate inverters
• Essentially the same thing
Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
D1 1

4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
(1) Two levels of 2:1 muxes
S1S0 S1S0 S1S0 S1S0

(2) Or four tristates

S0 S1

D0 0
D1 1
D2 0 D2
D3 1

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6.Explain floor planning in detail.

Difference Between Floorplanning and Placement
In floorplanning, some of the blocks may be flexible, and the exact locations of the pins not yet
In placement, all blocks are assumed to be of well-defined geometrical shapes, with defined pin

ocations .
Design Style Specific Issues
• Full Custom
– All the steps required for general cells.
• Standard Cell
– Dimensions of all cells are fixed.
– Floorplanning problem is simply the placement problem.
– For large netlists, two steps:
• First do global partitioning.
• Placement for individual regions next.
• Gate Arra
– Floorplanning problem same as placement problem
Estimating Cost of a Floorplan
• The number of feasible solutions of a floorplanning problem is very large.
– Finding the best solution is NP-hard.
• Several criteria used to measure the quality of
a) Minimize area
b) Minimize total length of wire
c) Maximize routability
d) Minimize delays
e) Any combination of above
How to determine wire length?
– A coarse measure is used.

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– Based on a model where all I/O pins of the blocks are merged and assumed to reside at its
– Overall wiring length L = Σi,j (cij * dij)
where cij : connectivity between blocks i and j
dij : Manhattan distances between the centres of rectangles of blocks i and j
Typical cost function used:
Cost = w1 * A + w2 * L
where w1 and w2 are user-specified parameters
Slicing Structure
– A rectangular dissection that can be obtained by repeatedly splitting rectangles by
horizontal and vertical lines into smaller rectangles.
• Slicing Tree
– A binary tree that models a slicing structure.
– Each node represents a vertical cut line (V), or a horizontal cut line (H).
• A third kind of node called Wheel (W) appears for nonsliceable floorplans
– Each leaf is a basic block (rectangle).
Floorplanning Algorithms
– Integer programming based
– Rectangular dual graph based
– Hierarchical tree based
– Simulated annealing based
Integer Linear Programming Formulation
• The problem is modeled as a set of linear equationsusing 0/1 integer variables.
• Given:
– Set of n blocks S = {B1, B2, …,Bn} which are rigid and have fixed orientation.
– 4-tuple associated with each block (xi, yi, wi, hi)
Rectangular Dual-Graph Approach
• Basic Concept:
– Output of partitioning algorithms represented by a graph.
– Floorplans can be obtained by converting the graph into its rectangular dual.
• The rectangular dual of a graph satisfies the following properties:
– Each vertex corresponds to a distinct rectangle.

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– For every edge, the corresponding rectangles are adjacen.

Without loss of generality, we assume that a rectangular floorplan contains no cross junctions.
• Under this assumption, the dual graph of a rectangular floorplan is a planar triangulated graph
Every dual graph of a rectangular floorplan (without cross junction) is a PTG.
However, not every PTG corresponds to a rectangular floorplan.
• A new approach to floorplanning, in which many sub-problems are still unsolved.
• The main problem concerns the existence of the rectangular dual, i.e. the elimination of complex
– Select a minimum set E of edges such that each complex triangle has at least one edge in E.
– A vertex can be added to each edge of E to eliminate all complex triangles.
– The weighted complex triangle elimination problem has been shown to be NP-complete.
• Some heuristics are available.
Hierarchical Approach
• Widely used approach to floorplanning.
– Based on a divide-and-conquer paradigm.
– At each level of the hierarchy, only a small number of rectangles are considered.

7.Explain Multiplier in detail.

1100 : 12 10
0101 : 5 10 multiplier
0000 partial
1100 products
00111100 : 60 10 product

M x N-bit multiplication
o Produce N M-bit partial products
o Sum these to produce M+N-bit product

Multiplicand: Y = (yM-1, yM-2, …, y1, y0)

Multiplier: X = (xN-1, xN-2, …, x1, x0)

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Product: �M −1
� N− 1
j � i�
−N 1−M 1
P =�� y j 2� �
� x i 2=�� � x iy j 2i j +

�j =0 ��=
i 0 �=i 0= j 0

y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product

Dot Diagram


partial products
multiplier x


Array Multiplier
y3 y2 y1 y0






p7 p6 p5 p4 p3 p2 p1 p0

Sin A Cin critical path A B
B Sin
= Cout Cin = Cout Cin
Cout Cin
Cout Sout Sout

Fewer Partial Products

Array multiplier requires N partial products
If we looked at groups of r bits, we could form N/r partial products.
o Faster and smaller?

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o Called radix-2r encoding

Ex: r = 2: look at pairs of bits
o Form partial products of 0, Y, 2Y, 3Y
First three are easy, but 3Y requires adder

Booth Encoding
Instead of 3Y, try –Y, then increment next partial product to add 4Y
Similarly, for 2Y, try –2Y + 4Y in next partial product

Booth Hardware
Booth encoder generates control lines for each PP
o Booth selectors choose PP bits
yj yj­1

Xi x2i­1

2X i

PP ij

8. Explain power distribution in cmos circuits in detail.

Importance of Low-power Designs
Cost factor for high-end systems
High-end systems
Cooling and package cost
> 40 W: 1 W à $1
Air-cooled techniques: reaching limits
Electricity bill

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Desktop PCs consume around 10% power in US

Usability of Portable systems:
Battery lifetime
Restriction factor for high-performance server design
Power determines processor density
Dynamic vs. Static Power

Charge/discharge capacitors when switching between 0 and 1
Short-circuit currents on transitions
Static (Leakage)
o From sub-threshold currents

Sources of Power Consumption

Dynamic (dominant)
P dync = C⋅V 2⋅A⋅ f

Static (2~5%)
P static =N⋅V⋅k design⋅I leak

Importance of Low-power Architecture Designs

Low power CMOS and logic designs alone can no longer solve all power problems

P dync = C⋅V 2⋅A⋅ f
 V ' =0 . 7V

 '
C ' =0 .7×2C ⇒ P dync=1 . 4P dync
f ' =2f

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Introduction to FPGA – Xilinx FPGA – Xilinx 2000 – Xilinx 3000 – Overview of Digital
Design with Verilog HDL – Hierarchical modeling concepts – Modules and Port definitions –
Gate level modeling – Data flow modeling – Behavioral modeling



1.What is Verilog? [Nov-2004]

Verilog is a general purpose hardware descriptor language. It is similar in syntax
to the C programming language. It can be used to model a digital system at many
levels of abstraction ranging from the algorithmic level to the switch level.

2. What are the various modeling used in Verilog? [APRIL-2009]

• Gate-level modeling
• Data-flow modeling
8. Switch-level modeling
9. Behavioral modeling

3. What is the structural gate-level modeling?[ Nov-2004]

Structural modeling describes a digital logic networks in terms of the components
that make up the system. Gate-level modeling is based on using primitive logic
gates and specifying how they are wired together
4.What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of MOSFETs.
Digital circuits at the MOS-transistor level are described using the MOSFET
4. What are identifiers? [APRIL-2009]
Identifiers are names of modules, variables and other objects that we can

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reference in the design. Identifiers consists of upper and lower case letters, digits
0 through 9, the underscore character(_) and the dollar sign($). It must be a single
group of characters. Examples: A014, a ,b, in_o, s_out

5. What are the value sets in Verilog?[ Nov-2004]

Verilog supports four levels for the values needed to describe hardware referred to
as value sets.
Value levels Condition in hardware circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state

6.What are the types of gate arrays in ASIC?

17. Channeled gate arrays
18. Channel less gate arrays
19. Structured gate arrays

7. Give the different arithmetic operators?

Operator symbol Operation performed Number of operands
* Multiply Two
/ Divide Two
+ Add Two
- Subtract Two
% Modulus Two
** Power (exponent) Two

8. Give the different bitwise operators. [APRIL-2009]

Operator symbol Operation performed Number of operands
~ Bitwise negation One
& Bitwise and Two
| Bitwise or Two

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^ Bitwise xor Two

^~ or ~^ Bitwise xnor Two
~& Bitwise nand Two
~| Bitwise nor Two

9. What are gate primitives?

Verilog supports basic logic gates as predefined primitives. Primitive logic
function keyword provide the basics for structural modeling at gate level. These
primitives are instantiated like modules except that they are predefined in verilog
and do not need a module definition. The important operations are and, nand, or,
xor, xnor, and buf(non-inverting drive buffer).

10. Give the two blocks in behavioral modeling.

1. An initial block executes once in the simulation and is used to set up
initial conditions and step-by-step data flow
• An always block executes in a loop and repeats during the simulation.

11. Name the types of ports in Verilog[APRIL-2009]

Types of port Keyword
Input port Input
Output port Output
Bidirectional port inout

12. What are the types of procedural assignments? [APRIL-2009]

o Blocking assignment
o Non-blocking assignment

13.What is meant by FPGA?

A field programmable gate array (FPGA) is a programmable logic device that supports
implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit
with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000
equivalent gates. FPGAs are quite different from CPLDs because FPGAs do not contain AND or
OR planes. Instead, they provide logic blocks for implementation of the required functions.

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• Give the general structure of FPGA

11. What are the types of reprogrammable GA?

Ad-hoc Array and Structured Array are the two types of Reprogrammable Gate Array.

12. What is the type’s o FPLA?

− PROM [Programmed Read-Only Memory]
− PAL [Programmed Array Logic]

13. What are the applications of PAL?

(m)Control logic application
(n) Input/Output
(o) Data-path logic

16. What are the characteristics of PLA/FSM?

(h) Regularity
(i) Modularity
(j) Suitability
(k) Efficiency

17. What is CLB?

CLB means Configurable Logic Block.

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18. Define mealy machine?

In mealy machine, output may change with the change in the input asynchronously.

19. Define moore machine?

In moore machine, output can be changed when state is changed.


1.What are the types of conditional statements? [APRIL-2009]

1. No else statement
Syntax : if ( [expression] ) true – statement;
2. One else statement
Syntax : if ( [expression] ) true – statement;
else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is
executed. If it is false (zero) or ambiguous (x), the false-statement is executed.

2. Give the classifications of timing control? [APRIL-2009]

Methods of timing control:
o Delay-based timing control
o Event-based timing control
o Level-sensitive timing control

Types of delay-based timing control:

1. Regular delay control
2. Intra-assignment delay control
3. Zero delay control
Types of event-based timing control:
1. Regular event control
2. Named event control
3. Event OR control

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• Level-sensitive timing control

3. Explain the concept of gate delay in VERILOG with example [APRIL-2009]

Gate-Level Modelling
Primitive logic gates are part of the Verilog language. Two properties can be specified,
drive_strength and delay. Drive_strength specifies the strength at the gate outputs. The strongest
output is a direct connection to a source, next comes a connection through a conducting transistor,
then a resistive pull-up/down. The drive strength is usually not specified, in which case the
strengths defaults to strong1 and strong0. Refer to Cadence Verilog-XL Reference Man-ual for
more details on strengths.
Delays: If no delay is specified, then the gate has no propagation delay; if two delays are specified,
the first represent the rise delay, the second the fall delay; if only one delay is specified, then rise
and fall are equal. Delays are ignored in synthesis. This method of specifying delay is a special case
of “Parameterized Modules” on page 11. The parame-ters for the primitive gates have been
predefined as delays.

Basic Gates
These implement the basic logic gates. They have one output and one or more inputs. In the gate
instantiation syntax shown below, GATE stands for one of the keywords and, nand, or, nor, xor,

Syntax Example
GATE (drive_strength) # (delays) and c1 (o, a, b, c, d); // 4-
instance_name1(output, input_1, input AND called c1
input_2,..., input_N), and c2 (p, f g); // a 2-
instance_name2(outp,in1, in2,..., inN); input AND called c2.
Delays is or #(4, 3) ig (o, a, b); /* or gate
#(rise, fall) or called ig
# rise_and_fall or (instance name);
#(rise_and_fall) rise time = 4, fall
time = 3 */
xor #(5) xor1 (a, b, c); // a = b
XOR c after 5 time units
xor (pull1, strong0) #5
(a,b,c); /* Identical gate
with pull-up strength pull1
and pull-down strength
strong0. */

buf, not Gates

These implement buffers and inverters, respectively. They have one input and one or more outputs.
In the gate instan-tiation syntax shown below, GATE stands for either the keyword buf or not


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not #(5) not_1 (a,

GATE (drive_strength) # (delays) c); // a = NOT c after 5 time units
buf c1 (o, p, q, r, in); // 5-output and 2-output
c2 (p, f g);
..., output_n,

instance_name2(out1, ..., outN,

out2, in);

4 .Explain Verilog Syntax Details

Structural Data Types: wire and reg

Verilog supports structural data types called nets which model hardware connections between
circuit components. The two most common structural data types are wire and reg. The wire nets act
like real wires in circuits. The reg type hold their values until another value is put on them, just like
a register hardware component. The declarations for wire and reg signals are inside a module but
outside any initial or always block. The initial state of a reg is x unknown, and the initial state of a
wire is z.

Ports:Modules communicate with each other through ports, the signals listed in the parameter list at
the top of the module. Ports can be of type in, out, and inout.

Here are 3 simplistic rules for matching the structural data type to the type of port:

13. Use reg as the outputs of Behavioral blocks. If you us a wire then the value will never be
seen by other blocks.
14. Use wire for all inputs, inouts, and most outputs of Structural elements.
15. If you need a special strength type operation use special net keyword wand, wor, tir, triand,
trior, trireg.

Behavioral Data Types: integer, real, and time

The types in integer and real are convenient data types to use for counting in behavioral code
blocks. These data types act like their counter parts in other programming languages. If you

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eventually plan to synthesize your behavioral code then you would probably want to avoid using
these data types because they often synthesize large circuits.

The data type time can hold a special simulator value called simulation time which is extracted
from the system function $time. The time information can be used to help you debug your

..... //code fragment from inside a module

integer i, y;
real a;
real b = 3.5;
real c = 4;
time simulationTime;
y = 4;
i = 5 + y;
c = c + 3.5;
a = 5.3e4;
simulationTime = $time;
$display("integer y = %d, i = %f \n", y, i);
$display("reals c = %f, a = %e, b= %g \n", c, a, b);
$display("time simulationTime = %t \n", simulationTime);

Number Syntax

Numbers in verilog are in the following format


The size is always specified as a decimal number. If no is specified then the default size is at least
32bits and may be larger depending on the machine. Valid base formats are 'b , 'B , 'h , 'H 'd , 'D ,
'o , 'O for binary, hexadecimal, decimal, and octal. Numbers consist of strings of digits (0-9, A-F, a-
f, x, X, z, Z). The X's mean unknown, and the Z's mean high impedance If no base format is
specified the number is assumed to be a decimal number. Some examples of valid numbers are:

2'b10 // 2 bit binary number

'b10 // at least a 32-bit binary number
3 // at least a 32-bit decimal number
8'hAf // 8-bit hexadecimal
-16'd47 // negative decimal number

Behavioral Design with blocking and non-blocking statements

There are 2 kinds of assignment statements: blocking using the = operator, and non-blocking using

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the <= operator. Blocking assignments act like sequential code statements and execute when they
are called. Non-blocking schedule events to happen at some time in the future. This can be
confusing because lines that appear after a non-blocking statement execute at the same time as the
non-blocking statement. Here are some examples:

#5 x = 1'b0; // blocks for 5 time units, applies value to x, then next line
y = 1'b1; // blocks, sets y to 1 now, then next statement goes
y <= #3 1'b0; // evaluates now, schedules apply y=0 in 3 time units, and next
line goes
#5 x <= y; // waits for 5 time units, evaluates,
// schedules apply at end of current time, and next line goes

The following two code blocks are not equivalent:

// Section 1: Blocking statements execute sequentially

#5 a = b; // waits 5 time units, evaluates and applies value to a
c = d; // evaluates and applies value to c

// Section 2: Non-Blocking statements execute concurrently

#5 a <= b; // waits 5 time units, evaluates, schedules apply for end of current
c <= d; // evaluate, schedules apply for end of current time
// At end of current time both a and c receive their values

Arrays, Vectors, and Memories

Verilog supports three similar data structures called Arrays, Vectors, and Memories. Arrays are used
to hold several objects of the same type. Vectors are used to represent multi-bit busses. And
Memories are arrays of vectors which are accessed similar to hardware memories. Read the
following examples to determine how to reference and use the different data structures.

//*** Arrays for integer, time, reg, and vectors of reg ***************
integer i[3:0]; //integer array with a length of 4
time x[20:1]; //time array with length of 19
reg r[7:0]; //scalar reg array with length of 8

c = r[3]; //the 3rd reg value in array r is assigned to c

//*** Vectors are multi-bit words of type reg or net (wire)************

reg [7:0] MultiBitWord1; // 8-bit reg vector with MSB=7 LSB=0
wire [0:7] MultiBitWord2; // 8-bit wire vector with MSB=0 LSB=7
reg [3:0] bitslice;
reg a; // single bit vector often referred to as a scalar
.... //referencing vectors
a = MultiBitWord1[3]; //applies the 3rd bit of MultiBitWord1 to a
bitslice = MultiBitWord1[3:0]; //applies the 3-0 bits of MultiBitWord1 to

//*** Memories are arrays of vector reg ********************************

reg [7:0] ram[0:4095]; // 4096 memory cells that are 8 bits wide

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//code excerpt from Chapter 2 SRAM model

input [11:0] ABUS; // 12-bit address bus to access all 4096 memory cells
inout [7:0] DATABUS; // 8-bit data bus to wite into and out of a memory cell
reg [7:0] DATABUS_driver;
wire [7:0] DATABUS = DATABUS_driver; //inout must be driven by a wire
for (i=0; i < 4095; i = i + 1) // Setting individual memory cells to 0
ram[i] = 0;
ram[ABUS] = DATABUS; //writing to a memory cell
DATABUS_driver = ram[ABUS]; //reading from a memory cell

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5. list out the symbols of Operators

Here is a small selection of the Verilog Operators which look similar but have different effects.
Logical Operators evaluate to TRUE or FALSE. Bitwise operators act on each bit of the operands to
produce a multi-bit result. Unary Reduction operators perform the operation on all bits of the
operand to produce a single bit result.

Operator Name Examples

! logical negation
~ bitwise negation
&& logical and
abus =
& bitwise and
& reduction and abit = &bbus;
~& reduction nand
|| logical or
| bitwise or
| reduction or
~| reduction nor
^ bitwise xor
^ reduction xor
~^ ^~ bitwise xnor
~^ ^~ reduction xnor

== logical equality, result may be unknown if x or z in the input if (a == b)

=== logical equality including x and z
!= logical inequality, result may be unknown if x or z in the input
!== logical inequality including x and z
> relational greater than
a = shiftvalue >>
>> shift right by a number of positions
>= relational greater than or equal
< relational less than
<< shift left by a number of positions
<= relational less than or equal if (a <= b)
non blocking assignment statement, schedules assignment for
<= #5 b <= b + 2;
future and allows next statement to execute
blocking assignment statement, waits until assignment time
= #5 a = a + 2;
before allowing next statement to execute
Verilog also supports arithmetic, replication, and concatenation operators

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