module fullAdder_b(cOut, sum, aIn, bIn, cIn);

output cOut, sum;

input aIn, bIn, cIn;
reg[1:0]tmp;
reg cOut, sum;
always @(aIn or bIn or cIn)
begin
Imp = aIn+bIn+cIn;
sum = tmp[0];
cOut = tmp[1];
end
endmodule
//Parametrized Models for datapath using continuous assignments
`define clock_period 10
module adder(in1, in2, sum, carry, cc);
parameter size = 32; //default is 32-bit adder
input [size-1:0] in1, in2;
output [1:0] cc; // condition code
output [size-1:0] sum;
output carry;
assign #`clock_period{carry, sum} = in1 + in2;
// Set condition codes
assign cc[0] = (sum == 0)? 1:0;//Condition Code 0 - Zero Value
60 Chapter 3
assign cc[l] = (sum[size-l]); //Condition Code 1 - Negative Value
endmodule
module multiplier(inl, in2, product, carry, cc);
parameter size = 32; //default is 8-bit adder
input [size-l:0] inl, in2;
output [size-1:0] product;
output carry;
output [1:0] cc; // condition code
assign #(2*`clock_period) {carry, product} = inl * in2;
// Set condition codes
assign cc[0] = (product == 0)? 1:0; //Condition Code 0 - Zero Value
assign cc[l] = (product[size-l]); //Condition Code 1 - Negative Value
endmodule
module alu;
endmodule
module multiplexor(out, control, inl, in2, in3, in4);
parameter size = 32;
input [1:0] control;
input [size-l:0] inl, in2, in3, in4;
output [size-1:0] out;
assign out = (control == 0) ? inl :
((control == 1) ? in2 :
((control == 2) ? in3 :
((control == 3) ? in4 :
'bx)));
endmodule
module bus_control;
parameter size = 32;
tri [size-l:0]bus;
wire [size-l:0] data;
wire dcontrol;
assign bus = dcontrol ? data: 128'bz;
endmodule
module comparator(inl, in2, compare);
parameter size=32;
ABSTRACTION LEVELS IN VERILOG 61
input [size-l:0] inl, in2;
output compare;
assign compare = (inl == in2);
endmodule
module xdetect(in, xdet);
parameter size=32;
input [size-1:0] in;
output xdet;
assign xdet = ((in == in) ? 0:1);
endmodule
module barrel_shifter(func, mode, out, in);
parameter size = 32;
output [size-1:0] out;
input [size-l:0] in;
input func, mode;
`define SHIFT 1
`define ROTATE 0
`define LEFT 1
`define RIGHT 0
`define shift_expr (mode ? (in << 1): (in >> 1))
`define rotate_expr (mode ? ({in[size-2:0], in[size-l]}): ({in[0], in[size-l:l]}
))
assign out = `shift_expr;
assign out = `rotate_expr;
assign out = func ? `shift_expr: `rotate_expr;
endmodule
module test;
parameter alu_size = 64;
//Build and test a 64-bit alu using the above datapath elements
wire [alu_size-l:0] sum, prod, shift_out, out;
wire cl,c2;
reg [alu_size-l:0] rl, r2;
reg func 1, mode;
reg [1:0] control;
62 Chapter 3
reg [1:0] func2;
wire [1:0] ccodel, ccode2;
/* Build 64-bit DataPath and test it using the above Verilog modules */
adder a (rl, r2, sum, cl, ccodel);
multiplier m (rl, r2, prod, c2, ccode2);
comparator c (rl, r2, compare_out);
barrel_shifter b (funcl, mode, shift_out, rl);
multiplexor mx(out, func2, sum, prod, {compare_out,63'b0}, shift_out);
defparam a.size = alu_size;
defparam m.size = alu_size;
defparam c.size = alu_size;
defparam b.size = alu_size;
defparam mx.size = alu_size;
initial
begin: testl
rl = 5;
r2 = 3;
funcl = 1;
mode = 1;
for (func2 =0; func2 <=3; func2=func2+l)
begin
#100
$display("alu inputs func2 = %0d inl=%0d and in2=%0d func=%0d
mode=%0d give output out =%0d with carryl=%0d carry2=%0d and condition codel=%0d
code2=%0d",
func2, rl, r2, funcl, mode, out, cl, c2, ccodel, ccode2);
if (func2 == 3) disable testl;
end
end
endmodule