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EGR 220 Laboratory

Experiment #10

MOSFET Amplifiers

Gabriel Chong, Than Aung

March 24, 2008


INTRODUCTION VDD

The purpose of this lab is to explore the operation of


RD=1k
MOSFETs. The operation of the MOSFET will be
+5V
investigated under both the DC and AC operation
conditions. Point by point characteristics will be RGG=10k D
10k G
taken using the multimeter to view the DC pot. 14
VGG
operation and the oscilloscope will be used to view S C=
the AC operation.
0.1F
EQUIPMENT
Figure 2
For this lab the HP 54603B Oscilloscope is used in
junction with the HP BenchLink XL software to The circuit in Figure 2 was constructed using one of
capture data and visual representations of inputs and the NMOS devices in the CD 4007 MOS array.
outputs of the transformer. The HP E3630A Power
Supply is used to provide power to the circuits built. The threshold voltage was determined by first setting
The HP 33120A Function generator will be used to VDD to 10V and VG to 0V. The potentiometer was
supply the AC signals to the circuit. The circuits then slowly adjusted, effectively altering VGG until a
are comprised of the CD 4007 MOS array, various small drain current began to flow through the
capacitors, resistors, a potentiometer and wires. MOSFET. The value of VG was recorded at this point
as the threshold voltage, VT.
PROCEDURE 1
Next, VG was rounded up to the closest integer value.
The purpose of this section is to analyze the DC The drain current, ID, and drain voltage, VD, were
operation of the MOSFET and use point by point recorded at this point. VDD was then decreased by
measurements to determine the threshold voltage, 1V and the drain values were recorded again. This
VTN, the FET characteristic, K, and the Early process was repeated until 0V was reached. VG was
voltage, VA. then increased by 1V and VDD was set back to 10V
and the process of measuring drain voltage and
14 13 12 11 10 9 8 current then reducing VDD was repeated. This
process was repeated until VG reached a value of 5V.
The ID-VD graphs were then plotted as a function of
VG and the values of VT, K and VA were determined
from this graph.

Results Procedure 1

VTN = 1.617V
Vg=2V
1 2 3 4 5 6 7 Vdd (V) Id(uA) Vd (V)
Figure 1 10 97.3 9.88
9 95.8 8.88
Figure 1 shows the layout of the CD 4007 MOS 8 94.5 7.88
array used for this lab. The chip contains three n- 7 93.3 6.89
channel MOSFETs and three p-channel MOSFETs. 6 92.1 5.89
5 90.8 4.91
This lab will concentrate on the use of the NMOS
4 89.4 3.91
devices.
3 87.8 2.9
2 85.9 1.91
1 82.8 0.92
0 0 0
-3 I-V Graph for MOSFET as a function of V GS
x 10
3.5
Vg=3 VGS = 2V

Vdd (V) Id(mA) Vd (V) 3


VGS = 3V
VGS = 4V
10 0.745 9.23 VGS = 5V

9 0.737 8.25 2.5

8 0.728 7.26
7 0.721 6.27 2

ID (A)
6 0.712 5.29
1.5
5 0.703 4.3
4 0.692 3.31 1
3 0.678 2.31
2 0.658 1.34 0.5

1 0.5 0.49
0 0 0 0
0 1 2 3 4 5 6 7 8 9 10
VD (V)

Vg=4
Graph 1- I-V Graph for MOSFET as a Function of V GS
Vdd (V) Id(mA) Vd (V)
10 1.866 8.14 K =.18794749386742178681145468836546e-2
9 1.848 7.15
8 1.83 6.91 4
x 10
-3 I-V Graph for MOSFET as a function of V GS

7 1.81 5.2 VGS = 2V


VGS = 3V
6 1.789 4.22 3.5
VGS = 4V

5 1.762 3.24 3
VGS = 5V
Triode/Saturation Separation
4 1.724 2.28
2.5
3 1.627 1.37
2 1.248 0.74
ID (A)

1 0.671 0.34
1.5
0 0 0
1

Vg=5 0.5
Vdd (V) Id(mA) Vd (V)
10 3.31 6.72 0
0 1 2 3 4 5 6 7 8 9 10
VD (V)
9 3.28 5.74
8 3.24 4.77
Graph 2- Line Separating Triode and Saturation Regions
7 3.2 3.81
6 3.14 2.88 VGS VDS Separating Triode and Saturation Region
5 3.02 1.98 2 0.1
4 2.65 1.34 3 0.78
3 2.07 0.91 4 1.3
2 1.43 0.55 5 1.74
1 0.751 0.26 Table 2- Values of VDS Separating Regions at Different VGS
0 0 0
Table 1- Results from point by point measurement
x 10
-3 I-V Graph for MOSFET as a function of V GS points as a starting point a line was calculated using
MATLAB to extend until the line crossed the
4
voltage axis, and the current became zero. The
VGS = 2V
3.5 VGS = 3V voltage at this point defines the early voltage. The
3
VGS = 4V
VGS = 5V
values determined match up with the range for
Triode/Saturation Separation expected values.
2.5
ID (A)

1.5

0.5

0
-25 -20 -15 -10 -5 0 5 10
VD (V)

Graph 3- Lines Used to Calculate Early Voltage


Early Voltage as determined by VGS=2V graph = -25.5200V
Early Voltage as determined by VGS=5V graph = -20.6700V

DISCUSSION AND SUMMARY

Discussion on Procedure 1
Graph 1 shows a plot of the ID vs.VD data collected
plotted as a function of VGS. This plot is very
similar to graphs seen in Sedra Smith’s
‘Microelectronic Circuits’ which show the value of
I vs. V plotted as a function of VGS, therefore the
experimental method is sound and the data collected
very accurate.

This data was then used to determine a value for K


based on the drain current and overdrive voltage at
the highest values of current and voltage in the
saturation region. An average was taken across the
varying VGS values. The value for K is on the
correct order of magnitude as would be expected.

Once this value of K was determined it was possible


to plot the line separating the triode region from the
saturation region, by knowing the equation which
defined this line. Once this line was drawn, the
points of intersection between this line and the I-V
plots of the MOSFET were discovered in the
MATLAB plot window. The values determined are
closed to the expected values, however they vary
slightly because the method for determining K was
not exact, but rather an average.

The values on the 2V and 5V I-V plots closest to


the separation between triode and saturation, while
still in saturation, were used to define the slope for
the line used to find the Early voltage. Using these