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HDL LAB MANUAL

4TH SEM ELECTONICS AND COMMUNICATION

S K LAKSHMI NARAYAN

R C VISHVAKIRAN

AND COMMUNICATION S K LAKSHMI NARAYAN R C VISHVAKIRAN 2 0 1 2 10ESL 48 ELECTRONICS

2

0

1

2

10ESL 48

COMMUNICATION S K LAKSHMI NARAYAN R C VISHVAKIRAN 2 0 1 2 10ESL 48 ELECTRONICS AND

ELECTRONICS AND COMMUNICATION ENGG DEPT.

S K LAKSHMI NARAYAN R C VISHVAKIRAN 2 0 1 2 10ESL 48 ELECTRONICS AND COMMUNICATION

CONTENTS

PART A:

PROGRAMMING (using VHDL and Verilog)

1. Write HDL code to realize all the logic gates

 

1

2. Write a HDL program for the following combinational designs

 

3-16

a. 2 to 4 decoder

3

b. 8 to 3 (encoder without priority & with priority)

 

5,7

c. 8 to 1 multiplexer

9

d. 4 bit binary to gray converter

 

11

e. De-multiplexer, comparator

13,15

3. Write a HDL code to describe the functions of a Full Adder Using 3 modeling styles

 

17-21

a. Full Adder Data Flow Description

 

17

b. Full Adder Behavioral Description

18

c. Full Adder Structural Description

20

4. Write

a shown below A (31:0) B (31:0)

model

for

32

bit

ALU

using

the

schematic

 

diagram

22

ALU

should

use

combinational

logic

to

calculate

an

output

based

on

the

four-bit

op-code input.

ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable line is low.

ALU should decode the 4 bit op-code according to the given in example below.

OPCODE

ALU OPERATION

1.

 

A + B

2.

 

A – B

3.

A Complement

4.

A

AND B

5.

A OR B

6.

A NAND B

7.

A

XOR B

OPCODE ENABLE ALU OPERATION
OPCODE ENABLE ALU OPERATION

OPCODE

ENABLE

ALU

OPCODE ENABLE ALU OPERATION

OPERATION

5. Develop the HDL code for the following flip-flops, SR, JK, D, T

 

24-31

a. SR Flip Flop

 

24

b. JK Flip Flop

26

c. D Flip Flop

28

d. T Flip Flop

30

6. Design

4

bit

binary,

BCD

counters

(Synchronous

reset

and

Asynchronous

reset)

and “any sequence” counters

 

32-40

a. Binary Synchronous Reset 4bit Counter

 

32

b. Binary Asynchronous Reset 4bit Counter

33

c. BCD Synchronous Reset 4bit Counter

35

d. BCD Asynchronous Reset 4bit Counter

37

e. Binary Any Sequence up down 4bit Counter

 

39

i

PART B:

INTERFACING (at least four of the following must be covered using VHDL/Verilog)

1. Write HDL code to display messages on the given seven segment display and LCD and accepting

Hex keypad input data

 

41-47

a. 7 Segment Display

41

b. LCD Display

 

45

2. Write HDL code to control speed, direction of DC and Stepper motor

 

48-53

a. Stepper Motor

 

48

b. DC Motor

 

51

3. Write HDL code to control external lights using

 

54

4. Write

HDL

code

to

generate

different

waveforms

(Sine,

Square,

Triangle,

Ramp etc.,) using DAC change the frequency and amplitude

 

56-66

a. Sine Wave

 

57

b. Square Wave

59

c. Triangle Wave

 

61

d. Positive Ramp

63

e.

Negative Ramp

65

Web link: http://www.scribd.com/doc/49031100

ii

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

1. ALL LOGIC GATES

a_in

b_in

ALL

LOGIC

GATES

not_opB ANGALORE 1. ALL LOGIC GATES a_in b_in ALL LOGIC GATES and_op nand_op or_op nor_op xor_op

and_op1. ALL LOGIC GATES a_in b_in ALL LOGIC GATES not_op nand_op or_op nor_op xor_op xnor_op inputs

nand_opALL LOGIC GATES a_in b_in ALL LOGIC GATES not_op and_op or_op nor_op xor_op xnor_op inputs outputs

or_opGATES a_in b_in ALL LOGIC GATES not_op and_op nand_op nor_op xor_op xnor_op inputs outputs Figure 1:

nor_opa_in b_in ALL LOGIC GATES not_op and_op nand_op or_op xor_op xnor_op inputs outputs Figure 1: Block

xor_opb_in ALL LOGIC GATES not_op and_op nand_op or_op nor_op xnor_op inputs outputs Figure 1: Block Diagram

xnor_opLOGIC GATES not_op and_op nand_op or_op nor_op xor_op inputs outputs Figure 1: Block Diagram of All

GATES not_op and_op nand_op or_op nor_op xor_op xnor_op inputs outputs Figure 1: Block Diagram of All

inputs

outputs

and_op nand_op or_op nor_op xor_op xnor_op inputs outputs Figure 1: Block Diagram of All Logic Gates

Figure 1: Block Diagram of All Logic Gates

not_op a_in and_op b_in nand_op or_op nor_op xor_op xnor_op
not_op
a_in
and_op
b_in
nand_op
or_op
nor_op
xor_op
xnor_op

Logic Diagram of All Gates

Inputs

 

Outputs

a_in

b_in

not_op

and_op

nand_op

       

(a_in)

or_op

nor_op

xor_op

xnor_op

0

0

1

0

1

 

0 1

0

1

0

1

1

0

1

 

1 0

1

0

 

1 0

0

0

1

 

1 0

1

0

 

1 1

0

1

0

 

1 0

0

1

Truth Table 1: All Logic Gates

VHDL File Name: AlllogicGates.vhd -- All Logic Gates - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AllLogicGates is

port (

a_in

: in STD_LOGIC;

b_in

: in STD_LOGIC;

not_op

: out STD_LOGIC;

and_op

: out STD_LOGIC;

nand_op : out STD_LOGIC;

or_op

: out STD_LOGIC;

nor_op

: out STD_LOGIC;

xor_op

: out STD_LOGIC;

xnor_op : out STD_LOGIC); end AllLogicGates;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

architecture DataFlow of AllLogicGates is begin

not_op <= not a_in; and_op <= a_in and b_in;

nand_op <= a_in nand b_in;

or_op

nor_op <= a_in nor b_in; xor_op <= a_in xor b_in; xnor_op <= a_in xnor b_in; end DataFlow;

<= a_in or b_in;

Verilog File Name: AlllogicGates.v // All Logic Gates module AllLogicGates( a_in, b_in, not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op ); input a_in, b_in; output not_op, and_op, nand_op, or_op, nor_op, xor_op, xnor_op;

assign

not_op = ~(a_in);

assign

and_op =

a_in & b_in;

assign

nand_op = ~(a_in & b_in);

assign

or_op

=

a_in | b_in;

assign

nor_op

= ~(a_in | b_in);

assign

xor_op =

a_in ^ b_in;

assign

xnor_op = ~(a_in ^ b_in);

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

2. Decoder 2 to 4

d_in

2

E&C D EPT ., CEC, B ANGALORE 2. Decoder 2 to 4 d_in 2 inputs en

inputs

enD EPT ., CEC, B ANGALORE 2. Decoder 2 to 4 d_in 2 inputs Decoder 2

Decoder 2 to 4

4

ANGALORE 2. Decoder 2 to 4 d_in 2 inputs en Decoder 2 to 4 4 outputs

outputs

2. Decoder 2 to 4 d_in 2 inputs en Decoder 2 to 4 4 outputs d_op

d_op

Figure 2: Block Diagram of Decoder 2 to 4

 

Inputs

 

Outputs

 

en

d_in(1)

d_in(0)

d_op(3)

d_op(2)

d_op(1)

d_op(0)

1

X

X

Z

Z

Z

Z

0

0

0

0

0

0

1

0

0

1

0

0

1

0

0

1

0

0

1

0

0

0

1

1

1

0

0

0

Truth Table 2: Decoder 2 to 4

VHDL File Name: decoder2to4.vhd -- decoder2to4 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity decoder2to4 is

Port ( d_in : in STD_LOGIC_VECTOR (1 downto 0);

en

: in STD_LOGIC;

d_op : out STD_LOGIC_VECTOR (3 downto 0)); end decoder2to4;

architecture Behavioral of decoder2to4 is begin

process(en,d_in)

begin

if(en/='0')then -- Active Low Enabled d_op<="ZZZZ";

else

case d_in is when "00" => d_op <= "0001"; when "01" => d_op <= "0010"; when "10" => d_op <= "0100"; when "11" => d_op <= "1000"; when others => d_op <= "ZZZZ"; end case; end if; end process; end Behavioral;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

Verilog File Name: decoder2to4.v // decoder2to4 module decoder2to4( d_in, en, d_op ); input [1:0] d_in; input en; output [3:0] d_op; wire en; wire [1:0] d_in; reg [3:0] d_op;

always @ (en, d_in) begin

if(en) // Active Low Enabled d_op = 4'bZZZZ;

else

begin

case (d_in) 2'b00 : d_op = 4'b0001; 2'b01 : d_op = 4'b0010; 2'b10 : d_op = 4'b0100; 2'b11 : d_op = 4'b1000; default : d_op = 4'bZZZZ; endcase

end

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

3. Encoder Without Priority

8

D EPT ., CEC, B ANGALORE 3. Encoder Without Priority 8 Encoder Without Priority 3 outputs

Encoder Without Priority

Encoder Without Priority

3

3

outputs

Priority 8 Encoder Without Priority 3 outputs a_in inputs en y_op Figure 3: Block Diagram of

a_in

inputs

en
en

y_op

Figure 3: Block Diagram of Encoder Without Priority

 

Inputs

 

Outputs

 

a_in(7)

a_in(6)

a_in(5)

a_in(4)

a_in(3)

a_in(2)

a_in(1)

a_in(0)

y_op

y_op

y_op

en

(2)

(1)

(0)

1

X

X

X

X

X

X

X

X

Z

Z

Z

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

0

1

0

1

0

0

1

0

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

0

1

1

1

Truth Table 3: Encoder Without Priority

VHDL File Name: encd_wo_prior.vhd -- encoder without priority - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encd_wo_prior is Port ( en : in STD_LOGIC; a_in : in STD_LOGIC_VECTOR (7 downto 0); y_op : out STD_LOGIC_VECTOR (2 downto 0)); end encd_wo_prior;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

architecture Behavioral of encd_wo_prior is begin

process (en,a_in) begin

if(en /= '0') then -- Active Low Enabled y_op <= "ZZZ";

else

case a_in is when "00000001" => y_op <= "000"; when "00000010" => y_op <= "001"; when "00000100" => y_op <= "010"; when "00001000" => y_op <= "011"; when "00010000" => y_op <= "100"; when "00100000" => y_op <= "101"; when "01000000" => y_op <= "110"; when "10000000" => y_op <= "111"; when others => y_op <= "ZZZ"; end case; end if; end process; end Behavioral;

Verilog File Name: encd_wo_prior.v // encoder without priority module encd_wo_prior( en, a_in, y_op ); input en; input [7:0] a_in; output [2:0] y_op; wire en; wire [7:0] a_in; reg [2:0] y_op;

always @ (a_in, en) begin

if(en) //Active Low Enabled y_op = 3'bZZZ;

else

begin

case (a_in) 8'b00000001 : y_op = 3'b000; 8'b00000010 : y_op = 3'b001; 8'b00000100 : y_op = 3'b010; 8'b00001000 : y_op = 3'b011; 8'b00010000 : y_op = 3'b100; 8'b00100000 : y_op = 3'b101; 8'b01000000 : y_op = 3'b110; 8'b10000000 : y_op = 3'b111; default : y_op = 3'bZZZ; endcase

end

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

4. Encoder With Priority

8

E&C D EPT ., CEC, B ANGALORE 4. Encoder With Priority 8 Encoder With Priority 3

Encoder

With Priority

3

3

outputs

With Priority 8 Encoder With Priority 3 outputs a_in inputs en y_op Figure 4: Block Diagram

a_in

inputs

en
en

y_op

Figure 4: Block Diagram of Encoder With Priority

 

Inputs

 

Outputs

en

a_in(7)

a_in(6)

a_in(5)

a_in(4)

a_in(3)

a_in(2)

a_in(1)

a_in

y_op

y_op

y_op

(0)

(2)

(1)

(0)

1

X

X

X

X

X

X

X

X

Z

Z

Z

0

1

X

X

X

X

X

X

X

1

1

1

0

0

1

X

X

X

X

X

X

1

1

0

0

0

0

1

X

X

X

X

X

1

0

1

0

0

0

0

1

X

X

X

X

1

0

0

0

0

0

0

0

1

X

X

X

0

1

1

0

0

0

0

0

0

1

X

X

0

1

0

0

0

0

0

0

0

0

1

X

0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

Truth Table 4: Encoder With Priority

VHDL File Name: encd_w_prior.vhd -- encd_w_prior - Dataflow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encd_w_prior is Port ( en : in STD_LOGIC; a_in : in STD_LOGIC_VECTOR (7 downto 0); y_op : out STD_LOGIC_VECTOR (2 downto 0)); end encd_w_prior;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

architecture Dataflow of encd_w_prior is begin

y_op <=

end Dataflow;

"ZZZ" when en = '1' else -- Active Low Enabled "111" when a_in(7)='1' else "110" when a_in(6)='1' else "101" when a_in(5)='1' else "100" when a_in(4)='1' else "011" when a_in(3)='1' else "010" when a_in(2)='1' else "001" when a_in(1)='1' else "000" when a_in(0)='1' else "ZZZ";

Verilog File Name: encd_w_prior.v // encoder with priority module encd_w_prior( en, a_in, y_op ); input en; input [7:0] a_in; output [2:0] y_op; wire en; wire [7:0] a_in; reg [2:0] y_op;

always @ (a_in, en) begin

if (en == 1'b1) // Active Low Enabled y_op = 3'bZZZ;

else begin if(a_in[7] == 1'b1) y_op = 3'b111; else if(a_in[6] == 1'b1) y_op = 3'b110; else if(a_in[5] == 1'b1) y_op = 3'b101; else if(a_in[4] == 1'b1) y_op = 3'b100; else if(a_in[3] == 1'b1) y_op = 3'b011; else if(a_in[2] == 1'b1) y_op = 3'b010; else if(a_in[1] == 1'b1) y_op = 3'b001; else if(a_in[0] == 1'b1) y_op = 3'b000; else y_op = 3'bZZZ;

end

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

5. Multiplexer 8 to 1

8

E&C D EPT ., CEC, B ANGALORE 5. Multiplexer 8 to 1 8 Multiplexer 8 to
Multiplexer 8 to 1 output

Multiplexer 8 to 1

Multiplexer 8 to 1 output

output

5. Multiplexer 8 to 1 8 Multiplexer 8 to 1 output i_in inputs en 3 sel

i_in

inputs

en8 to 1 8 Multiplexer 8 to 1 output i_in inputs 3 sel Figure 5: Block

3
3

sel Figure 5: Block Diagram of Multiplexer 8 to 1

y_out

 

Inputs

Output

en

sel

sel

sel

i_in

i_in

i_in

i_in

i_in

i_in

i_in

i_in

y_out

(2)

(1)

(0)

(7)

(6)

(5)

(4)

(3)

(2)

(1)

(0)

1

X

X

X

X

X

X

X

X

X

X

X

Z

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

0

1

0

1

0

0

1

0

0

0

0

0

0

1

0

0

1

0

0

1

1

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

1

0

0

0

0

1

0

1

0

1

0

0

1

0

0

0

0

0

1

0

1

1

0

0

1

0

0

0

0

0

0

1

0

1

1

1

1

0

0

0

0

0

0

0

1

Truth Table 5: Mux 8 to 1

VHDL File Name: mux8to1.vhd --mux8to1 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8to1 is Port ( en : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (2 downto 0); i_in : in STD_LOGIC_VECTOR (7 downto 0); y_out : out STD_LOGIC);

end mux8to1; architecture Behavioral of mux8to1 is begin

process(en,sel,i_in)

begin

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

if( en /= '0') then -- Active Low Enabled y_out <= 'Z';

else

case sel is when "000" => y_out <= i_in(0); when "001" => y_out <= i_in(1); when "010" => y_out <= i_in(2); when "011" => y_out <= i_in(3); when "100" => y_out <= i_in(4); when "101" => y_out <= i_in(5); when "110" => y_out <= i_in(6); when "111" => y_out <= i_in(7); when others => y_out <= 'Z'; end case; end if; end process; end Behavioral;

Verilog File Name: mux8to1.v // Multiplexer 8 to 1 module mux8to1(en,i_in,sel,y_out); input en; input [2:0] sel; input [7:0] i_in; output y_out; wire en; wire [7:0] i_in; wire [2:0] sel; reg y_out;

always@(en,sel,i_in)

begin

if(en != 0) // Active Low Enabled y_out = 1'bZ;

else

begin

case(sel) 3'b000: y_out = i_in[0]; 3'b001: y_out = i_in[1]; 3'b010: y_out = i_in[2]; 3'b011: y_out = i_in[3]; 3'b100: y_out = i_in[4]; 3'b101: y_out = i_in[5]; 3'b110: y_out = i_in[6]; 3'b111: y_out = i_in[7]; default: y_out = 1'bZ; endcase

end

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

6. 4Bit Binary to Gray Converter

b_in

inputs

4

B ANGALORE 6. 4Bit Binary to Gray Converter b_in inputs 4 Binary to Gray Converter 4

Binary

to

Gray

Converter

4

Converter b_in inputs 4 Binary to Gray Converter 4 outputs g_op Figure 6: Block Diagram of

outputs

b_in inputs 4 Binary to Gray Converter 4 outputs g_op Figure 6: Block Diagram of Binary

g_op

Figure 6: Block Diagram of Binary to Gray Converter

b_in(0) g_op(0) b_in(1) g_op(1) b_in(2) g_op(2) b_in(3) g_op(3)
b_in(0)
g_op(0)
b_in(1)
g_op(1)
b_in(2)
g_op(2)
b_in(3)
g_op(3)

Logic Diagram of 4bits Binary to Gray Converter

Boolean Expressions g_op(3) = b_in(3) g_op(2) = b_in(3) b_in(2) g_op(1) = b_in(2) b_in(1) g_op(0) = b_in(1) b_in(0)

 

Inputs

 

Outputs

 

Decimal

 

Binary

 

Gray

 

b_in(3)

b_in(2)

b_in(1)

b_in(0)

g_op(3)

g_op(2)

g_op(1)

g_op(0)

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

1

2

0

0

1

0

0

0

1

1

3

0

0

1

1

0

0

1

0

4

0

1

0

0

0

1

1

0

5

0

1

0

1

0

1

1

1

6

0

1

1

0

0

1

0

1

7

0

1

1

1

0

1

0

0

8

1

0

0

0

1

1

0

0

9

1

0

0

1

1

1

0

1

10

1

0

1

0

1

1

1

1

11

1

0

1

1

1

1

1

0

12

1

1

0

0

1

0

1

0

13

1

1

0

1

1

0

1

1

14

1

1

1

0

1

0

0

1

15

1

1

1

1

1

0

0

0

Truth Table 6: Binary to Gray

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: bin_to_gray_4bit.vhd -- Binary to Gray 4 bit converter - Dataflow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin_to_gray_4bit is Port ( b_in : in STD_LOGIC_VECTOR (3 downto 0); g_op : out STD_LOGIC_VECTOR (3 downto 0)); end bin_to_gray_4bit;

architecture Dataflow of bin_to_gray_4bit is begin

g_op(3) <= b_in(3); g_op(2) <= b_in(3) xor b_in(2); g_op(1) <= b_in(2) xor b_in(1); g_op(0) <= b_in(1) xor b_in(0); end Dataflow;

Verilog File Name: bin_to_gray_4bit.v // Binary to Gray 4bit Converter module bin_to_gray_4bit( b_in, g_op ); input [3:0] b_in; output [3:0] g_op; wire [3:0] b_in; reg [3:0] g_op;

always @ (b_in) begin

g_op[3] = b_in[3]; g_op[2] = b_in[3] ^ b_in[2]; g_op[1] = b_in[2] ^ b_in[1]; g_op[0] = b_in[1] ^ b_in[0];

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

7. Demultiplexer 1 to 4

Demultiplexer 1 to 4

enCEC, B ANGALORE 7. Demultiplexer 1 to 4 Demultiplexer 1 to 4 sel a_in inputs 2

sel

a_in

inputs

2

1 to 4 Demultiplexer 1 to 4 en sel a_in inputs 2 4 outputs y_out Figure
1 to 4 Demultiplexer 1 to 4 en sel a_in inputs 2 4 outputs y_out Figure

4

1 to 4 Demultiplexer 1 to 4 en sel a_in inputs 2 4 outputs y_out Figure

outputs

1 to 4 Demultiplexer 1 to 4 en sel a_in inputs 2 4 outputs y_out Figure

y_out

Figure 7: Block Diagram of Demultiplexer 1 to 4

 

Inputs

   

Outputs

 

en

sel (1)

sel (0)

a_in

y_out (3)

y_out (2)

y_out (1)

y_out (0)

1

X

X

X

Z

Z

Z

Z

0

0

0

1

0

0

0

1

0

0

1

1

0

0

1

0

0

1

0

1

0

1

0

0

0

1

1

1

1

0

0

0

Truth Table 7: Demux 1 to 4

VHDL File Name: demux1to4.vhd -- Demux1to4 - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demux1to4 is

Port (

en

: in STD_LOGIC;

sel

: in STD_LOGIC_VECTOR(1 downto 0);

a_in : in STD_LOGIC; y_out : out STD_LOGIC_VECTOR (3 downto 0));

end demux1to4;

architecture Behavioral of demux1to4 is begin

process(en,sel,a_in)

begin

if(en /= '0') then -- Active Low Enabled y_out <= "ZZZZ";

else

y_out <= "0000"; case sel is when "00" => y_out(0) <= a_in; when "01" => y_out(1) <= a_in; when "10" => y_out(2) <= a_in; when "11" => y_out(3) <= a_in; when others => y_out <= "ZZZZ"; end case; end if; end process; end Behavioral;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

Verilog File Name: demux1to4.v // Demultiplexer 1 to 4 module demux1to4(en,sel,a_in,y_out); input en; input [1:0] sel; input a_in; output [3:0] y_out; wire en; wire [1:0] sel; wire a_in; reg [3:0] y_out;

always@(en,sel,a_in)

begin

if(en != 0) // Active Low Enabled y_out = 4'bZZZZ;

else

begin

y_out = 4'b0000; case(sel) 2'b00 : y_out[0] = a_in; 2'b01 : y_out[1] = a_in; 2'b10 : y_out[2] = a_in; 2'b11 : y_out[3] = a_in; default : y_out = 4'bZZZZ; endcase

end

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

8. 4Bit Comparator

a_in

b_in

Comparator 4bit outputs

Comparator 4bit

Comparator 4bit
Comparator 4bit outputs
Comparator 4bit outputs

outputs

Comparator 4bit outputs
Comparator 4bit outputs

8. 4Bit Comparator a_in b_in Comparator 4bit outputs 4 inputs 4 g_op L_op e_op Figure 8:

4 4

inputs

4

Comparator a_in b_in Comparator 4bit outputs 4 inputs 4 g_op L_op e_op Figure 8: Block Diagram

g_opComparator a_in b_in Comparator 4bit outputs 4 inputs 4 L_op e_op Figure 8: Block Diagram of

L_opa_in b_in Comparator 4bit outputs 4 inputs 4 g_op e_op Figure 8: Block Diagram of Comparator

e_op

Figure 8: Block Diagram of Comparator 4bit

   

Outputs

Inputs

a_in > b_in

a_in = b_in

a_in < b_in

a_in

b_in

g_op

e_op

L_op

----

----

Z

Z

Z

1100

0011

1

0

0

0110

0110

0

1

0

1000

1110

0

0

1

Truth Table 8: Comparator 4Bits

VHDL File Name: comparator4bit.vhd --Comparator4bit - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator4bit is

Port (

a_in : in STD_LOGIC_VECTOR (3 downto 0); b_in : in STD_LOGIC_VECTOR (3 downto 0);

g_op : out STD_LOGIC; e_op : out STD_LOGIC; L_op : out STD_LOGIC); end comparator4bit;

architecture Behavioral of comparator4bit is begin

process(a_in,b_in)

begin

if( a_in > b_in) then g_op <= '1'; e_op <= '0'; L_op <= '0'; elsif(a_in = b_in) then g_op <= '0'; e_op <= '1'; L_op <= '0'; elsif(a_in < b_in) then g_op <= '0'; e_op <= '0'; L_op <= '1';

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

else

g_op <= 'Z'; e_op <= 'Z'; L_op <= 'Z'; end if; end process; end Behavioral;

Verilog File Name: comparator4bit.v // Comparator 4bit module comparator4bit( a_in,b_in,g_op,L_op,e_op); input [3:0] a_in,b_in; output g_op,L_op,e_op; wire [3:0] a_in,b_in; reg g_op,L_op,e_op;

always@(a_in,b_in) if( a_in > b_in) begin

g_op = 1; L_op = 0; e_op = 0;

end else if( a_in < b_in) begin

g_op = 0; L_op = 1; e_op = 0;

end else if( a_in == b_in) begin

end

else

begin

end

endmodule

g_op = 0; L_op = 0; e_op = 1;

g_op = 1'bZ; L_op = 1'bZ; e_op = 1'bZ;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

9. Full Adder

a_in

b_in

c_in

Full Adder outputs

Full Adder

Full Adder outputs
Full Adder outputs

outputs

Full Adder outputs
ANGALORE 9. Full Adder a_in b_in c_in Full Adder outputs sum inputs carry Figure 9: Block

sumANGALORE 9. Full Adder a_in b_in c_in Full Adder outputs inputs carry Figure 9: Block Diagram

inputs9. Full Adder a_in b_in c_in Full Adder outputs sum carry Figure 9: Block Diagram of

Full Adder a_in b_in c_in Full Adder outputs sum inputs carry Figure 9: Block Diagram of

carryFull Adder a_in b_in c_in Full Adder outputs sum inputs Figure 9: Block Diagram of Full

Figure 9: Block Diagram of Full Adder

a_in S1 b_in x1 sum x2 a2 S3 carry o1 a1 S2 c_in
a_in
S1
b_in
x1
sum
x2
a2
S3
carry
o1
a1
S2
c_in

Logic Diagram of Full Adder

 

Inputs

Outputs

a_in

b_in

c_in

sum

carry

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Truth Table 9: Full Adder

Full Adder Data Flow Description

VHDL File Name: FullAdder_DF.vhd -- FullAdder_DF - Data_Flow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder_DF is

Port ( a_in, b_in, c_in : in STD_LOGIC;

sum, carry end FullAdder_DF;

: out STD_LOGIC);

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

architecture Data_Flow of FullAdder_DF is begin

sum <= a_in xor b_in xor c_in; carry <= (a_in and b_in) or (b_in and c_in) or (a_in and c_in);

end Data_Flow;

Verilog File Name: FullAdder_DF.v // FullAdder - Data Flow Model module FullAdder_DF( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry;

assign sum = a_in ^ b_in ^ c_in; assign carry = (a_in & b_in) | (b_in & c_in) | (c_in & a_in); endmodule

Full Adder Behavioral Description

VHDL File Name: FullAdder_Behav.vhd -- Full Adder - Behavioral library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder_Behav is

Port ( a_in, b_in, c_in : in STD_LOGIC;

sum, carry end FullAdder_Behav;

: out STD_LOGIC);

architecture Behavioral of FullAdder_Behav is begin

process ( a_in, b_in, c_in) begin

if(a_in='0' and b_in='0' and c_in = '0') then sum <= '0';carry <= '0'; elsif (( a_in='0' and b_in='0' and c_in = '1') or (a_in='0' and b_in='1' and c_in = '0') or (a_in='1' and b_in='0' and c_in = '0')) then sum <= '1';carry <= '0'; elsif (( a_in='0' and b_in='1' and c_in = '1') or (a_in='1' and b_in='0' and c_in = '1') or (a_in='1' and b_in='1' and c_in = '0')) then sum <= '0';carry <= '1'; elsif(a_in='1' and b_in='1' and c_in = '1') then sum <= '1';carry <= '1'; end if; end process; end Behavioral;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

Verilog File Name: FullAdder_Behav.v //FullAdder - Behavioral Model module FullAdder_Behav( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; wire a_in, b_in, c_in; reg sum, carry;

always @ ( a_in, b_in, c_in) begin

if(a_in==0 & b_in==0 & c_in==0) begin

sum = 0; carry = 0;

end

else if (( a_in==0 & b_in==0 & c_in == 1)

| (a_in==0 & b_in==1 & c_in == 0)

| (a_in==1 & b_in==0 & c_in == 0))

begin

sum = 1; carry = 0;

end

else if (( a_in==0 & b_in==1 & c_in == 1)

| (a_in==1 & b_in==0 & c_in == 1)

| (a_in==1 & b_in==1 & c_in == 0))

begin

sum = 0; carry = 1;

end else if(a_in==1 & b_in==1 & c_in == 1) begin

end

end

endmodule

sum = 1; carry = 1;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

Full Adder Structural Description

VHDL File Name: full_adder_struct.vhd -- Full Adder - Structural library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is port ( a_in, b_in, c_in : in STD_LOGIC; sum,carry : out STD_LOGIC);

end full_adder;

architecture structural of full_adder is component xor2_1 port( a, b : in STD_LOGIC;

y : out STD_LOGIC);

end component; component and2_1 port( a, b : in STD_LOGIC;

y : out STD_LOGIC);

end component; component or2_1 port( a, b : in STD_LOGIC;

y : out STD_LOGIC);

end component; signal s1,s2,s3: STD_LOGIC; begin

x1: xor2_1 port map (a_in, b_in, s1); a1: and2_1 port map (a_in, b_in, s2); x2: xor2_1 port map (s1, c_in, sum); a2: and2_1 port map (s1, c_in, s3);

o1: or2_1 end structural;

port map (s2, s3, carry);

VHDL File Name: xor2_1.vhd -- xor2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xor2_1 is Port ( a,b : in STD_LOGIC; y : out STD_LOGIC);

end xor2_1;

architecture data_flow of xor2_1 is begin

y <= a xor b; end data_flow;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

VHDL File Name: and2_1.vhd -- and2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and2_1 is

port ( a, b : in STD_LOGIC;

end and2_1;

y : out STD_LOGIC);

architecture data_flow of and2_1 is begin

y <= a and b;

end data_flow;

VHDL File Name: or2_1.vhd -- or2_1 - DataFlow library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity or2_1 is

Port ( a,b : in STD_LOGIC;

end or2_1;

y : out STD_LOGIC);

architecture data_flow of or2_1 is begin

y <= a or b;

end data_flow;

Verilog File Name: full_adder_struct.v //Full Adder - Structural module full_adder( a_in, b_in, c_in, sum, carry ); input a_in, b_in, c_in; output sum, carry; wire s1,s2,s3;

//syntax: gate_operator lable (ouput, input, input); xor x1 (s1, a_in, b_in); and a1 (s2, a_in, b_in); xor x2 (sum, s1, c_in); and a2 (s3, s1, c_in); or o1 (carry, s2, s3); endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

10. ALU 32 Bits

en

a_in

b_in

opc

D EPT ., CEC, B ANGALORE 10. ALU 32 Bits en a_in b_in opc 32 ALU

32

ALU 32bits

B ANGALORE 10. ALU 32 Bits en a_in b_in opc 32 ALU 32bits inputs 32 32

inputs

32

32

10. ALU 32 Bits en a_in b_in opc 32 ALU 32bits inputs 32 32 outputs 4

outputs

32 Bits en a_in b_in opc 32 ALU 32bits inputs 32 32 outputs 4 y_op Figure
32 Bits en a_in b_in opc 32 ALU 32bits inputs 32 32 outputs 4 y_op Figure
4
4

y_op

Figure 10: Block Diagram of ALU 32bits

 

Inputs

Outputs

 

en

opc

a_in

b_in

y_op

Actions

0

XXXX

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ

No Change

1

0001

01100000000000000111111111111111

01000000000000000111111110011001

10100000000000001111111110011000

a_in + b_in

1

0010

01100000000000000111111111111111

01000000000000000111111110011001

00100000000000000000000001100110

a_in - b_in

1

0011

01100000000000000111111111111111

01000000000000000111111110011001

10011111111111111000000000000000

not a_in

1

0100

01100000000000000111111111111111

01000000000000000111111110011001

01000000000000000111111110011001

a_in and b_in

1

0101

01100000000000000111111111111111

01000000000000000111111110011001

01100000000000000111111111111111

a_in or b_in

1

0110

01100000000000000111111111111111

01000000000000000111111110011001

10111111111111111000000001100110

a_in nand b_in

1

0111

01100000000000000111111111111111

01000000000000000111111110011001

00100000000000000000000001100110

a_in xor b_in

Truth Table 10: ALU 32bits

VHDL File Name: alu32bit.vhd --ALU32bit – Behavioral

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu32bit is Port ( en : in BIT; opc : in STD_LOGIC_VECTOR (3 downto 0); a_in, b_in : in STD_LOGIC_VECTOR (31 downto 0); y_op : out STD_LOGIC_VECTOR (31 downto 0)); end alu32bit;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

architecture Behavioral of alu32bit is begin

process(en, a_in, b_in, opc) begin

if (en = '1') then -- Active High Enabled case opc is when "0001" => y_op <= a_in + b_in; when "0010" => y_op <= a_in - b_in; when "0011" => y_op <= not a_in; when "0100" => y_op <= a_in and b_in; when "0101" => y_op <= a_in or b_in; when "0110" => y_op <= a_in nand b_in; when "0111" => y_op <= a_in xor b_in; when others => null; end case;

else

y_op <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; end behavioral;

Verilog File Name: alu32bit.v // ALU 32bit module alu32bit( en, opc, a_in, b_in, y_op ); input en; input [3:0] opc; input [31:0] a_in, b_in; output [31:0] y_op; wire en; wire [3:0] opc; wire [31:0] a_in, b_in; reg [31:0] y_op;

always @ ( en, opc, a_in, b_in) if (en == 1) // Active High Enabled case (opc) 4'b0001 : y_op = a_in + b_in; 4'b0010 : y_op = a_in - b_in; 4'b0011 : y_op = ~ a_in; 4'b0100 : y_op = a_in & b_in; 4'b0101 : y_op = a_in | b_in; 4'b0110 : y_op = ~ (a_in & b_in); 4'b0111 : y_op = a_in ^ b_in; default null; endcase

else

y_op = 32'bZ;

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

11.

S R Flip Flop

s

r

rst

clk

D EPT ., CEC, B ANGALORE 11. S R Flip Flop s r rst clk inputs
D EPT ., CEC, B ANGALORE 11. S R Flip Flop s r rst clk inputs

inputs

EPT ., CEC, B ANGALORE 11. S R Flip Flop s r rst clk inputs SR

SR Flip Flop

SR Flip Flop

outputs

q11. S R Flip Flop s r rst clk inputs SR Flip Flop outputs qb Figure

qb11. S R Flip Flop s r rst clk inputs SR Flip Flop outputs q Figure

Figure 11: Block Diagram of SR Flip Flop

 

Inputs

   

Outputs

rst

clk

s

r

q

qb

Action

1

X

 

X

q

qb

No Change

0

0

 

0

q

qb

No Change

0

0

 

1

0

1

Reset

0

1

 

0

1

0

Set

0

1

 

1

-

-

Illegal

Truth Table 11: S R Flip Flop

VHDL File Name: sr_ff.vhd -- S R Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sr_ff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end sr_ff;

architecture Behavioral of sr_ff is signal temp : std_logic := '0';

begin

process(clk,rst)

begin

if(rst = '1') then temp <= '0';

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

elsif (clk'event and clk = '1') then if(s = '0' and r ='0') then temp <= temp; elsif(s = '0' and r ='1') then temp <= '0'; elsif(s = '1' and r ='0') then temp <= '1'; elsif(s = '1' and r ='1') then temp <= 'X'; end if; end if; end process; q <= temp; qb <= not temp; end Behavioral;

Verilog File Name: sr_ff.v //Async SR Flip Flop module sr_ff( sr , clk , reset , q ,qb ); input [1:0] sr; input clk, reset ; output q,qb; reg q,qb;

always @ ( posedge clk or posedge reset) if (reset) begin

q = 1'b0; qb = ~q;

end

else

begin

case (sr) 2'd0 : q = q; 2'd1 : q = 1'b0; 2'd2 : q = 1'b1; 2'd3 : q = 1'bX; endcase qb = ~q; end endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

12.

J K Flip Flop

j

k

rst

clk

D EPT ., CEC, B ANGALORE 12. J K Flip Flop j k rst clk inputs
D EPT ., CEC, B ANGALORE 12. J K Flip Flop j k rst clk inputs

inputs

EPT ., CEC, B ANGALORE 12. J K Flip Flop j k rst clk inputs JK

JK Flip Flop

JK Flip Flop

outputs

q12. J K Flip Flop j k rst clk inputs JK Flip Flop outputs qb Figure

qb12. J K Flip Flop j k rst clk inputs JK Flip Flop outputs q Figure

Figure 12: Block Diagram of JK Flip Flop

 

Inputs

   

Outputs

rst

clk

j

k

q

qb

Action

1

X

 

X

q

qb

No Change

0

0

 

0

q

qb

No Change

0

0

 

1

0

1

Reset

0

1

 

0

1

0

Set

0

1

 

1

q'

q'

Toggle

Truth Table 12: J K Flip Flop

VHDL File Name: jk_ff.vhd --JK Flip Flop library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jk_ff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC);

end jk_ff; architecture Behavioral of jk_ff is signal temp : std_logic := '0'; begin

process(clk,rst)

begin

if(rst = '1') then temp <= '0'; elsif(clk'event and clk = '1') then if(j = '0' and k ='0') then temp <= temp; elsif(j = '0' and k ='1') then temp <= '0'; elsif(j = '1' and k ='0') then temp <= '1'; elsif(j = '1' and k ='1') then temp <= not temp; end if; end if; end process; q <= temp; qb <= not temp; end Behavioral;

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

Verilog File Name: jk_ff.v //Async JK Flip Flop module jk_ff( jk , clk , reset , q ,qb ); input [1:0] jk; input clk, reset ; output q,qb; reg q,qb;

always @ ( posedge clk or posedge reset) if (reset) begin

q = 1'b0; qb = ~q;

end

else

begin

case (jk) 2'd0 : q = q; 2'd1 : q = 1'b0; 2'd2 : q = 1'b1; 2'd3 : q = ~q; endcase qb = ~q;

end

endmodule

4TH SEM, HDL MANUAL, 10ESL48

2012

E&C DEPT., CEC, BANGALORE

13.

D Flip Flop

D Flip Flop

D Flip Flop
d inputs rst
d
inputs
rst

clk

outputs

q13. D Flip Flop D Flip Flop d inputs rst clk outputs qb Figure 13: Block

13. D Flip Flop D Flip Flop d inputs rst clk outputs q qb Figure 13:

qb

Figure 13: Block Diagram of D Flip Flop

Inputs

   

Outputs

rst

clk

d

q

qb

Action