Final Ic & PDC Manual

Department of ECE IC & PDC LAB Manual
EXPERIMENT No: 1
LINEAR WAVE SHAPING

AIM:
1. To design high pass and low pass RC circuits for different time constants and verify
their responses for a square wave input of given frequency.
2. To find the % tilt of high pass RC circuit for long time constant.
3. To study the operation of high pass RC circuit as a differentiator and low pass
circuit as an integrator.
Apparatus:
1. CRO (Dual Channel) - 1 No.
2. Signal Generator – 1 No.
3. CDS Board - 1 No.
4. Decade capacitance box - 1 No.
5. Resistor (100 KΩ) - 1 No.
6. Connecting wires
CIRCUIT DIAGRAMS:
Fig 1.1 High Pass RC circuit Fig 1.2 Low Pass RC circuit
THEORY:
Resistors and Capacitors can be connected in series or parallel in various combinations.

The RC circuits can be configured in two ways as shown above
i) High Pass RC circuit ii) Low Pass RC circuit
High Pass RC circuit
The reactance of the capacitor depends upon the frequency of operation. At very high
frequencies, the reactance of the capacitor is zero. Hence the capacitor in fig.1.1 acts as short
circuit. As a result the entire input appears at the output.
At low frequencies, the reactance of the capacitor is infinite. So the capacitor acts as open
circuit. Hence no input reaches the output. Since the circuit allows only high frequencies,
therefore it is called as high pass RC circuit.
1 VARDHAMAN COLLEGE OF ENGINEERING

High – pass RC circuit as a differentiator:
In high pass RC circuit, if the time constant is very small in comparison with the time
required for the input signal to make an appreciable change, the circuit is called a
“Differentiator”. Under these circumstances the voltage drop across R will be very small in
comparison with the drop across C. Hence we may consider that the total input Vi appears across
C. So that the current is determined entirely by the capacitor. i = C dVi/dt.
The output signal voltage across R is Vo = RC dVi/dt.
i.e. The output is proportional to the differentiation of the input. Hence the high pass RC circuit
acts as a differentiator for RC << T
Low Pass RC circuit
The reactance of the capacitor depends upon the frequency of operation. At very high
frequencies, the reactance of the capacitor is zero. Hence the capacitor in fig.1.2 acts as short
circuit. As a result, the output will fall to zero.
At low frequencies, the reactance of the capacitor is infinite. So the capacitor acts as open
circuit. As a result the entire input appears at the output. Since the circuit allows only low
frequencies, therefore it is called as low pass RC circuit.
Low – pass RC circuit as an integrator:
In low pass circuit, if the time constant is very large in comparison with the time required
for the input signal to make an appreciable change, the circuit is called an “integrator”. Under
these circumstances the voltage drop across C will be very small in comparison to the drop across
R and we may consider that the total input Vi appears across R. ∴i = Vi/R
1 1
∴ The output signal across C is Vo =
c ∫ idt =
RC ∫
Vi dt
i.e. The output is proportional to the integral of the input. Hence the low pass RC circuit acts as a
integrator for RC >> T
Design:
RC high pass circuit:
i)Long time constant: RC > > T ;

Where RC is time constant and
T is time period of input signal.
Let RC = 10 T, Choose R = 100kΩ, f = 1kHz.
C = 10 / 103Χ 100Χ103 = 0.1µf
ii) Medium time constant: RC = T

C = T/R = 1/ 103Χ100Χ103 = 0.01µf
iii) Short time constant: RC < < T

RC = T/10 ⇒ C = T/10R = 1/ 10Χ103Χ100Χ103 = 0.001 µf.

RC low pass circuit: (Design procedure is same as RC high pass circuit)
i) Long time constant : RC > > T, C = 0.1µf

ii) Medium time constant : RC = T, C = 0.01µf.
iii) Short time constant : RC = T/10, C = 0.001µf
Expected output wave forms of High pass RC circuit for square wave input:
Consider the input at V1 during T1 and V11 during T2 then the voltages V1, V1 1 ,V2 , V2 1 are given
by following equations.
− T1
V11 =V1. e RC
V11 -V2=V
T2
−
V21 =V2. e RC 1
V1- V2 =V
V V
For a symmetrical square wave V11 = T
and V1=
−T
1+ e 2 RC
1+ e 2 RC
& because of symmetry V1= -V2 V1 =- V21

1
V1 − V11
The percentage tilt ‘P’ is defined by P= x100
V
2
a) RC = T
b) RC>>T
RC = 10T

C) RC<<T
RC= 0.1T
Expected output wave forms of Low pass RC circuit for square wave input:
Consider the input at V1 during T1 and V11 during T2 then the voltages V01, V02 during T1 and T2 is
given by following equations.
T1
−
V = V + (V - V ). e
1 1 RC
01 1 T
− 2
V = V 11 + (V - V 11 ). e RC
02 2
V T
For a symmetrical square wave V2 = tanhx and V1 = -V2 where x=
2 4RC
a) RC=T
b) RC >>T

C) RC<<T
PROCEDURE:
1. Connect the circuit as shown in figure (LPF / HPF)

2. Apply the Square wave input to this circuit (Vi = 10 VP-P, f = 1KHz)
3. Observe the output waveform for (a) RC = T, (b) RC>>T, (c) RC>>T
4. Verify the values with theoretical calculations.
OBSERVATIONS:
a) Theoretical
High pass RC circuit:

Low pass RC circuit:
Time O/P Voltage Time O/P Voltage
constant levels in Volts constant in levels in Volts
S.No. S.No.
in m.sec m.sec
V1
V1
V11
1. RC=T 1 RC=T
V2
V2
V21
V1
V1
V11
2
RC>>T 2 RC>>T
V2
V2
V21
V1
V1
V11
3 RC<<T 3 RC<<T
V2
V2
V21

b) Practical
High pass RC circuit
Output Signal Output Signal

Time constant in Voltage Voltage levels % Tilt
m.sec levels(Theoretical) (Practical) in
in Volts Volts
Short time constant
(RC<<T)
Medium time constant

(RC=T)
Long time constant
(RC>>T)
Low pass RC circuit:
Output Signal Voltage

Time constant in Output Signal Voltage
levels(Theoretical) in
m.sec levels(Practical) in Volts
Volts
Short time constant

(RC<<T)
Medium time constant

(RC=T)
Long time constant

(RC>>T)
REVIEW QUESTIONS:
1. When HP-RC circuit is used as Differentiator?
2. Draw the responses of HPF to step, pulse, ramp inputs?
3. Draw the responses of LPF to step, pulse, ramp inputs?
4. Define % tilt and rise time?
5. When LP-RC circuit is used as integrator?
6. Why noise immunity is more in integrator than differentiator?
7. Why HPF blocks the DC signal?
8. What is meant by linear wave shaping?
9. Define time constant?
10. Differences between High pass and Low pass RC circuits?
11. What is the working principle of high pass and low pass RC circuits for non sinusoidal signal
inputs.
12. Define % tilt, time constant, cut-off frequencies, rise time and delay times of RC High pass &
Low pass Circuits.

WORKSPACE

WORKSPACE

EXPERIMENT NO: 2
NON LINEAR WAVE SHAPING-CLIPPERS

AIM:
To study the various clipper circuits and to plot the output waveforms for a sinusoidal
input signal.
APPARATUS:
2. Signal Generator – 1 No.
3. CDS - 1 No.
4. Diode (1N4007) - 2 No.
5. Resistor (2.2 KΩ) - 1 No.
6. D.C Power Supply (dual) - 1 No.
7. Connecting wires
THEORY:
The process where by the form of a sinusoidal signals are going to be altered by
transmitting through a non-linear network is called non-linear wave shaping. Non-linear elements
in combination with resistors can function as clipper circuit.
Clipping circuits are used to select transmission of that part of an arbitrary wave form
which lies above or below some particular reference voltage level. Clipping circuits are also
referred to as Limiters, Amplitude selectors or Slicers.
Clipping circuits are constructed using a series combination of resistor, diode or transistor
and reference voltage. Clipping circuits are classified based on the position of diode as
i) Series clipper ii) Shunt clipper
PROCEDURE:
1. Connect the circuit as shown in fig.

2. In each case apply 10 VP-P, 1 KHz Sine wave I/P using a signal generator.
3. O/P is taken across the load RL.
4. Observe the O/P waveform on the CRO and compare with I/P waveform.
5. Sketch I/P as well as O/P waveforms and mark the numerical values.
6. Note the changes in the O/P due to variations in the reference voltage VR = 2V, 3V.
7. Obtain the transfer characteristics of Fig.1, by keeping CRO in X-Y mode.
8. Repeat the above steps for all the circuit.

CIRCUIT DIAGRAMS:
Fig 2.1 Negative clipper with zero reference (Series clipper)
Fig 2.2 Positive clipper with zero reference (Series clipper)
Fig 2.3 Negative clipper with zero reference (Shunt clipper)
Fig 2.4 Positive clipper with zero reference (Shunt clipper)

Fig 2.5 Positive clipper with positive reference (Series clipper)
Fig2.6 Positive clipper with positive reference (Shunt clipper)
Fig2.7 Negative clipper with positive reference (Series clipper)
Fig2.8 Negative clipper with positive reference (Shunt clipper)

Fig.2.9 clipping at two independent levels.
TRANSFER CHARACTERISTIC CURVES:


Observations:
Sl No. Type of Clipper Reference Theoretical Practical

Voltage Clipping Voltage Clipping Voltage
levels levels
0V
1 Series Positive Clipper 2V

-2V
0V
2 Series Negative Clipper 2V

-2V
0V
3 Shunt Positive Clipper 2V

-2V
0V
4 Shunt Negative Clipper 2V

-2V
5 Two level clipper

RESULT:
The different types of clippers circuits are studied and observed the response for various
combinations of VR and clipping diodes.
REVIEW QUESTIONS:
1. Define non linear wave shaping?
2. Define clipping circuit?
3. What is piecewise linear mode of a diode?
4. What are the different types of clippers?
5. Which kind of a clipper is called a slicer circuit?
6. What are the disadvantages of the shunt clipper?
7. What are the disadvantages of the series clipper?
8. What considerations are taken into account while designing clipping circuits?

WORKSPACE

EXPERIMENT NO: 3
NON LINEAR WAVE SHAPING-CLAMPERS

AIM:
To study the various clamping circuits and to plot the output waveforms for a sinusoidal input of
given peak amplitude. (Choose f=1 kHz, Vp-p =10v)
APPARATUS:

2. Signal Generator - 1 No.
3. CDS - 1 No.
4. Diode (1N4007) - 1 No.
5. Resistor (100 KΩ) - 1 No.
6. Capacitor (0.1µf) - 1 No.
7. D.C Power Supply (dual) - 1 No.
8. Connecting wires
THEORY:
The process where by the form of a sinusoidal signals are going to be altered by
transmitting through a non-linear network is called non-linear wave shaping. Non-linear elements
in combination with resistors and capacitors can function as clamping circuit.
A Clamping circuit is one that takes an input waveform and provides an output i.e a
faithful replica of its shape, but has one edge clamped to the voltage reference point. The
clamping circuit introduces the d.c component at the output side, for this reason the clamping
circuits are referred to as d.c restorer or d.c reinserter.
Clamping circuits are classified as two types.
i) Negative Clampers ii) Positive Clampers
PROCEDURE:
1. Connect the circuit as shown in fig..
2. Apply a Sine wave of 10VP-P, 1 KHz at the input terminals with the help of Signal
Generator.
3. Observe the I/P & O/P waveforms of CRO and plot the waveforms and mark the values
with VR = 2 V, 3V
4. O/P is taken across the load RL.
5. Repeat the above steps for all clamping circuits as shown.
6. Waveforms are drawn assuming diode is ideal.

CIRCUIT DIAGRAMS:
Fig.3.1 Negative clamping with zero reference voltage
Fig.3.2 positive clamping with zero reference voltage
Fig.3.3 Negative clamping with Negative reference voltage
Fig.3.4 positive clamping positive reference voltage
Fig.3.5 Negative clamping with Positive reference voltage

Fig.3.6 Positive clamping with Negative reference voltage
OBSERVATIONS:
Theoretical Practical
Reference Clamping Clamping
Sl No. Type of Clamper
Voltage reference reference
Voltage level Voltage level
0V
1 Positive Clamper 2V
-2V
0V
2 Negative Clamper 2V
-2V
RESULT:
The different types of clamping circuits are studied and observed the response for various
combinations of VR, capacitors and diodes.
REVIEW QUESTIONS:
1. What are the applications of clamping circuits?

2. What is the synchronized clamping?
3. Why clamper is called as a dc inserter?
4. What is clamping circuit theorem. How the modified clamping circuit theorem does
differs from this?
5. Differentiate –ve clamping circuit from +ve clamping circuits in the above circuits?
6. Describe the charging and discharging of a capacitor in each circuit?
7. What is the function of capacitor?
8. What are the effects of diode characteristics on the output of the Clamper?

WORKSPACE

EXPERIMENT NO: 4
STUDY OF LOGIC GATES & SOME APPLICATIONS

AIM:
1. Study of logic gates using IC’s.
2. Realization of basic gates using NAND & NOR gates (Universal gates).
3. Implementation of Half Adder and Full Adder using logic gate.
APPARATUS:
1. IC 7400, IC 7404, IC 7408, IC 7432, IC 7486 - 1 No. each
2. CDS - 1 No.
3. Connecting patch chords
THEORY:
A logic gate performs a logical operation on one or more logic inputs and produces a
single logic output. The logic normally performed is Boolean logic and is most commonly found in
digital circuits
The different types of logic gates are:
i) NOT gate ii) OR gate iii) AND gate iv) EX-OR gate v) NAND gate vi) NOR gate
Inverter or NOT gate:
The inverter is a logic gate which has only one input & one output. In inverter a low input
produces a high output and a high input produces a low output and vice-versa.
Logic equation is: Y= A Digital IC for NOT: IC 7404.
AND gate:
AND gate is a logic gate Which can have two or more inputs. But there is only one output. The
output of AND gate is high only if all inputs are high. Even if one input is low, the output will be
low.
Logic equation is: Y= A B Digital IC for AND: IC 7408.
OR gate:
An OR gate is a logic gate Which can have two or more inputs and a single output. The output of
an OR gate is high if any of the input’s or all inputs are high. The output is low only if all the
inputs are low.
Logic equation is: Y= A + B Digital IC for OR: IC 7432.
NAND gate:
NAND gate is a combination of AND & NOT gates. Thus NAND gate is the inverse of AND gate.
The output is low when all inputs are high. The output is high for all the remaining combinations.
Logic equation is: Y= AB Digital IC for NAND: IC 7400.

NOR gate:
NOR gate is a combination of OR & NOT gates. Thus NOR gate is the inverse of OR gate. When all
or either of the inputs are high output is low. The output of NOR gate is high only when all inputs
are low.
Logic equation is: Y= A + B Digital IC for NOR: IC 7402.

EX-OR gate:
In EX-OR gate if either of the inputs is high, output will be high. If both the inputs are high
output will be low. If both inputs are low then also output will be low.
Logic equation is: Y= A.B + B. A =A ⊕ B Digital IC for EX-OR: IC 7486.
Fig 5.1 Logic gates symbols and truth tables.

CIRCUIT DIAGRAMS:
Fig 5.2 NOT gate (IC 7404) Fig 5.3 AND gate (IC 7408)
Fig 5.4 OR gate (IC 7432) Fig 5.5 NAND gate (IC 7400)
Fig 5.6 NOR gate (IC 7402) Fig 5.7 EX-OR gate (IC 7486)

Realization of basic gates using NAND gates:
Realization of basic gates using NOR gates:
OR GATE

Implementation of Half Adder and Full Adder using logic gates:

Half Adder
Circuit Diagram Truth Table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Full Adder
Circuit Diagram Truth Table
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
PROCEDURE:
1. Connect the NOT gate using digital IC’s as shown in the figures 5.2.
2. Use +5V for logic 1 and 0V for logic 0.
3. Feed the logic signals 0 or 1 from the logic input switches at the inputs A & B.
4. Monitor the output using LED indicators and verify its truth table.
5. Repeat step 1 to 4 for all the remaining gates.
RESULT:
Truth tables of all logic gates are verified.
REVIEW QUESTIONS:
1. Realize the EX – OR gates using minimum number of NAND gates.
2. Give the truth table for EX-NOR (EX-OR+NOT) and realize using NAND gates.
3. Explain the operation of NAND gate when realized using discrete components.
4. What are the logic low and High levels of TTL IC’s and CMOS IC’s.
5. Which logic family is called fastest and which logic family is called low power dissipated.
6. Explain the operation of OR, NOR gates when realized using discrete Components
7. Why the transistor operates as NOT gate.
8. In what a region does the transistor is operated such that it behaves like a switch.
WORKSPACE

EXPERIMENT NO: 5
ASTABLE MULTIVIBRATOR USING BIPOLAR JUNCTION TRANSISTORS

AIM:
1. To study the operation and observe the wave forms of Astable Multivibrator.
2. To Design an Astable Multivibrator to generate a square wave of 1KHz frequency using
Transistor.
APPARATUS:
2. Function Generator – 1 No.
3. CDS - 1 No.
4. Resistor (1 KΩ, 7.2 KΩ) - 1 No. each
5. Capacitors (0.1µF) - 2 No.’s
6. Transistor (BC 107) - 2 No.’s
7. Regulated D.C Power Supply (dual) - 1 No.
8. Connecting wires
CIRCUIT DIAGRAM:
Fig. 1.1 Astable Multivibrator

THEORY:
The Astable circuit has two quasi-stable states. Without external triggering signal the
astable configuration will make successive transitions from one quasi-stable state to the other.
The astable circuit is an oscillator. It is also called as free running multivibrator and is used to
generate “Square Wave”. Since it does not require triggering signal, fast switching is possible.

Operation:
When the power is applied, due to some importance in the circuit, the transistor Q2
conducts more than Q1 i.e. current flowing through transistor Q2 is more than the current flowing
in transistor Q1. The voltage VC2 drops. This drop is coupled by the capacitor C1 to the base by Q1
there by reducing its forward base-emitter voltage and causing Q1 to conduct less. As the current
through Q1 decreases, VC1 rises. This rise is coupled by the capacitor C2 to the base of Q2. There
by increasing its base- emitter forward bias. This Q2 conducts more and more and Q1 conducts
less and less, each action reinforcing the other. Ultimately Q2 gets saturated and becomes fully
ON and Q1 becomes OFF. During this time C1 has been charging towards VCC exponentially with a
time constant T1 = R1C1. The polarity of C1 should be such that it should supply voltage to the
base of Q1. When C1 gains sufficient voltage, it drives Q1 ON. Then VC1 decreases and makes Q2
OFF. VC2 increases and makes Q1 fully saturated. During this time C2 has been charging through
VCC, R2, C2 and Q1 with a time constant T2 = R2C2. The polarity of C2 should be such that it should
supply voltage to the base of Q2. When C2 gains sufficient voltage, it drives Q2 On, and the
process repeats.
Design Procedure:
The period T is given by

T = T1 + T2 = 0.69 (R1C1 + R2C2)
For symmetrical circuit, with R1 = R 2 = R & C1 = C2 = C
T = 1.38 RC
Let VCC = 12V; hfe = 51 (for BC107), VBESat = 0.7V; VCESat = 0.3V
Let C = 0.1µF & T=1msec.
T = 1.38 RC
10-3 = 1.38 x R ×0.1 ×10-6
R = 7.24 KΩ
Choose ICmax = 10mA,
VCC − VCESAT 12 − 0.3

RC = = = 1.17 KΩ
I C max 10 × 10 − 3
PROCEDURE:
1. Make then connections as per the circuit diagram.
2. Observe the Base Voltage and Collector Voltages of Q1 & Q2 on CRO in DC mode and
measure the frequency (f = 1/T).
3. Trace the waveforms at collector and base as each transistor with the help of dual trace
CRO and plot the waveforms.
4. Verify the practical output frequency with theoretical values f = 1/T, where T = 1.38 RC secs

EXPECTED WAVEFORMS:
RESULT:
An Astable Multivibrator is designed; the waveforms are observed and verified the results
theoretically.
REVIEW QUESTIONS:
1. What are the other names of Astable Multivibrator?
2. Define quasi stable state?
3. Is it possible to change time period of the waveform with out changing R & C?
4. Collector waveforms are observed with rounded edges. Explain?
5. Explain charging and discharging of capacitors in an Astable Multivibrator?
6. How can an Astable Multivibrator be used as VCO?
7. Why do you get overshoots in the Base waveforms?
8. What are the applications of Astable Multivibrator?
9. How can Astable Multivibrator be used as a voltage to frequency converter?
10. What is the formula for frequency of oscillations?

WORKSPACE

EXPERIMENT NO: 6
MONOSTABLE MULTIVIBRATOR USING BIPOLAR JUNCTION TRANSISTORS

AIM:
1. To study the operation and observe the wave forms of Monostable Multivibrator.
2. To Design a Monostable Multivibrator for the pulse width of 0.3msec.
APPARATUS:
3. CDS - 1 No.
4. Resistor (1 KΩ, 8.2 KΩ) - 1 No. each
5. Transistor (BC 107) - 2 No.
7. Connecting wires
CIRCUIT DIAGRAM:
Fig. 2.1 Monostable Multivibrator
THEORY:
The Monostable circuit has one permanently stable and one quasi-stable state. In the monostable
configuration, a triggering signal is required to induce a transition from the stable state to the
quasi-stable state. The circuit remains in its quasi-stable for a time equal to RC time constant of
the circuit. It returns from the quasi-stable state to its stable state without any external
triggering pulse. It is also called as one-shot a single cycle, a single step circuit or a univibrator.

Operation:
Assume initially transistor Q2 is in saturation as it gets base bias from VCC through R. coupling
from Q2 collector to Q1 base ensures that Q1 is in cutoff. If an appropriate negative trigger pulse
applied at collector of Q 1 (VC1) induces a transition in Q2, then Q2 goes to cutoff. The output at Q2
goes high. This high output when coupled to Q1 base, turns it ON. The Q1 collector voltage falls
by IC1 RC1 and Q2 base voltage falls by the same amount, as voltage across a capacitor ‘c’ cannot
change instantaneously.
The moment, a –ve trigger is applied VC1, Q2 goes to cutoff and Q1 starts conducting.
There is a path for capacitor C to charge from VCC through R and the conducting transistor Q1.
The polarity should be such that Q2 base potential rises. The moment, it exceeds Q2 base cut-in
voltage, it turns ON Q2 which due to coupling through R1 from collector of Q2 to base of Q1, turns
Q1 OFF. Now we are back to the original state i.e. Q2 On and Q1 OFF. Whenever trigger the circuit
into the other state, it cannot stay there permanently and it returns back after a time period
decided by R and C.
Pulse width is given as T = 0.69RCsec.
Design Procedure:
To design a monostable multivibrator for the Pulse width of 0.3mSec.
Choose ICmax = 15mA, VCC = 15V, VBB = 15V, R1 = 10KΩ.
T = 0.69 RC
Choose C = 10nf
0.3 x 10-3Sec = 0.69 x R x 10 x 10-9
R = 43.47 KΩ
RC = = ≈ 1 KΩ
I C max 15 × 10 − 3
Minimum requirement of | VB1| ≤ 0.1
for more margin, given VB1 = -1.185
− V BB R1 VCEsat R 2
VB1 = +
R1 + R 2 R1 + R 2
− 15R1 + 0.2 R 2
-1.18 =
R1 + R 2
given R1 = 10KΩ and R2 = 100KΩ
PROCEDURE:
1. Make then connections as per the circuit diagram.
2. Select the triggering pulse such that the frequency is less than 1/T
3. Apply the triggering input to the circuit and to the CRO’s channel 1. Connect the CRO channel-
2 to the collector and base of the TransisterQ1&Q2..

4. Adjust the triggering pulse frequency to get stable pulse on the CRO and now measure the
pulse width and verify with the theoretical value.
5. Obtain waveforms at different points like VB1, VB2, VC1 & VC2.
EXPECTED WAVEFORMS:
RESULT:
Monostable Multivibrator is designed; the waveforms are observed and verified the results
theoretically.
REVIEW QUESTIONS:
1. What are applications of Monostable Multivibrator?
2. Why a Monostable Multivibrator is called a gating circuit?
3. Explain the waveform of VB1?
4. Describe the operation of the capacitor C3 in the circuit?
5. Why is the time period T also called Delay time?
6. Justify, Why Monostable Multivibrator is called one-shot circuit?
7. Why is the –ve voltage given at the base of Q1 transistor?
8. What is the no of quasi & stable states of Monostable Multivibrator?
9. What is meant by quasi stable state?
10. What is the function of commutating capacitors?

WORKSPACE

EXPERIMENT NO: 7
BISTABLE MULTIVIBRATOR USING BIPOLAR JUNCTION TRANSISTORS

AIM:
To Design a Bistable Multivibrator & observe its response.
APPARATUS:
3. CDS - 1 No.
5. Resistor (1 KΩ, 8.2 KΩ) - 1 No.
6 Capacitors
7. Transistor (BC 107) - 2 No.
8. Diodes
10. Connecting wires
CIRCUIT DIAGRAM:
Fig. 3.1 Bistable Multivibrator

THEORY:
A Bistable circuit is one which can exist indefinitely in either of two stable states and which
can be induced to make an abrupt transition from one state to the other by means of external
excitation. The Bistable circuit is also called as Bistable multivibrator, Eccles Jordon circuit,
Trigger circuit, Scale-of-2 toggle circuit, Flip-Flop & Binary.
A Bistable Multivibrator is used in a many digital operations such as counting and the
storing of binary information. It is also used in the generation and processing of pulse-type
waveform. They can be used to control digital circuits and as frequency dividers.
There are two outputs available which are complements of one another. i.e. when one
output is high the other is low and vice versa .
Operation:
When VCC is applied, one transistor will start conducting slightly more than that of the other,
because of some differences in the characteristics of a transistor. Let Q2 be ON and Q1 be OFF.
When Q2 is ON, The potential at the collector of Q2 decreases, which in turn will decrease the
potential at the base of Q1 due to potential divider action of R1 and R2. The potential at the
collector of Q1 increases which inturn further increases the base to emitter voltage at the base of
Q2. The voltage at the collector of Q2 further decreases, which inturn further reduces the voltage
at the base of Q1. This action will continue till Q2 becomes fully saturated and Q1 becomes fully
cutoff.
Thus the stable state of binary is such that one device remains in cut-off and other device
remains at saturation. It will be in that state until the triggering pulse is applied to it. It has two
stable states. For every transition of states triggering is required. At a time only one device will
be conducting.
NEED OF COMMUTATING CAPACITORS (SPEED UP CAPACITORS):
It is desired that the transition should take place as soon as the trigger pulse is applied
but such is not the case.
When transistor is in active region it stores charge in its base and when it is in the
saturation region it stores even none charge. Hence transistor cannot come out of saturation to
cut-off. Until all such charges are removed. The interval during which conduction transfer one
transistor to other is called as the transition
Design Procedure:

RC = = ≈ 1 KΩ
I C max 15 × 10 − 3
− V BB R1 VCEsat R 2
VB1 = +
R1 + R 2 R1 + R 2
− 15R1 + 0.2 R 2
-1.2 = given R1 = 10K
R1 + R 2
R2 = 100K
R1 + R2 (10 + 100) ×103

fmax = = =55 KHz.
2CR1 R2 2 × 0.3 ×10−6 ×10 × 100 ×106

PROCEDURE:
1. Make the connections as per the circuit diagram.
2. Apply trigger pulse of 1 KHz 5v (p-p) from function generator.
3. Observe the output waveforms at any collector point and measure the voltage levels.
4. Trace the waveform at collector and base of each transistor with the help of dual trace
CRO note the time relation of waveforms.
5. Obtain waveforms at different points like VB1, VB2, VC1 & VC2.
EXPECTED WAVEFORMS:
RESULT :
Bistable Multivibrator is designed; and the waveforms are observed.
REVIEW QUESTIONS :
1. What are the applications of a Bitable Multivibrator?
2. Describe the operation of commutating capacitors?
3. Why is a Binary also called a flip-flop?
4. Mention the name of different kinds of triggering used in the circuit shown?
5. What are the disadvantages of direct coupled Binary?
6. How many types of unsymmetrical triggering are there?
7. What are catching diodes?
8. Which triggering is used in binary counting circuits?

WORKSPACE

EXPERIMENT NO: 8
SCHMITT TRIGGER USING BIPOLAR JUNCTION TRANSISTORS
AIM :
1. To design the circuit of Schmitt trigger with UTP=2.2V and LTP=1V.
2. To obtain square wave from sine wave.
3. To obtain UTP and LTP values practically
APPARATUS:
2. Function Generator - 1 No.
3. CDS - 1 No.
4. Resistor (1 KΩ, 4 KΩ, 220 Ω) - 1 No. each
5. Resistor (1.5 KΩ) - 2 No.’s
6. Capacitors (0.1 µF) - 1 No.
7. Transistor (2N2222) - 2 No.
8. Regulated D.C. Power Supply (dual) - 1 No.
9. Connecting wires
CIRCUIT DIAGRAM:
Fig. 4.1 Schmitt trigger

THEORY:
In digital circuits fast waveforms are required i.e, the circuit remain in the active region
for a very short time (of the order of nano seconds) to eliminate the effects of noise or undesired
parasitic oscillations causing malfunctions of the circuit. Also if the rise time of the input
waveform is long, it requires a large coupling capacitor. Therefore circuits which can convert a
slow changing waveform (long rise time) in to a fast changing waveform (small rise time) are
required. The circuit which performs this operation is known as “Schmitt Trigger”.
In a Schmitt trigger circuit the output is in one of the two levels namely low or high.
When the output voltage is raising the levels of the output changes. When the output passes
through a specified voltage V1 known as Upper trigger level, similarly when a falling output
voltage passes through a voltage V2 known as lower triggering level. The level of the output
changes V1 is always greater than V2.The differences of these two voltages is known as
“Hysteresis”.
Design Procedure:
The voltage required to drive the transistor Q1 from OFF to ON is called upper trigger
point.
UTP = V1 = V1 – 0.1
Vcc R2
Where V1 = V' =
R1 + R2 + Rc1
The voltage required to drive the transistor Q1 from ON to OFF is called lower trigger
point.
Re
LTP = V2 = VBE1(active)+ (V1- Vγ )
2
aRc + Re
th
Rc1 ( R1 + R2 ) R2
Rc = a=
th
Where ;
R1 + R2 + Rc1 R1 + R2
Choose 2N2222 transistors with hfe = 200
Let Vcc = 12 V, R1=2.2 KΩ and R2=1.5 KΩ
Since UTP = V1 – 0.1 2.2 = V1 – 0.1 V1=2.3 volts

But V1 = 12 ×1.5 Rc1 = 4.12 K Ω ≈ 4 K Ω
2.2 + 1.5 + Rc1
4 × 103 (2.2 + 1.5)
Rc th = = 1.92 K Ω
2.2 + 1.5 + 4
R2 1.5
a= = = 0.4
R1 + R2 2.2 + 1.5
Let VBE ( active ) = 0.7V ; Vϒ = 0.6V
1 2
Re
LTP = V2 = VBE1(active)+ (V1- Vγ )
2
aRc + Re
th
1 = 0.7+(2.3-0.6) Re
0.4 × 1.92 + Re
Re = 165 Ω ≈ 220 Ω
VE = V1 - VBE2
= 2.3 - 0.7 = 1.6 volts

VE 1.6
I B2 = = = 0.036mA
RE (1 + h fe ) 220(1 + 200)
I C2 = h fe I B2 = 7.24mA
When Vin < V2, output = 1 volt
Vcc − output 12 − 1
= Rc2 = Rc2 = 1.5 K Ω
I c2 7.24mA
PROCEDURE:
1. Connect the circuit diagram as shown in fig 4.1.
2. Apply a sine wave input of 10 Vp-p amplitude and 1 KHz frequency to the circuit
3. Observe the output voltage on CRO.
4. Obtain the output voltage at which LOW to HIGH transition occurs and measure the
corresponding input voltage. This input voltage is called UTP.
5. Now, Obtain the output voltage at which HIGH to LOW transition occurs and measure
the corresponding input voltage. This input voltage is called LTP.
6. Compare these practical values with theoretical values.
EXPECTED WAVEFORMS:
Fig.4.2 input & output waveforms of Schmitt Trigger

RESULT:
Schmitt trigger circuit with the given values is designed; and the response is observed.
REVIEW QUESTIONS:
1. What are the applications of Schmitt Trigger?
2. Define hysteresis action?

3. Why is Schmitt Trigger called a squaring circuit?
4. What is UTP & LTP?
6. What is the difference between a Binary and Schmitt Trigger?
WORKSPACE

EXPERIMENT NO: 9
APPLICATIONS OF OPERATIONAL AMPLIFIER (IC 741)

AIM: To design and study the operation of IC 741 Operational amplifier as
a) Adder
b) Subtractor
c) Comparator
APPARATUS REQUIRED:
1. CDS Board with in-built power supply / Bread Board.
2. Function Generator
3. Cathode Ray Oscilloscope.
4. Digital Multimeter.
5. Regulated Power Supply (Dual Channel).
6. Connecting Wires.
COMPONENTS REQUIRED:
1. IC741 :1No
2. Decade Resistance Box (DRB) :1No
3. Resistor ------1KΩ :4No
10KΩ :3No
100KΩ :1No
CIRCUIT DIAGRAMS:
a) ADDER
Fig.1

b) SUBTRACTOR
Fig.2
THEORY:
Adder:
A typical summing amplifier (Inverting Adder) with three inputs Va ,Vb & Vc applied at the
inverting terminal of IC741 is shown in fig(1). The following analysis is carried out assuming that
the Op-Amp is an ideal one, that is AOL = ∞, Ri = ∞ & R0=0; since the input bias current is
assumed to be zero, there is no voltage drop across the resistor Rcomp and hence the non
inverting input terminal is at ground potential.
The voltage at node ‘A’ is zero as the non- inverting input terminal is grounded. The
nodal equation by KCL at node ‘a’ is given as
Va Vb Vc Vo
+ + + =0
Ra Rb Rc Rf
 R   R   R  
Vo =− f Va + f Vb + f Vc 
 R 
 a   Rb   Rc  
Case (1):- Ra=Rb=Rc=Rf
V0 = - (Va + Vb+ Vc)
Case (2):- Ra=Rb=Rc=3Rf
V0 = - (Va + Vb+ Vc)/3
Subtractor
A typical subtractor with two inputs Va & Vb applied at the non-inverting terminal & Inverting
terminal of IC741 respectively is shown in fig(2). The following analysis is carried out assuming
that the Op-Amp is an ideal one, that is AOL = ∞, Ri = ∞ & R0=0;
Let Ra = Rb= Rf = R, V o= V a - V b
PROCEDURE:
Part-I
Adder
1. Connect the Adder circuit as shown in fig.1 with Ra = Rb = Rc = Rf = 1KΩ, RL =100KΩ and R
= 250Ω on the CDS board.
2. Switch ‘ON’ the power supply and apply + 15V to pin no.7 and -15V to pin no.4 of the IC741.
3. Apply the input voltages from the regulated supplies to the corresponding inputs at the
inverting input terminal of IC741 (pin no.2).
3. Connect the Digital Multimeter at the Out put terminals (pin no.6), and note down the output
voltage and verify with theoretical values.
4. Repeat the above steps for different input voltages.
Subtractor
1. Connect the subtractor circuit as shown in fig.2 with Ra = Rb = Rf = R = 1KΩ and RL =100KΩ
on the CDS board.
3. Apply the input voltages from the regulated supplies to the corresponding inputs at the
inverting & non-inverting input terminals of IC741 (pin no.2 & 3 respectively).
3. Connect the Digital Multimeter at the Out put terminals (pin no.6), and note down the output
voltage and verify with theoretical values.
4. Repeat the above steps for different input voltages.
RESULT:
Adder and Subtractor are designed using 741 Op – Amp and the experimental results were
compared with the theoretical values.
Applied input signal is compared with reference voltages in a comparator using 741 Op – Amp
and the corresponding waveforms were noted.
REVIEW QUESTIONS:
1. Draw an Op- amp circuit whose output VO = V1+ V2 – V3 –V4.
3. Show that the o/p of an n-input inverting adder is V0 = - (Va +Vb + … + Vn)
4. Draw the circuit of non-inverting adder with 3 inputs and find the o/p Voltage V0
5. What is a mixed adder and how do you construct it using IC 741 Op- amp.
6. Design a mixed adder for V0=V1+2V2-V3-5V4.
7. Design a subtractor for V0 = Va - 5Vb -2Vc
8. Mention the other mathematical operations obtained using Op-Amps.
9. Why are the diodes D1 & D2 used in the circuit?
10. What is the difference between a basic comparator and the Schmitt trigger?
11. List the important characteristics of the comparator.
12. List out different applications of comparator.
13. What is the difference between Inverting and Non – Inverting Comparator?
14. Show the outputs for Inverting comparator with negative bias and non-inverting comparator
with positive bias.
15. Show the output waveform for Inverting comparator with positive bias of 2V and supply
voltage ±12V.
16. Briefly explain the features of comparator IC LM311.
17. Calculate VO in the circuit shown below for V1 = 5V, V2 = 2V.

WORKSPACE

WORKSPACE

EXPERIMENT No: 10
INTEGRATOR AND DIFFERENTIATOR

AIM: To design, construct and verify the response of
a) Integrator using Op-amp IC741 for sine and square wave inputs at 1 KHz frequency.
b) Differentiator using Op-amp IC741 for sine and square wave inputs at 1 KHz frequency.
APPARATUS REQUIRED:
1. Bread Board / CDS Board.
2. Function Generator (1MHz).
3. Cathode Ray Oscilloscope (20MHz/30 MHz)
1. IC741 :1No
2. Resistor ----- 10KΩ :2No
3. 100KΩ POT/ Decade Resistance Box (DRB) :1No
4. 10KΩ POT/ Decade Resistance Box (DRB) :1No
5. Capacitor ---- 0.1µF :2No
CIRCUIT DIAGRAMS:
INTEGRATOR:
Fig.1

DIFFERENTIATOR:
Fig.2
THEORY:
The integrator
A circuit in which the output voltage waveform is the integration of the input is called integrator.
1. The equation (1) indicates that the output voltage is directly proportional to the negative
integral of the input voltage and inversely proportional to the time constant R1CF. For Example if
the input is a sine wave, the output will be a cosine wave or if the input is a square wave, the
output will be a triangular wave.
2. When the input signal frequency is ZERO, the integrator works as an open – loop amplifier.
This is because of the capacitor CF acts as an open circuit (XCF =1/ωCF = infinite for f=0).
3. Therefore the ideal integrator becomes unstable & suffers with low frequency noise. To
overcome this problem RF is connected across the feed back capacitor CF. Thus RF limits the low-
frequency gain and hence minimizes the variations in the output voltage.
3. Frequency fb at which the gain of the integrator is 0 dB, is given by
fb =1/2∏R1CF -----------
(2)
4. Both the stability and the low – frequency roll-off problems can be corrected by the addition of
a resistors RF in the feed back path. The frequency response of practical integrator is as shown in
fig (3). In this ‘f’ is relative operating frequency and for f < fa gain of the integrator is constant
and is equal to RF / R1. However after fa the gain decreases at a rate of 20dB/decade. In other
words, between fa and fb the circuit acts as an integrator. The gain-Limiting frequency fa is given
by

fa =1/2∏RFCF ----------
(3)
NOTE: The input signal will be integrated properly if the time period T of the input signal is
greater than or equal to RFCF.
The Differentiator
The differentiator circuit performs the mathematical operation of differentiation. That is the
output waveform is the derivative of the input waveform. Therefore
VO = RFC1 dVin / dt -------------- (4)
1. The above equation (4) indicates that the output voltage is directly proportional to the
derivative of the input voltage and also proportional to the time constant RFC1.
For Example if the input is a sine wave, the output will be a cosine wave or if the input is a
square wave, the output will be spikes.
2. The reactance of the circuit increases with increase in frequency at a rate of 20dB/ decade.
This makes the circuit unstable. In other words the gain of an ideal differentiator circuit is direct
dependent on input signal frequency. Therefore at high frequencies (f=∞), the gain of the circuit
becomes infinite making the system unstable.
3. The input impedance XC1 decreases with increase in frequency, which makes the circuit very
susceptible to high frequency noise.
4. The frequency response of the basic differentiator is shown in fig.4 In this fig fa is the
frequency at which the gain is 0 dB.
fa =1/2∏RFC1 -----------
(5)
5. Both the stability and the high – frequency noise problem can be corrected by the addition of
two components R1 and CF as shown in fig.2.The frequency response of which is shown in fig.4.
From f to fa the gain decreases at 40dB/decade.This 40 dB/decade change in gain is caused by
the R1C1 and RFCF combinations. The gain limiting frequency fb is given by
fb =1/2∏R1C1 ----------
(6) Where R1 C1 = RF CF.
R1C1 and RFCF help to reduce significantly the effect of high frequency input, amplifier noise, and
offsets. Above all, it makes the circuit more stable by preventing the increase in gain with
frequency. In general, the value of f1, and in turn R1C1 and RFCF should be selected such that fa
<fb < fc, Where fc is the unity gain- bandwidth of an open-loop Op-Amp.
NOTE: The input signal will be differentiated properly if the time period T of the input signal is
greater than or equal to RF C1.

PROCEDURE:
Integrator
1. Connect the circuit as shown in fig.1 on the breadboard.
3. Apply a sine wave input signal of 2V peak-to-peak amplitude at 1 KHz frequency from the
function generator (at pin no.2 of the IC741).
4. Connect the C.R.O at (pin no.6) the output terminals.
5. Observe and plot the input & output voltage waveforms.
6. Measure the output voltage (Vo) from the experimental results.
7. Calculate the output voltage of the inverting Amplifier theoretically using the formula
8. Apply a square wave input signal of 2V P-P amplitude at 1 KHz frequency from the function
generator and repeat the above steps.
9. Compare the experimental results with the theoretical values.
Differentiator
6. Measure the output voltage (Vo) from the experimental results.
7. Calculate the output voltage of the inverting Amplifier theoretically using the formula VO =
RFC1 dVin / dt
8. Apply a square wave input signal of 2V P-P amplitude at 1 KHz frequency from the function
generator and repeat the above steps.
9. Compare the experimental results with the theoretical values.

EXPECTED WAVEFORMS:
Fig.3. Frequency Response of Integrator
Fig.4. Frequency Response of Differentiator
Fig.5a: Output waveform of Integrator for Sine wave input
Fig.5b: Output waveform of Integrator for Square wave input

Fig.6a: Output waveform of Differentiator for Sine wave input
Fig.6b: Output waveform of Differentiator for Square wave input
RESULT: The Integrator & Differentiator circuits were constructed using IC 741 and verified their
response for sine & square wave inputs.
REVIEW QUESTIONS:
1. Show that the output of a differentiator is differential of input.
2. Show that the output of a integrator is integral of input.
3. Mention the difference between practical integrator and ideal Integrator.
4. Sketch the Input and Output waveforms when we apply a 1Khz Triangle wave with peak to
peak value of 5V to the Differentiator circuit.
5. Explain the frequency response of an integrator.
6. What type of output waveform is obtained when a triangular wave is applied to integrator
circuit and also to Differentiator circuit?
7. A low frequency differentiator is desired for a particular application to Perform the operation Vo
(t) =-0.001 dvi(t)/dt . Determine the suitable design of differentiator circuit for the periodic signal
with a frequency of 1 KHz.

WORKSPACE

WORKSPACE

EXPERIMENT No: 11
DESIGN AND STUDY OF ACTIVE FILTERS

AIM: To design, construct and plot the frequency response of
a) First order low pass filter with cut-off frequency of 5 KHz
b) First order high pass filter with a cut-off frequency of 1 KHz.
APPARATUS REQUIRED:
1. Bread Board / CDC Board.
2. Function Generator (1MHz).
3. Cathode Ray Oscilloscope (20MHz/30 MHz)
6. Decade Resistance Box.
1. IC741 :1No
2. 1KΩ Potentiometer / DRB :1No
3. Resistor ------- 10KΩ :2No
100KΩ :1No
4. Capacitor ----- 0.1µF :1No
0.01µF :1No
CIRCUIT DIAGRAMS:
a) LOW PASS FILTER
Fig .1. Circuit diagram of 1st Order LPF

b) HIGH PASS FILTER
Fig .2. Circuit diagram of 1st Order HPF

THEORY:
A first order filter consists of a single RC network connected to the non-inverting input terminal of
the op-Amp as shown in the figure. Resistors R1 & Rf determine the gain of the filter in the pass
band. Components R & C determine the cutoff frequency of the filter.
Low-Pass filter: The circuit of 1st order low-pas filter is shown in fig.1 & its frequency response
is as shown in the fig3. The dashed curve in the fig.3 indicates the ideal response & solid curve
indicates practical filter response. It is not possible to achieve ideal characteristics. However with
special design techniques (Higher order filters) it is possible to closely approximate the ideal
response. Active filters are typically specified by the voltage transfer function,
H(s) = V0 (s)/ Vi(s) ___________(1) (under steady state conditions)
J Φ(w)
i.e s=jω => H (jω) = │H(jω) │ e _________(2), Where │ H (jω) │ is the magnitude
J Φ(w)
function and e is the phase function. Magnitude function is 20 log │H(jω) │dB & phase
function is -Φ(ω) * 57.296 degrees.
High Pass Filter: The circuit of 1st order high pass filter is shown in fig.2 & its frequency
response is as shown in the fig4. The dashed curve in the fig.4 indicates the ideal response &
solid curve indicates practical filter response. When an input signal is applied to High pass filter,
the signals at high frequencies are passed through circuit and signals at low frequencies are
rejected. That is the signal which are having frequencies less than the lower cutoff frequency fL
are rejected and the signal with frequency greater the lower cut off frequency fL are passed
through the circuit. That is
1. For f > fL, Vo(s) /Vi(s) = Maximum and is called as pass band.
2. For f < fL, Vo(s) /vi(s) = 0 and is called as the stop band

DESIGN:
Pass band gain of the active filter VO/Vin = AF = 1 + RF/R1 __________(3)
Higher cut-off frequency of the low pass filter, fH =1/2ПRC ____________(4)
Lower cut-off frequency of the High pass filter, fL =1/2ПRC ____________(5)
First order LPF
1. The higher cut-off frequency is given as, fH = 5 KHz.
2. Choose the value of C such that the value of C ≤1µF (Typically C= 0.1µF)
3. Calculate the value of R, using the formula
R =1/2ПCfH ___________ (6)
= 318.47Ω (320 Ω Approx.)
4. Get the value of damping factor, α from the Butterworth polynomials
Note: For a 1st order Butterworth active filter, the value of damping factor α=1 (from Butterworth
polynomials)
5. Calculate the value of pass-band gain, AF using the formula, α =3-Af _________ (7)
=> AF = 3- α = 3-1= 2 _________ (8)
6. Using the formula AF = 1 + RF/R1, get a relation between RF & R1.
=> RF/R1= AF -1 = 1
=> RF= R1 _______________(9)
7. Choose the value of R1=10 KΩ => RF=10 KΩ ___________ (10)
First order HPF
1. The lower cut-off frequency is given as, fL = 1 KHz.
2. Choose the value of C such that the value of C ≤1µF (Typically C= 0.01µF)
3. Calculate the value of R, using the formula
R =1/2ПCfL
= 15.9 KΩ __________ (11)
4. Get the value of damping factor, α from the Butterworth polynomials
Note: For a 1st order Butterworth active filter, the value of damping factor α=1 (from Butterworth
polynomials)
5. Calculate the value of pass-band gain, AF using the formula, α =3-Af _________ (12)
=> AF = 3- α = 3-1= 2 ___________ (13)
6. Using the formula AF = 1 + RF/R1, get a relation between RF & R1.
=> RF/R1= AF -1 = 1
=> RF= R1 __________ (14)
7. Choose the value of R1=10 KΩ => RF=10 KΩ ___________ (15)

PROCEDURE:
Low pass Filter
3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator (at
pin no.3 of the IC741 via RC Low pass network).
5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding
output voltage of the filter and tabulate the results.
6. Calculate the gain of the filter from the experimental results.
7. Plot the frequency response curve of the low pass filter with the experimental results obtained
& compare it with the expected waveform shown in Fig.3.
OBSERVATION TABLE:
VIN = 2V p-p
Vin Vout GAIN

Input
Input volatage Output Voltage 20 Log (Vout / Vin)
Frequency(Fin) Vout / Vin
in volts in volts Magnitude in dB
in Hz

High pass Filter

3. Apply a sine wave input signal of 2V peak-to-peak amplitude from the function generator (at
pin no.3 of the IC741 via RC High pass network).
5. Increase the input signal frequency in steps from 10Hz to 1MHz & Observe the corresponding
output voltage of the filter and the results.
6. Calculate the gain of the filter from the experimental results.
7. Plot the frequency response curve of the high pass filter with the experimental results obtained
& compare it with the expected waveform shown in Fig.4.
OBSERVATION TABLE:
VIN = 2V P-P
Vin Vout GAIN

Input
Input volatage Output Voltage 20 Log (Vout / Vin)
Frequency(Fin) Vout / Vin
in volts in volts Magnitude in dB
in Hz

EXPECTED WAVEFORMS:
Fig. 3 Frequency response of 1st Order LPF
Fig. 4 Frequency response of 1st Order HPF
RESULT: The first order LPF & HPF are designed for a chosen cutoff frequency and the frequency
response curves were plotted between voltage gain (dB) and frequency (Hz).

REVIEW QUESTIONS:
1. List the advantages of active filters over passive filter.
2. Derive fH of second order LPF.
3. Draw the frequency response for ideal and practical of all types of filters.
4. What are the three design techniques used for design of filters.
5. Compare the Butter worth and Chebyshev design.
6. Design a first order low pass filter for 2 KHz frequency.
7. Design a five pole low pass active Butter worth filter with 3dB cut off frequency of 2 KHz.
8. Show that the amplitude response of low pass Butter worth filter well above cutoff decreases
by 20dB per decade.
9. Draw the ideal and practical frequency response characteristics of high pass filter.
10. Mention the advantages of active filters over passive filters.
11. Draw the fourth order High pass filter for cut off frequency fL=10 KHz.
12. Design a two pole high pass active Butter worth filter with a 3dB cutoff frequency of 1 KHz.
13. Find the transfer function of first order HPF and show its frequency response.
14. What happens to filter response if the number of filter poles is increased?
15. Show the characteristics of Butter worth, Chebyshev and maximally flat time delay filter.
16. Design 4th order butter worth high pass filter with 3dB cutoff frequency of 5 KHz.

WORKSPACE

EXPERIMENT NO: 12
FUNCTION GENERATOR USING IC 741 OP – AMP

AIM: Study of op-Amp as function generator that produces various specific waveforms for test
purpose over a wide range of frequencies.
APPARATUS:
1. Function Generator Trainer kit.
2. C. R.O.
THEORY:
Function generator is a signal generator that produces various specific waveforms for test
purposes over a wide range of frequencies. In laboratory type function generator generally one of
the functions (sine, square & triangle) is generated using dedicated chips or standard circuits and
converts it in to required signal.
This consists of
1. Sine wave generator Using IC 741.
2. Square wave generator (Astable Multivibrator using IC 741)
3. Active integrator using IC 741
SINE WAVE GENERATOR:
Fig.1. Sine wave generator

The sine wave generator circuit is shown in fig.1. The operational amplifier (IC 741) used in the
circuit is provided with a positive feed back through two 47KΩ resistors and a 0.047µF capacitor.
This positive feed back provides a fraction of output signal in phase(00 or 3600) with the input at
the non-inverting terminal (pin No.3) of Op-Amp 741. Once the loop gain (Aβ) of the circuit
equals to 1 the circuit produce oscillates. The frequency of the oscillations can be controlled by
varying the feed back network components. However a negative feed back is also provided to the
Op-Amp 741 to improve the stability of the circuit.
SQUARE WAVE GENERATOR (ASTABLE MULTIVIBRATOR)
In comparison to sine wave oscillations, square wave signals are generated when the Op-Amp is
forced to operate in saturated region. That is the output of the Op-Amp is forced to swing
between +Vsat & -Vsat, resulting in square wave output. The circuit arrangement of a square
wave generator using IC 741 is shown in fig.2.
Figure .2 Square & Triangular Wave Generators
TRIANGULAR WAVE GENERATOR:

The circuit arrangement of a triangular wave generator is shown in Fig.2. A square wave from the
square wave generator is fed to the integrator. The RC time constant of the integrator has been
chosen in such a way that it is very small value compared to the time period of the incoming
square wave. For the basic operation of integrator, it is known that the output of the integrator
for a given square wave input is a triangle wave.
PROCEDURE:
1. Connect trainer kit to the 230V AC mains and switch on the supply.
2. Observe the output of the sine wave generator. If signal is not coming or distorted in shape
adjust the gain trim pot provided on the kit until a good signal is obtained. Measure the signal
frequency using Oscilloscope.

3. Observe the output of the square wave generator and measure the output signal frequency.
4. Observe the output of the Integrator (triangular wave generator) by varying the input signal
frequency (square wave is internally connected to the circuit).
5. Measure the frequency of the triangular wave using CRO.
RESULT: Hence studied op-Amp as function generator that produces Sine, square and triangular
waveforms for test purpose over a wide range of frequencies.
REVIEW QUESTIONS:
1. Explain the internal block diagram of function generator IC 8038.
2. What are the different types of function generators IC’s?
3. What type of output waveforms is obtained from function generator?
4. What type of oscillator is used in the sine wave generator and what is the frequency range?
5. What is the function of diodes across the feedback resistor in the sine wave generator?
6. What is the advantage of using OP-AMP as an oscillator?
7. Why do we call sine to square wave converter as zero crossing detector?
8. What happens when a negative reference voltage is applied at the non-inverting terminal of a
square wave generator?
9. Why the RC time constant kept very small compared to incoming square wave time period to
generate triangular waveforms?
10. How do you vary the frequency and amplitude of different waveforms obtained from function
generator

WORKSPACE

EXPERIMENT NO: 13
MONOSTABLE MULTIVIBRATOR USING 555 TIMER

AIM: To design a Monostable Multivibrator using 555 timer to get 10msec. pulse output.
APPARATUS REQUIRED:
1. C.R.O
2. Regulated DC power Supply
3. Function generator
4. CDS Board/ Bread Board.
5. Connecting patch chords.
1. IC 555 Timer :1 No.
2. Resistors ---- 100 KΩ :1 No.
3. Capacitor ---- 1µF :1 No.
0.01µF :1 No.
CIRCUIT DIAGRAM:
Fig.1
Fig.2. Trigger Circuit

THEORY:
The 555 Timer is used in number of applications; it can be used as monostable, astable
multivibrators, DC to DC converters, digital logic probes, analog frequency meters, voltage
regulators and time delay circuits.
The IC 555 timer is 8-pin IC and it can operate in free- running (Astable) mode or in one-
shot (Monostable) mode. It can produce accurate and highly stable time delays or oscillations.
Monostable can also called as One-shot Multivibarator. Fig (1) shows the Pin configuration of
Monostable Multivibrator. When the output is low, the circuit is in stable state, Transistor Q1 is
ON and capacitor C is shorted out to ground. However, upon application of a negative trigger
pulse to pin-2, transistor Q1 is turned OFF, which releases short circuit across the external
capacitor and drives the output High. The capacitor C now starts charging up toward Vcc through
R. However, when the voltage across the external capacitor equals 2/3 Vcc, the output of
comparator1 switches from low to high, which in turn drives the output to its low state. The
output, Q of the flip flop turns transistor Q1 ON, and hence, capacitor C rapidly discharges
through the transistor. The output of the Monostable remains low until a trigger pulse is again
applied. Then the cycle repeats. Fig (2) shows the trigger circuit & Fig.3 shows trigger input,
output voltage and capacitor voltage waveforms.
Pulse width of the trigger input must be smaller than the expected pulse width of the output
waveforms. Trigger pulse must be a negative going input signal with amplitude larger than 1/3
Vcc. The time during which the output remains high is given by
tp =1.1RC -------------(1)
Once triggered, the circuit’s output will remain in the high state until the set time tp elapses. The
output will not change its state even if an input trigger is applied again during this time interval
tp.
DESIGN:
Step 1: Choose C=1µF.
Step 2: Since in monostable multivibrator, tp=1.1RC. Therefore R= tp / 1.1C ---- (2)
Step 3: Using equation (2), design the value of R.
PROCEDURE:
1. Connect the 555 timer in Monostable mode as shown in fig.1.
2. Connect the C.R.O at the output terminals & observe the output.
3. Apply external trigger at the trigger input terminal (PIN 2) and observe the output of
Monostable Multivibrator.
4. Record the trigger input, voltage across the capacitor & output waveforms and measure the
output pulse width.
5. Verify results with the sample output waveforms as shown in fig (3)
6. Calculate the time period of pulse (tp =1.1RC) theoretically & compare it with practical values.
OBSERVATION TABLE:
S.No Theoretical value of o/p pulse width (in m.sec) Practical value of the o/p
(tp =1.1RC) pulse width (in m.sec)
EXPECTED WAVEFORMS:
Fig.3
RESULT: Hence designed & studied 555 timer as a Monostable multivibrator and also theoretical
& Practical of time period values of the output waveform are compared.
REVIEW QUESTIONS:
1. List the important features of the 555 Timer.
2. Define Duty cycle.
3. What are the modes of operation of Timer and explain the differences between two operating
modes of the 555 Timer.
4. The Monostable multivibrator circuit is to be used as a divided by 2 network. The frequency of
the input trigger signal is 2 KHz. If the value of C=0.01 µF, what should be the value of RA (Let
tp =1.2T)
5. Consider the Monostable multivibrator with R=3KΩ and C=0.0068µF.
Determine the pulse width.
6. Design a Monostable multivibrator to produce an output pulse 2 msec wide.
7. What is the function of control input (pin5) of 555 timers?
8. List the applications of 555 timers in Monostable mode.
9. Why do we use negative trigger for Monostable operation?
10. Explain the trigger circuit used for Monostable multivibrator?

WORKSPACE

EXPERIMENT NO: 14
ASTABLE MULTIVIBRATOR USING 555 TIMER

AIM: To design an Astable Multivibrator using IC 555 timer to generate a square wave of 6.9
KHz with 52.38 % Duty Cycle.
APPARATUS REQUIRED:
1. C.R.O
2. Function generator
4. CDS Board/ Bread Board.
1. IC 555 Timer : 1 No.
2. Resistors ------ 10 KΩ : 1 No.
1KΩ : 1 No.
3. Capacitor ---- 0.01 µF : 1 No.
0.1 µF : 1 No.
PIN CONFIGURATION OF 555 TIMER:
Fig. 1
CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:
Fig. 2
THEORY:
The 555 Timer is used in number of applications; it can be used as monostable, astable
multivibrators, DC to DC converters, digital logic probes, analogy frequency meters, voltage
regulators and time delay circuits. The IC 555 timer is 8-pin IC and it can operate in free-
running (Astable) mode or in one-shot (Monostable) mode. The pin configuration of NE 555 Timer
is as shown fig (1). It can produce accurate and highly stable time delays or oscillations.
Astable Multivibrator often called a free-running Multivibrator. External Trigger input is not
required to operate the 555 as an Astable Configuration. However, the time during which the
output is either high or low is determined by two external components Resistor & Capacitor. Fig
(2) shows the 555 as Astable Multivibrator. Initially, when the output is high, capacitor C starts
charging towards Vcc through resistor Ra and Rb. As soon as voltage across the capacitor equals
to 2/3 Vcc, comparator-1 triggers the flip-flop, and the output is low. Now capacitor discharges
through Rb and transistor Q1. When the voltage across capacitor C equals to 1/3Vcc, comparator-
2’s output triggers the flip-flop, and the output goes high. Then the cycle repeats. The output
voltage waveforms are as shown in fig (3).In this way capacitor periodically charges and
discharges between 2/3Vcc and 1/3Vcc respectively.
The time during which the capacitor charges from 1/3Vcc to 2/3 Vcc is equal to the ON
time of the timer (i.e. the output is HIGH) and is given by
tc =0.69(R1+R2)C ---- (1)

The time during which the capacitor discharges from 2/3 Vcc to 1/3Vcc is equal to the OFF time
of the timer, during which the output is LOW and is given by
td =0.69(R2)C --- (2)

The total time period of the output is the sum of charging time( tc )and discharging time(td) and
is given by
T = tc + td = 0.69(R1 + 2R2) C --- (3)

Therefore the frequency of oscillations of Astable multivibrator is given by
F = 1/T = 1.45/ (R1 + 2R2) C --- (4)
DUTY CYCLE:
This term is in conjunction with Astable Multivibrator. The duty cycle is the ratio of the ON time,
tc during which the output is high to the total time period T. It is generally expressed as a
percentage.
Duty cycle,D = (TON /TON+ TOFF) = tc /T = (R1 + R2) / (R1 + 2R2) --- (5)

DESIGN:
Step1: Choose C=0.01 µF
Step2: using the formula, F = 1.45/ (R1 + 2R2) C, Get a relation between R1 & R2.
Step3: Consider the expression for duty cycle, D= (TON /TON+ TOFF) = (R1 + R2) / (R1 +2R2) &
obtain a relation between R1 & R2.
Step4: Using the relations between R1 & R2., obtained in step2 & step3, solve for R1 & R2.
PROCEDURE:
1. Connect the IC 555 timer in Astable mode as shown in fig.2
2. Connect the C.R.O at the output terminal (pin 3) and observe the output.
3. Record the waveforms at pin3, across the capacitor & compare them with the
sample output waveforms as shown in fig (3)
4. Measure the charging time (tc), discharging time (td) and total time period/ Frequency from
the output waveform.
5. Calculate tc, td, time period (T), frequency (f) of the square wave output and percentage duty
cycle theoretically.
6. Compare the theoretical values charging time (tc), discharging time (td) ,total time period/
Frequency & % Duty cycle with the practical values.
OBSERVATION TABLE:
S.NO Theoretical Values Practical Values
tc td T f D tc td T F D
(m.sec) (m.sec) (m.sec) (in Hz) (m.sec) (m.sec) (m.sec) (inHz)
EXPECTED WAVEFORMS:
Fig.3
RESULT: Hence designed & studied IC 555 timer as an Astable multivibrator and also calculated
the frequency of oscillations & time period of output waveform.
REVIEW QUESTIONS:
1. List the important features of the IC555 Timer. 2. Define Duty cycle.
3. What are the modes of operation of Timer and explain the difference between two operating
modes of the 555 Timer.
4. Consider the Astable multivibrator with R1=10KΩ,R2=200KΩ and C=0.1µF. Determine
a) High state interval b) Low state interval c) Period d) Frequency e) Duty cycle.
5. Design an Astable 555 timer circuit to produce a 2kHz square wave with a duty cycle of 70%.
6. What is the function of control input (pin5) of 555 timer?
7. Compare the time period ‘T’ of the Astable multivibrator using IC555 timer& op-amp IC741.
8. Why do we connect pin 4 of IC 555 timer to supply pin when it is not used.

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EXPERIMENT NO: 15 (a)
SCHMITT TRIGGER USING IC 741 OP-AMP

AIM: To construct and study the Schmitt Trigger using IC741 Operational Amplifier
APPARATUS REQUIRED:
3. Dual Channel Oscilloscope(CRO)
4. Digital Multimeter
5. CDS Board / Bread Board
6. Connecting wires
1. IC 741 : 1 No.
2. Resistors -------- 1KΩ : 2 No.
3. Decade Resistance Box (DRB) : 1 No.
CIRCUIT DIAGRAM:
Fig.1
THEORY:
Circuit diagram of Schmitt trigger is shown in Fig 1. It’s also called regenerative comparator. The
input Voltage is applied to the inverting terminal & feed back voltage to the non-inverting
terminal. The input voltage vi triggers the output Vo every time it exceeds certain voltage levels.
These voltage levels are called upper threshold & lower threshold. The hysteresis width is
difference between these two values.
These voltages are calculated as follows
Suppose the output voltage Vo= +Vsat. The voltage at inverting terminal will be
R2
Vref + Vsat − Vref  = Vut
R1 + R2 
----- (1)
For Vo= -Vsat then
R2
Vref − Vsat +Vref  = Vlt
R1 + R2  ---- (2)
The input voltage Vi must become lesser than VL in order to cause Vo to switch from -Vsat to +
Vsat.
The hysterisis width VH can be written as
2R2
VH =Vut −Vlt = Vsat ---- (3)
V1 +V2
PROCEDURE:
1. Connect the circuit as shown Fig.1.
2. Set Function Generator output for sine wave signal of Amplitude at 1V(p-p) & frequency
1KHz.
3. Set R1 and R2 values at fixed positions and note down the values in tabular column.
Calculate theoretical values of Vut and Vlt and note down the values in tabular column.
(+Vsat = 14V,- Vsat = -14V).
4. Apply Function Generator output at input terminals Vi, connect C.R.O- CH2 at output
terminals Vo, C.R.O-CH1 at input terminals Vi.
5. Observe square wave output on C.R.O for the given input sine wave & compare them
with the sample waveform as shown in fig.2.
6. Note down the practical Vut , Vlt and VH values in tabular column.
7. Compare the theoretical and practical values of Vut,Vlt and VH
OBSERVATION TABLE:
Theoretical Values Practical Values

R1 R2 R1 R1 VH Vlt Vut VH
S.No Vut =
R1 + R2
( +Vsat ) Vlt =
R1 + R2
( −Vsat ) in (Volts) (Volts) in
volts volts
in Volts in Volts

INPUT AND OUTPUT WAVE FORMS OF SCHMITTH TRIGGER:
Fig.2
RESULT: Hence constructed and studied Schmitt trigger using IC 741.

REVIEW QUESTIONS:
1. How can a comparator be converted to Schmitt trigger
2. What do you mean by the Phenomenon hysteresis or backlash.
3. In the circuit shown R2 = 100Ω, R1 = 50KΩ ,Vref = 0V, Vi = 1VPP(Peak to Peak) sine wave
and saturation Voltage = ± 14V. Determine threshold voltages VUT and VLT
4. Define upper trigger point (UTP) and lower trigger point (LTP).
5. Find UTP and LTP values when R1=20 KΩ, R2=5KΩ, Vref=0V and Vcc=±12v
6. When the op amp is operated with Vcc=± 12 V then what will be the saturated output
voltages.
7 How do you change the trigger levels of the Schmitt trigger?
8. Define the Hysteresis voltage VH and how can we reduce VH.
9. Calculate the threshold voltage and sketch the input-output characteristics curve with
R1 = 10Kohms, R2 = 16Kohms & V = ± 13V for Inverting Schmitt trigger.
10. Sketch the output waveform, when a triangular wave of 5V p-p is applied to non- inverting
Schmitt trigger.

WORKSPACE

EXPERIMENT No.15 (b)
SCHMITT TRIGGER USING IC555 TIMER

AIM: To construct and study of the Schmitt Trigger using IC 555 timer.
APPARATUS REQUIRED:
1. C.R.O
5. Connecting Patch Chords
1. IC 555 timer : 1No.
2. Resistors --- 10KΩ : 2No.
3. Capacitors --- 0.01µF : 1No.
--- 0.1 µF : 1No.
CIRCUIT DIAGRAM:
Fig.1
THEORY:
In Schmitt Trigger two internal comparators are tied together and externally biased at VCC/2
through R1 & R2. Since the upper comparator will trip at (2/3) VCC and lower comparator at
(2/3) VCC the bias provided by R1 & R2 is centered within these two thresholds. Thus a sine
wave of sufficient amplitude (>VCC/6 = 2/3 VCC – VCC/2) to exceed the reference levels causes
the internal flip –flop to alternately set and reset providing a square wave output.

PROCEDURE:
1. Connect the circuit as shown in fig (1).
2. Apply the input sine wave 5V (P-P) using function generator at 1KHZ frequency.
3. Observe the output waveform at Pin No: 3.
4. Calculate the duty cycle using formula.
D=  = 10 K
R2  =0.5 or 50%
 R1 + R2   10 K + 10 K 
INPUT AND OUTPUT WAVEFORMS:
Fig. 2
RESULT: Constructed and studied the Schmitt Trigger using IC 555 timer.
REVIEW QUESTIONS:
1. Explain how a square wave is obtained at the output of timer when sine wave input is given.
2. What type of waveform is obtained when triangular or ramp waveforms are applied to Schmitt
trigger circuit?
3. Explain how upper trigger and lower trigger levels are obtained in the Schmitt trigger circuit.
4. Why do we short pin 2 and pin 6 of IC 555 timer for Schmitt trigger operation.
5. Why do we connect pin 4 of 555 timer to Vcc.
6. What is the function of pull up resistor RL in the Schmitt trigger circuit?
7. Why do we call Schmitt trigger as square wave generator.
8. How do you vary the duty cycle of the output waveform?

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WORKSPACE

EXPERIMENT NO: 16
VOLTAGE REGULATOR USING IC 723

AIM: a) To construct and study low and high voltage regulators using IC 723.
b) To find the %regulation of low and high voltage regulators.
APPARATUS REQUIRED:
1. Oscilloscope.
5. Regulated Power Supply
1. IC 723 : 1No.
2. 10K POT : 1No.
3. Resistors ---- 2.2KΩ : 2No.
1 KΩ : 1No.
4. Capacitors ---- 100 pF : 1No.
0.1 µF : 1No.
CIRCUIT DIAGRAM:
Fig.1 Low voltage Regulator

Fig.2 High Voltage Regulator

CIRCUIT DESCRIPTION:
The IC 723 is a monolithic integrated circuit voltage regulator featuring high ripple rejection,
excellent input and load regulation & excellent temperature stability etc. It consists of a
temperature compensating reference voltage amplifier, an error amplifier, 150mA output
transistor and an adjustable output current limiter.
The basic low voltage regulator type 723 circuit is shown in figure.1.The unregulated input
voltage is 24V and the regulated output voltage is varied from 0.2V to 7.5V by varying the value
of R2. A stabilizing capacitor (C1) of 100pF is connected between frequency compensation

terminal and inverting (INV) terminal. External NPN pass transistor is added to the basic 723-
regulator circuit to increase its load current capability. For intermediate output voltages the
following formula can be used
Vout = (R2/R1+R2) Vref ----------(1)

The basic high voltage regulator type 723 circuit is shown in figure.2.The output voltage can be
regulated from 7 to 37Volts for an input voltage range from 9.5 to 40Volts. For intermediate
output voltages the following formula can be used
R +R
V = 1 2 *V ----------(2)
out R ref
2
PROCEDURE:
LOW VOLTAGE REGULATOR
1. Connect the circuit diagram as shown in figure.1.
2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.
3.Calculate the line regulation of the regulator using the formula
Line Regulation = ∆VO / ∆Vi ------------- (3)
4. By varying 10K potentiometer at the load section and note down the regulator output voltage.
5. Calculate the Load regulation of the regulator using the formula
Load Regulation ==∆VO / ∆IL ------------ (4)
6. Also calculate the Percentage of load regulation using the formula
E1 − E2
*100 ----------------- (5)
E1
Where E1 = Out put voltage without load & E2 = Out put voltage with load.
HIGH VOLTAGE REGULATOR
2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.
3. Calculate the line regulation of the regulator using the formula
Line Regulation = ∆VO / ∆Vi ------------ (6)
4. By varying 10K potentiometer at the load section and note down the regulator output voltage.
Load Regulation = ∆VO / ∆IL ------------ (7)
6. Also calculate the Percentage of load regulation using the formula
E1 − E2
*100 -----------------(8)
E1
Where E1 = Out put voltage without load & E2 = Out put voltage with load.
OBSERVATION TABLE:
i) FOR LOW VOLTAGE REGULATOR

LINE REGULATION: (RL is constant)
S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is Constant)
Load Resistance, RL in Ohms Regulated DC output, VO in Volts

S.No
ii) FOR HIGH VOLTAGE REGULATOR

S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts
EXPECTED WAVE FORMS
Fig.3. Line Regulation
Fig.4. Load Regulation

RESULT: Low and high voltage regulators using IC 723 were constructed and studied. Also the
line and load regulations of the low & high voltage regulators are verified.
REVIEW QUESTIONS:
1. What is the function of a voltage regulator?
2. What is a voltage reference? Why is it needed?
3. Draw the functional block diagram of 723 regulators and explain.
4. Design a high voltage and low voltage regulator using IC 723.
5. Define line and load regulation of a regulator.
6. List the features of a voltage regulator IC 723.
7. List the different types of IC voltage regulators
8. What is the output voltage range of an IC 723 voltage regulator?
9. What is the function of CL & CS terminals of IC 723 regulator?
10. What is the difference between a series and shunt voltage regulator?
11. What is the difference between a linear and switching regulator.
12. What are the basic units / elements of a voltage regulator?

WORKSPACE

WORKSPACE

EXPERIMENT NO: 17
DIGITAL TO ANALOG (D/A) CONVERTERS

a) Weighted Resistor DAC
AIM: To obtain analog output voltages for the digital input data using 4- bit D/A converter using
weighted resistors method.
APPARATUS REQUIRED:
1. 4 – bit D/A converter (weighted resistors) Trainer kit.
2. Multimeter.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect trainer to the mains and switch on the power supply.
2. Measure the power supply voltages in the circuit as +12V & -12V.
3. Calculate V0 theoretically for the digital I/P data using formula.
b 2b 4b2 8b3 
Vo = −Rf  0 + 1 + + 
 R R R R 
Use Rf = 1 kΩ & R= 10kΩ.

4. Note down O/P voltages for different combinations of digital inputs and compare it with
theoretical value.
For Example:
When b3 is high and all other inputs are low then the output voltage is
0 0 0 5 
Vo = −Rf  + + +  = 4V
 R R / 2 R / 4 R /8

TABLE:
Digital Input Data
Theoretical (V0) Practical (V0)
b1 b2 b3 b4
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
RESULT: Obtained analog output voltages for the given digital input data using 4- bit weighted
resistor D/A converter.
REVIEW QUESTIONS:
1. How many resistors are required in 12 bit-weighted resisters DAC?
2. Mention different techniques for D/A conversion
3. What is the main disadvantage of weighted resistor DAC over others?
4. A 5-bit D/A converter is available. Assume that ‘00000’ corresponds to an output of 10V
and that the D/A converter is connected for 0.1 V for increment. What output voltage will
be produced for’11111’?
5. Define the terms full-scale voltage and one least-significant bit for a D/A converter.
6. Consider the 4-bit D/A converter with Vr=10V,Rf=10KΩ. Determine
a) Number of possible output levels b) Full scale voltage c) Value of 1 LSB
7. Determine the out put voltage for the following input digital words when 4-bit D/A converter
with Vr=10V, Rf=10KΩ is considered
i) 0001 ii) 0110 iii) 1010
8. Derive Vo of 4-bit D/A converter.

b) R-2R Ladder Network DAC

AIM: To obtain analog output voltages for the digital input data using 4-bit R-2R ladder type D/A
converter.
APPARATUS REQUIRED:
1) 4 – bit D/A converter (R-2R) Trainer Kit.
2) Multimeter.
CIRCUIT DIAGRAM:
PROCEDURE:
1. Connect the trainer to the mains and switch on the power supply.
2. Measure the supply voltages of the circuit as +12V & -12V.
3. Calculate theoretically Vo for all digital Input data using formula.
b b b b 
V0 = −Rf  3 + 2 + 1 + 0 
 2R 4R 8R 16R 
In this experiment Rf = 1 1kΩ & R= 11kΩ.
4. Note down Output voltages for different combinations of digital inputs and compare it with
theoretical values.
For Example:
When b3 is high and all other inputs are low then the output voltage is
5 0 0 0   5 
V = −R  + + + = −11K  = −2.5V
o f  2R 4R 8R 16R  2*11K 

TABLE:
Digital Input Data Theoretical Value of Practical Value of the

b1 b2 b3 b4 the output,V0 (in volts) output,V0 (in volts)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
RESULT: Obtained analog output voltages for the given digital input data using 4- bit R-2R
ladder network D/A converter.
REVIEW QUESTIONS:
1. Derive the expression for the output voltage V0 of R-2R type D/A converter.
2. What are the advantages of R-2R type D/A converter?
3. Compare R-2R Type with weighted resistor type D/A converter.
4. Mention the applications of D/A converters.
5. Define the terms full-scale voltage and one least-significant bit for D/A converter.
6. Consider the 4-bit D/A converter with Vr=10V,Rf=10KΩ. Determine
a) Number of possible output levels b) Full scale voltage
c) Value of 1 LSB
7. Determine the out put voltage for the following input digital words when 4-bit D/A converter
with Vr=10V,Rf=10KΩ is considered
i) 0001 ii) 0110 iii) 1010
8. What is the difference between Inverted R-2R and Non-Inverted R-2R type D/A converter?

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WORKSPACE

EXPERIMENT NO: 18
STUDY OF OP-AMPS
AIM: To study the pin configurations, specifications & functioning of different integrated circuits
used in the practical applications.
APPARATUS REQUIRED:
a). IC µA 741 OP-Am
b). LM 311N Voltage Comparator
c). NE ISE 555/SE 555C
d). VCO IC 566
e). Phase Locked Loop NE/SE 565
f). IC 723 Voltage Regulator
g). Three Terminal Voltage Regulators
a) µA 741 OP-AMP
Pin configuration
Specifications
1. Supply voltage:
µA 741A, µA 741, µA 741E ---------------- ±22V
µA 741C ---------------- ±18 V
2. Internal power dissipation
DIP package ----------------- 310 mw.
3. Differential input voltage ---------------- ±30 V.
4. Operating temperature range
Military (µA 741A, µA 741) --------------- -550 to +1250 C.
Commercial (µA 741E, µA 741C) --------- 00 C to +700 C.
5. Input offset voltage ------------ 1.0 mV.
6. Input Bias current ------------ 80 nA.
7. PSSR --------------30µV/V.
8. Input resistance -------------2MΩ.
9. CMMR --------------90dB.

10. Output resistance ---------------75Ω.

11. Bandwidth --------------1.0 MHz.
12. Slew rate ---------------0.5 V/µ sec.
b) LM 311N VOLTAGE COMPARATOR
Pin configuration
Specifications
1. Total supply voltage ------------ 36 V
2. Input Voltage ------------ ±15V
3. Power dissipation ------------ 500mW
4. Operating temperature ------------ 00 C to 700C
5. Input offset voltage ------------- 2.0 mV
6. Input Bias current ------------ 100nA
7. Voltage gain ------------- 200V/mv
c) NE / SE 555 TIMER
Pin configuration
Specifications
1. Supply voltage ------------ 4.5 V to 18 V
2. Supply current ------------ 3mA
3. Output voltage (low) ------------- 0.1 V
4. Output voltage (high) ------------- 12.5 V (15 V Vcc) & 3.3 V (5V Vcc)
5. Maximum operating frequency -------------- 500 KHz
6. Timing -------------- µsec to hours
d) IC 566 VCO
Pin configuration
Specifications
1. Operating supply voltage (Vcc) --------- 12V (on less otherwise specified 24V).
2. Operating Supply current --------- 12.5mA
3. Input Voltage (Vc) --------- 3Vp-p.
4. Operating Temperature --------- 0 to 700C.
5. Power dissipation --------- 300mw.
e) NE / SE 565 PHASE LOCKED LOOP
Pin configuration
Specifications
1. Maximum supply voltage ----------- 26 V
2. Input Voltage ---------------- 3 V(P-P)
3. Power dissipation ------------- 300mw
4. Operating temperature ----- NE 565- 00 C to 700C (SE 565—55 to +1250 C
5. Supply voltage ----------- 12 V
6. Supply current ------------ 8mA
7. Output current- sink ------- 1mA
Output current- Source ----------10 mA

f) IC 723 VOLTAGE REGULATOR
Pin configuration
Specifications
1. Input voltage ----------- 40V max.
2. Output voltage ----------- 2V to 37V.
3. Output current ----------- 150mA.
(With out external pass txt)
4. Output current ------------- 10A.
(With external pass txt)
5. Input regulation --------------- 0.02%.
6. Load regulation --------------- 0.03%.
7. Operating temperature ------ 550 C to 1250 C.
g) THREE TERMINAL VOLTAGE REGULATORS
i) IC 78XX (Positive Voltage Regulators)
Pin configuration

Specifications
1.Input voltage
For 5V to 18V regulated output ---------- 35V.
Upto 24V regulated output ---------- 40V.
2.Internal power dissipation ---------- Internally limited.
3.Storage temperature range -------- -650 C to 1500 C.
4.Operating junction Temperature range
µA7800 --------- -550 C to 1500 C.
µA7800C -------- 00 C to 1250 C.
ii) IC 79XX ( Negative Voltage Regulators )
Pin configuration
Specifications
1. Input voltage
For -5V to -18V regulated output ---------- -35V.
For -24V regulated output ---------- -40V.
2. Internal power dissipation ------- Internally limited.
3. Storage temperature range -------- -650 C to 1500 C.
4. Operating junction Temperature range
µA7800 --------- -550 C to 1500 C.
µA7800C -------- 00 C to 1250 C.
RESULT:
The pin configuration specifications & functioning of different integrated circuits used in the
practical applications have been studied.

WORKSPACE

EXPERIMENT NO: 19
INVERTING, NON- INVERTING AMPLIFIERS

AND VOLTAGE FOLLOWER USING IC 741 OP-AMP
AIM: a) To find the voltage gain of Inverting and Non- Inverting amplifiers Using IC
741 Operational Amplifiers.
b) To study the operation of Voltage Follower.
APPARATUS REQUIRED:
1. Bread Board/ CDS Board.
3. Cathode Ray Oscilloscope
1. IC741 :1No
2. Resistor s---- 1KΩ :1No
10KΩ :1No
100KΩ :1No
3. Capacitor --- 0.01µf :1No
CIRCUIT DIAGRAMS:
a) INVERTING AMPLIFIER:
Fig. 1
NON-INVERTING AMPLIFIER:
Fig. 2
b) VOLTAGE FOLLOWER
Fig. 3

THEORY:
When the input signal is applied at the inverting input by grounding the non-inverting input of an
op-amp, the amplifier operates in the inverting mode. That is the output differs in phase by 180
degrees with respect to the input. In an inverting amplifier the gain is given by the relation Af = -
Rf/R1. Where Rf and R1 are the feedback and input resistor respectively. When operated in the
non-inverting mode, the input signal is applied to the non-inverting input with the inverting
terminal grounded through a resistor. The gain in this case is given by the relation
Af = 1+Rf/R1.
The lowest gain can be obtained from a non-inverting amplifier with
feedback is 1. When the non-inverting amplifier is configured for unity gain, it is called as Voltage
follower because the output voltage is equal to and in phase with the input voltage. The voltage
follower is also called a non-inverting buffer amplifier because, when placed between two
networks, it removes the loading on the first network.
PROCEDURE:
Part-I
Inverting amplifier
NOTE: See that the amplifier should not saturate due to excessive input voltage. It is preferred
to keep the input signal amplitude less than or equal to 1 V).
4. Connect the C.R.O at (pin no.6)the output terminals.
6. Measure the output voltage (Vo) and voltage gain (Vo/Vin) from the experimental results.
7. Calculate the output voltage of the inverting Amplifier theoretically using the formula Vo = -
(Rf/R1) Vin and find its gain using the formula Af = -Rf/R1.
Non-inverting amplifier
10. Connect the CRO at (pin no.6) the output terminals.
12. Measure the output voltage (VO) and voltage gain (Vo/Vin) from the experimental results.
13. Calculate the output voltage of the Non-inverting amplifier theoretically using the formula VO
= (1+Rf/R1) Vin and find its gain using the formula Af = 1+Rf/R1.
14. Verify the experimental results with the theoretical values.

Part-II
Voltage follower
1. Connect the circuit of voltage follower as shown in fig.3 on the breadboard.
4. Connect the CRO at (pin no.6) the output terminals.
6. Measure the output voltage (Vo) and voltage gain (Vo/Vin) from the experimental results.
7. Calculate the gain of the voltage follower using the formula Af = 1+Rf/R1.
8. Verify the experimental results with the theoretical values.
EXPECTED WAVEFORMS:
INVERTING AMPLIFIER
NON-INVERTING AMPLIFIER

VOLTAGE FOLLOWER
RESULT: Inverting and Non- Inverting amplifiers using IC741 Operational Amplifier were studied
and the results were plotted.
The operation of Voltage Follower using IC741 Operational Amplifier was studied and the results
were plotted.
REVIEW QUESTIONS:
1. Mention the applications of Inverting and non-inverting amplifiers.
2. List the ideal and practical characteristics of IC741 Op-amp.
3. Draw the circuit of DC inverting amplifier.
4. Show that the output of inverting amplifier is Vo = - (Rf/R1)Vin
5. What is the phase of the output signal when zero phase signal is applied to inverting and non-
inverting amplifier.
6. What is the minimum gain of non-inverting amplifier?
7. Show that the gain of non-inverting amplifier is Af = 1+Rf/R1.
8. Why the input terminals of IC741 Op-Amp are called Inverting and Non-Inverting terminals.
9. Give the pin configuration of IC741.
10. Draw the voltage transfer curve of ideal and practical Op-Amp.
11. List the important characteristics of a voltage follower.
12. Mention the applications of a voltage follower.
13. Why R-C components are used for AC voltage follower.
14. List the applications of OP-AMP 741 operating in non- inverting mode.
15. Draw the DC voltage follower and explain.
16. Can we use the Inverting mode of Op-Amp as voltage follower?
17. What are the other voltage follower IC’s.

WORKSPACE

EXPERIMENT No.20
PHASE LOCKED LOOP (PLL) USING IC 565

AIM: To calculate free running frequency of VCO, capture range and lock range of PLL System.
APPARATUS REQUIRED:
1. C.R.O
3. DC power supply
4. CDS board
5. Connecting wires
1. LM 565 IC : 1No
2. Resistors 10K : 1No
680Ω : 2No
3. Capacitors 0.1µF : 1No
1µF : 1No
0.01µF : 1No
CIRCUIT DIAGRAM:

PIN DIAGRAM:
Fig.1.Pin configuration of IC 565
THEORY:
The following figure shows the phase-locked loop (PLL) in its basic form. The PLL
consists of i) a phase detector ii) a low pass filter and iii) a voltage controlled oscillator as shown.
The phase detector, or comparator compares the input frequency fIN with the
feedback frequency fOUT. The output of the phase detector is proportional to the phase difference
between fIN and fOUT. The output voltage of a phase detector is a dc voltage and therefore is
often referred to as the error voltage. The output of the phase detector is then applied to the
low-pass filter, which removes the high-frequency noise and produces a dc level. This dc level, in
turn, is the input to the voltage-controlled oscillator (VCO). The filter also helps in establishing
the dynamic characteristics of the PLL circuit. The output frequency of the VCO is directly
proportional to the input dc level. The VCO frequency is compared with the input frequencies and
adjusted until it is equal to the input frequencies. In short, the phase-locked loop goes through
three states: free running, capture, and phase lock.
Before the input is applied, the phase-locked loop is in the free-running state. Once
the input frequency is applied, the VCO frequency starts to change and the phase-locked loop is
said to be in the capture mode. The VCO frequency continues to change until it equals the input
frequency, and the phase-locked state. When phase locked, the loop tracks any change in the
input frequency through its repetitive action.
Lock Range: The range of frequencies over which the PLL can maintain lock with
incoming signal is called the “ Lock Range” or “Track Range”
FL= 8f0/V-------(1) where V= + V –(–V), where f0 is free running frequency.
Capture range: The range of frequencies over which the PLL can acquire lock with an
input signal is called the capture range.
½
FC = [FL / 2Π(3.6 Χ 103)C2 ] ---------(2)
PROCEDURE:
1. Apply +5v to pin 10 and –5v to pin 1 of LM565
2. Connect R1= 10KΩ resistor from pin 8 to10 and C1 =0.01µF capacitor from
pin 9 to 1.
3. Connect 680Ω resistor from pin 2 & pin 3 to ground.
4. Connect pin 4(VCO o/p) to CRO and measure its frequency. This frequency is called
the free running frequency, fo.
5. Calculate f0 theoretically using the formula f0 = 1.2 /4R1C1 and compare it with
practical value.
6. Connect the circuit as shown in fig.
7. Apply square wave at the input with an amplitude of 2Vpp and also connect it to channel
1 of CRO.
8. Connect pin 4(VCO o/p) to channel 2 of CRO.
9. Vary the input signal frequency in steps and measure its corresponding o/p
frequency.
10. Find the lock range and capture range from the obtained data.
11. Calculate lock range, fL and capture range, fC theoretically using formula
FL = 8 f0/V Hz where V = +V- (-V)
and FC = [ fL/(2Π Χ 3.6 Χ 103 Χ C2 ) ]1/2
12. Compare theoretical and practical values.
TABULAR COLUMN:
S.No. Input Output S.No. Input Output

frequency,KHZ frequency,KHZ frequency,KHZ frequency,KHZ
` `
RESULT: Free running frequency, lock range and capture range of PLL are measured practically
and compared with theoretical value.

WORKSPACE

EXPERIMENT NO: 21
THREE TERMINAL VOLTAGE REGULATORS

AIM: a) To construct and study the 3-terminal fixed voltage regulator using IC 78XX and
79XX series.
b) To find line regulation and load regulation of the IC regulator.
APPARATUS REQUIRED:
1. Multimeter
2. Regulated DC Dual Power supply
4. Connecting patch Chords
1. Capacitors --- 1000 µF : 1 No.
--- 22 µF : 1 No.
2. IC’s
7805 :1No
7812 :1No
7905 :1No
7912 :1No
CIRCUIT DIAGRAM:
a) Fixed Positive Voltage regulator:
Fig.1
b) Fixed Negative Voltage Regulator:
Fig.2
PROCEDURE:
For fixed positive voltage regulator (78XX):
2. Apply the unregulated voltage to the IC 78XX and note down the regulator output voltage,
vary input voltage from 7V to 20V and record the output voltages
4. By varying the load resistance RL note down the regulator output voltage.
For fixed negative voltage regulator (79XX):
2. Apply the unregulated voltage to the IC 79XX and note down the regulator output voltage,
vary input voltage from 7V to 20V and record the output voltages
4. By varying the load resistance RL note down the regulator output voltage.
OBSERVATION TABLES:
FOR POSITIVE VOLTAGE REGULATOR

S.NO Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts

LOAD REGULATION: (Vi is Constant)
S.NO Load Resistance, RL in Ohms Regulated DC output, VO in Volts
FOR NEGATIVE VOLTAGE REGULATOR


EXPECTED WAVE FORMS
Fig.3. Line Regulation For 78XX
Fig.4. Load Regulation for 78XX

Fig.5. Line Regulation for 79XX
Fig.6. Load Regulation for 79XX

RESULT: Hence constructed and studied the 3-terminal fixed voltage regulator using IC 78XX
and 79XX series & also the line regulation and load regulation of them are verified.
REVIEW QUESTIONS:
1. Define line and load regulation.
2. Mention the application of voltage regulator.
3. List the types of voltage regulator.
4. List the different types of 3- terminal voltage regulator IC’s?
5. Draw and explain the internal block diagram of 3- terminal regulator IC.
6. Why do we use capacitors at input and output terminal of a regulator?
7. Define “dropout” voltage of a regulator.
8. What is the difference between a +ve and a –ve voltage regulator.
9. Compare three terminal voltage regulators with 723 voltage regulator.
10. List the features of IC voltage regulators.
WORKSPACE

EXPERIMENT NO: 22
ADJUSTABLE VOLTAGE REGULATORS USING FIXED VOLTAGE

REGULATORS
AIM:
1) To construct and study the adjustable voltage regulator (10V) using fixed voltage .
regulator IC7805
2) To construct a constant current source using three terminal voltage regulator.
APPARATUS REQUIRED:
1. Digital Multimeter
2. Regulated DC Power supply
3. Breadboard / CDS Board
4. Connecting wires
1. Capacitors –-- 0.33µF :1 No.
2. IC 7805 :1 No
3. Resistors ---- 10 Ω : 2 No.
CIRCUIT DIAGRAM:
Fig.1 Constant Current Source using IC 7805
THEORY
In the laboratory, one may need variable regulated voltages or a voltage that is not available as
standard fixed voltage regulator. This can be achieved by using a fixed three terminal regulator
as shown in Fig .1. Note that the ground (GND) terminal of the fixed three terminal regulator is
floating. The output voltage
Vo = VR + VL ________________ (1)
= VR + ( IQ + IL) RL ______________ (2)

= VR + IQ RL + VRRL/ R ____________ (3)

Or
Vo = (1+ RL / R) VR + RL IQ ________ (4)

Therefore Vo=(1+ RL / R) VR ------------ (5) (Since IQ is negligible )
Where VR is the regulated voltage difference between the OUT and GND terminals. The effect of
IQ is minimized by choosing RL small enough & the term IQ R2 can be neglected. The minimum
output voltage is the value of the fixed voltage available from the regulator. The LM117, 217,317,
IC78XX positive regulators and LM137, 237,337, IC 79XX negative regulators have been specially
designed to be used for obtaining adjustable output voltages. It is possible to adjust output
voltage from 1.2V to 40V and current up to 1.5 A. Adjustable voltage regulators provided the
answers to the excessive inventory and production costs because a single device satisfies many
voltages requirements from 1.2 up to 57 V. In addition, they have the following performance and
reliability advantages over the fixed types.
• Improved system performance by having line and load regulation of a factor of 10 or
better.
• Improved overload protection allows greater output current over operating temperature
range.
• Improved system reliability with each device being subjected to 100% thermal limit burn-
in.
Thus, adjustable voltage regulators have become more popular because of versatility,
performance, and reliability. The IC 78XX & LM317 series are the most commonly used general –
purpose adjustable positive voltage regulators. IC 79XX and LM 337 series are the most
commonly used adjustable negative voltage regulators.
PROCEDURE:
2. Apply the unregulated voltage to the IC 7805 and note down the regulator output voltage,
vary input voltage from 12V to 30V and record the output voltages.
3. Vary the load resistance in steps (by keeping i/p voltage constant) & measure the regulator
output.
4. Calculate the load current in the circuit by varying the input voltage & load Resistance in steps.
5. Calculate the line regulation & load regulation of the regulator using the formulae
Line Regulation = ∆VO / ∆Vi
Line Regulation = ∆VO / ∆IL
6. Plot the curve between unregulated input voltage and the regulated output voltage & compare
it with the expected wave form shown in Fig.2.

OBSERVATION TABLES:



EXPECTED WAVE FORMS:
a. Line Regulation
b. Load Regulation
Fig.2 Line & Load Regulation curves
RESULT: Hence constructed and studied the adjustable voltage regulator (10V) & constant
current source using fixed voltage regulator IC7805 .
REVIEW QUESTIONS:
1. Define line and load regulation.
2. Mention the application of voltage regulator.
3. List the types of voltage regulator.
4. List the different types of 3- terminal voltage regulator IC’s?
5. Draw and explain the internal block diagram of 3- terminal regulator IC.
6. Why do we use capacitors at input and output terminal of a regulator?
7. Define “dropout” voltage of a regulator.
8. What is the difference between a +ve and a –ve voltage regulator.
9. Compare three terminal voltage regulators with 723 voltage regulator.
10. List the features of IC voltage regulators.
WORKSPACE

WORKSPACE

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Department of ECE IC & PDC LAB Manual

LINEAR WAVE SHAPING

Resistors and Capacitors can be connected in series or parallel in various combinations.

1 VARDHAMAN COLLEGE OF ENGINEERING

High – pass RC circuit as a differentiator:

RC high pass circuit:

i)Long time constant: RC > > T ;

ii) Medium time constant: RC = T

iii) Short time constant: RC < < T

2 VARDHAMAN COLLEGE OF ENGINEERING

RC low pass circuit: (Design procedure is same as RC high pass circuit)

i) Long time constant : RC > > T, C = 0.1µf

& because of symmetry V1= -V2 V1 =- V21

3 VARDHAMAN COLLEGE OF ENGINEERING

4 VARDHAMAN COLLEGE OF ENGINEERING

1. Connect the circuit as shown in figure (LPF / HPF)

High pass RC circuit:

5 VARDHAMAN COLLEGE OF ENGINEERING

Output Signal Output Signal

Medium time constant

Output Signal Voltage

Short time constant

Medium time constant

Long time constant

6 VARDHAMAN COLLEGE OF ENGINEERING

7 VARDHAMAN COLLEGE OF ENGINEERING

8 VARDHAMAN COLLEGE OF ENGINEERING

NON LINEAR WAVE SHAPING-CLIPPERS

1. Connect the circuit as shown in fig.

9 VARDHAMAN COLLEGE OF ENGINEERING

Fig 2.1 Negative clipper with zero reference (Series clipper)

Fig 2.2 Positive clipper with zero reference (Series clipper)

Fig 2.3 Negative clipper with zero reference (Shunt clipper)

Fig 2.4 Positive clipper with zero reference (Shunt clipper)

10 VARDHAMAN COLLEGE OF ENGINEERING

Fig 2.5 Positive clipper with positive reference (Series clipper)

Fig2.6 Positive clipper with positive reference (Shunt clipper)

Fig2.7 Negative clipper with positive reference (Series clipper)

Fig2.8 Negative clipper with positive reference (Shunt clipper)

11 VARDHAMAN COLLEGE OF ENGINEERING

Fig.2.9 clipping at two independent levels.

TRANSFER CHARACTERISTIC CURVES:

12 VARDHAMAN COLLEGE OF ENGINEERING

13 VARDHAMAN COLLEGE OF ENGINEERING

Sl No. Type of Clipper Reference Theoretical Practical

1 Series Positive Clipper 2V

2 Series Negative Clipper 2V

3 Shunt Positive Clipper 2V

4 Shunt Negative Clipper 2V

5 Two level clipper

14 VARDHAMAN COLLEGE OF ENGINEERING

15 VARDHAMAN COLLEGE OF ENGINEERING

16 VARDHAMAN COLLEGE OF ENGINEERING

NON LINEAR WAVE SHAPING-CLAMPERS

1. CRO (Dual Channel) - 1 No.

17 VARDHAMAN COLLEGE OF ENGINEERING

Fig.3.1 Negative clamping with zero reference voltage

Fig.3.2 positive clamping with zero reference voltage

Fig.3.3 Negative clamping with Negative reference voltage

Fig.3.4 positive clamping positive reference voltage

Fig.3.5 Negative clamping with Positive reference voltage

18 VARDHAMAN COLLEGE OF ENGINEERING