ECE 464/520 Class Notes

Introduction to CMOS Design

Dr. Paul D. Franzon
Outline
1. CMOS Transistors
2. CMOS cell design
3. Transistor Sizing
References
z Smith and Franzon, Chapter 11
z Weste and Eshraghian, Principles of CMOS VLSI Design,
A Systems Perspective

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ECE 464/520 Class Notes

CMOS Transistors
Gate Polysilicon Conductor
1. nMOS Transistor
Silicon Oxide Gate
Drain
Source
W
n n
p substrate

Gate L Gate

Drain Source Drain Source

substrate

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 ECE 464/520 Class Notes

Transistors
2. pMOS transistor: Gate
Silicon Oxide Gate
Drain
Source
W
p p
n substrate

Gate L Gate

Drain Source Drain Source

substrate

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ECE 464/520 Class Notes

MOS Transistor Theory

Transistor States:
1. Cutoff Region
Ids = 0 when Vgs < Vt
Vt = Threshold Voltage (typically 1 V for nMOS, - 1V for pMOS)
2. Linear Region
Ids = Β ((Vgs - Vt)Vds - Vds2/2)
when 0 < Vds < Vgs - Vt
Β=(µε/tox)(W/L)
W = channel width
L = channel length
µ = electron (n) / hole (p) mobility
ε = permittivity of gate insulator
tox = gate insulator (oxide) thickness

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 ECE 464/520 Class Notes

... nMOS Transistor Theory

.... Transistor States
3. Saturatation Region
Ids = Β (Vgs - Vt)2
when 0 < Vgs - Vt < Vds

Q: Draw a large signal equivalent model for transistor in Linear and

Saturation States for falling output:

t=0 Vo<VDD-Vtn

Transistor Characteristics:

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ECE 464/520 Class Notes

Transistor Characteristics

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 ECE 464/520 Class Notes

CMOS Inverter
Static CMOS Inverter: 5V
p1
Vin Vout
n1
0V

What are the transistor states when:

Vin = 0 V n1 : VGS < Vt : Off
p1 : |VGS| > |Vt|, Vds=0 : Linear

Vin = 5 V n1 : VGS > Vt, VDS=0 : Linear

p1 : |VGS| < |Vt| : Off

given |Vt| = 1 V

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ECE 464/520 Class Notes

Transistor Speed is determined by SIZE

CMOS circuit speeds can be modeled to a first approximation as RC delays:
1. What does the input of a CMOS gate `look like’?
Capacitor, C ∝ W x L

2. What does the `output’ of a CMOS gate `look like’ during switching?

Resistor, R ∝ L/W
3. Usually hole mobility is half of electron mobility. So what must you do to
make the pull up and pull down delays about the same?
Equalize RC constants, Wp/Wn = µn/µp

4. If a gate is heavilly loaded what must you do to speed up the delay?

Decrease RC, Make gate wider

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 ECE 464/520 Class Notes

Other Gate Designs

Refer to data sheets in CMOSX library:
z NOR gate
Analyze the circuits to determine `how
these gates work’.

A0 A1 : N0 N1 P0 P1 : Y
0 0 :
Off Off On On : 1

0 1 : Off On On Off : 0

1 0 : On Off Off On : 0

1 1 : On On Off Off : 0

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ECE 464/520 Class Notes

DFF
Master Slave

Clock buffer (guarantees clock edge rate and thus tsu, thold)

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 ECE 464/520 Class Notes

DFF

Function:

D Ck : Output

1 D
0 0 :

0 1 : z
Ck’
1 0 : 0

1 1 : 0
Ck

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ECE 464/520 Class Notes

DFF

Function:
Regenerative Latch
- Feedbacks MQ when Ck high

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 ECE 464/520 Class Notes

DFF
Master Slave

Propagates D Regenerates Propagates D Regenerates

when Ck low D when Ck high when Ck high D when Ck low
Positive Edge Flip-Flip
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ECE 464/520 Class Notes

Summary
• What dimensions determines the “drive strength” of a transistor?

Transistor width/length

• What states can a transistor have?

Off, Linear, Saturation

• Why is the clock input to the C2MOS flip-flop buffered?

To make the clock rise/fall time predictable,
so that t_setup is predictable, and race does not
occur.

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 ECE 464/520 Class Notes

Summary
z Complementary MOS transistors gives dense circuits and
lower power than other circuit families
z Standard Cell designs use Static CMOS
z Transistor speed approximated using `on resistance’
z Ron proportional to electron/hole mobility and W/L
‹ Hole mobility = half electron mobility

Î Inverter Wp = 2 Wn to make trise = tfall

‹ To drive larger loads, increase transistor width proportionally

z Power consumption important in many designs

Power = Σ Nswitch f Vcc2 Cload
z Lower ing voltage by one-half, quarters the power but halves the
speed
z Turn clock frequency down when performance not needed
z Reduce Nswitch through good design

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