VHDL Code for full adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fa1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end fa1;

architecture Behavioral of fa1 is

begin

sum<=a xor b xor cin;

cout<=(a and b) or( b and cin) or (cin and a);

end Behavioral;

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Technology schematic:

DFF VHDL CODE:

--------------------------------------------------------------------------------
--
-- Company:
-- Engineer:
--
-- Create Date: 16:25:40 02/23/2011
-- Design Name:
-- Module Name: diff_1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity diff_1 is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
rstn : in STD_LOGIC;
q : out STD_LOGIC;
qbar : out STD_LOGIC);
end diff_1;

architecture Behavioral of diff_1 is

SIGNAL qin : std_logic;
begin
process(d,clk,rstn)
begin
if(clk'event and clk='1')
then if(rstn='0')
then qin<='0';
else qin<=d;
end if;
end if;
end process;
q<=qin;
qbar<=not qin;

end Behavioral;
RTL SCHEMETIC:
TECHNOLOGY SCHEMETIC:
VHDL CODE FOR FULL SUBSTRACTOR:

--------------------------------------------------------------------------------
--
-- Company:
-- Engineer:
--
-- Create Date: 16:15:56 03/23/2011
-- Design Name:
-- Module Name: fs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fs is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
borin : in STD_LOGIC;
diff : out STD_LOGIC;
borout : out STD_LOGIC);
end fs;

architecture Behavioral of fs is

begin

process( a,b,borin )
begin
if(a='0') then
diff <= b xor borin;
borout <= b or borin;
else
diff <= b xnor borin;
borout <= b and borin;
end if;
end process;
end Behavioral;
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TECHNOLOGY SCHEMETIC: