CMOS Inverter - Dynamic Characteristics

The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
The Digital CMOS Inverter
Dynamic Characteristics
Anurup Mitra
BITS Pilani
April 2007
Charging and Discharging The Digital CMOS
Inverter
Anurup Mitra
The delay of the CMOS inverter is a performance metric for Introduction

how fast the circuit is. This delay is dependent upon the RC Delay Estimation
charging or discharging of the load capacitor by the pMOS Design Perspective
or nMOS devices respectively and provides a quantitative
feel for the time that is taken by the output of the inverter
to completely respond to a change at its input.
Output Waveforms The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
The output waveform shows a distinct RC charging and

discharging phase.
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective

discharging phase.
The green waveform indicates the short circuit current that

flows between supply and ground each time the inverter
switches. This is to be expected as the inverter passes
through the analog region during those times.
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective

discharging phase.
The green waveform indicates the short circuit current that

flows between supply and ground each time the inverter
switches. This is to be expected as the inverter passes
through the analog region during those times.
It can be intuitively inferred from these waveforms why the
dynamic power dissipation of digital circuits is usually
considered. Also, it can be noticed why this power is directly
proportional to the frequency of operation.
Simulation Results The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Capacitance Estimation The Digital CMOS
Inverter
Anurup Mitra
Several (even non-linear) capacitances contribute to the load
capacitance of the inverter. To simplify the calculation of Introduction
the delay incurred, the capacitances need to be linearised Delay Estimation
and lumped together at the output. Design Perspective

Capacitance Estimation The Digital CMOS
Inverter
Anurup Mitra
Several (even non-linear) capacitances contribute to the load
capacitance of the inverter. To simplify the calculation of Introduction
the delay incurred, the capacitances need to be linearised Delay Estimation
and lumped together at the output. Design Perspective
The most fundamental delay in digital circuits is the unit

delay where an inverter is loaded by a identical inverter and
the propagation delay calculated. This delay is constant for
any given technology.
Resistance Estimation The Digital CMOS
Inverter
Anurup Mitra
Introduction
As the output of an inverter swings from HIGH to LOW or Delay Estimation
vice versa, the nMOS and the pMOS devices (respectively) Design Perspective
might travel through various regions of operation, namely

linear, saturation and velocity saturation.
Inverter
Anurup Mitra
Introduction

Each of these regions exhibit a different ON resistance for
the MOS device. A decent approximation to the associated
Req can be got by averaging the resistances that the device
passes through during the output swing.
Inverter
Anurup Mitra
Introduction

Each of these regions exhibit a different ON resistance for
the MOS device. A decent approximation to the associated
Req can be got by averaging the resistances that the device
passes through during the output swing.
Z V1
1 V
Req = dV
V1 − V2 V2 ID (1 + λV )
where ID is chosen according to the region of operation.
Formal Definitions The Digital CMOS
Inverter
Anurup Mitra
The following are some formal definitions of temporal
parameters of digital circuits. All percentages are of the Introduction
steady state values. Delay Estimation
Design Perspective
tr Rise Time : Time taken to rise from 10% to
90%
Inverter
Anurup Mitra
Design Perspective
90%
tf Fall Time : Time taken to fall from 90% to
10%
Inverter
Anurup Mitra
Design Perspective
90%
10%
trf Edge Rate : (tr + tf )/2
Inverter
Anurup Mitra
Design Perspective
90%
10%
tpHL H-to-L propagation delay : Time taken to fall
from VOH to 50%
Inverter
Anurup Mitra
Design Perspective
90%
10%
from VOH to 50%
tpLH L-to-H propagation delay : Time taken to rise
from 50% to VOL
Inverter
Anurup Mitra
Design Perspective
90%
10%
from VOH to 50%
from 50% to VOL
tp Propagation Delay : (tpHL + tpLH )/2
Inverter
Anurup Mitra
Design Perspective
90%
10%
from VOH to 50%
from 50% to VOL
tp Propagation Delay : (tpHL + tpLH )/2
tcd Contamination Delay : Minimum time from the
input crossing 50% to the output crossing 50%
Graphical Depiction The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Delay Estimation... The Digital CMOS
Inverter
Anurup Mitra
Now that we can estimate the capacitance and resistance Introduction
associated with the charging/discharing of the output of an Delay Estimation
inverter, we can also estimate any of the defined delays by Design Perspective
viewing the output as a first-order RC network.

Delay Estimation... The Digital CMOS
Inverter
Anurup Mitra
Now that we can estimate the capacitance and resistance Introduction
associated with the charging/discharing of the output of an Delay Estimation
inverter, we can also estimate any of the defined delays by Design Perspective
viewing the output as a first-order RC network.
Hence, the rise and fall times are estimated as follows:
tpHL = 0.69Reqn Ceq
tpLH = 0.69Reqp Ceq

giving us

Reqn + Reqp
tp = 0.69 Ceq
2
...Contd. The Digital CMOS
Inverter
Anurup Mitra
Assuming velocity saturation, the Req of an MOS device is Introduction
given as Delay Estimation
Design Perspective
Z VDD
1 VdV 3 VDD 7
Req = ≈ 1 − λVDD
0.5VDD 0.5VDD ID (1 + λV ) 4 IDSAT 9
where
V2

W
IDSAT = µCox (VDD − Vt )VDSAT − DSAT
L 2
Inverter
Anurup Mitra
Design Perspective
Z VDD
1 VdV 3 VDD 7
where
V2

W
L 2
Usually, a normalised Req is provided as a technology
parameter.
Inverter
Anurup Mitra
Design Perspective
Z VDD
1 VdV 3 VDD 7
where
V2

W
L 2
Usually, a normalised Req is provided as a technology
parameter.
A similar technology parameter can be calculated for tr and
tf as well.
Example The Digital CMOS
Inverter
Anurup Mitra
Introduction
Calculate the propagation delay of a CMOS inverter in
Delay Estimation
0.18µm technology. The Req ’s of the nMOS and the pMOS Design Perspective
are 7 kΩ and 20 kΩ respectively. Their aspect ratios are 1
and 3 respectively and the load cap is 5fF.
Inverter
Anurup Mitra
Introduction
Delay Estimation
The charge down is determined by the nMOS device. Thus

7kΩ
tpHL = 0.69 × × 5fF = 24.2ps
1
Inverter
Anurup Mitra
Introduction
Delay Estimation

7kΩ
tpHL = 0.69 × × 5fF = 24.2ps
1
The charge up is determined by the pMOS device. Hence

20kΩ
tpLH = 0.69 × × 5fF = 23ps
3
Inverter
Anurup Mitra
Introduction
Delay Estimation

7kΩ
tpHL = 0.69 × × 5fF = 24.2ps
1
The charge up is determined by the pMOS device. Hence

20kΩ
tpLH = 0.69 × × 5fF = 23ps
3
Therefore the total propagation delay is given by 23.6 ps.
An Important Observation The Digital CMOS
Inverter
Anurup Mitra
Introduction
It might be tempting to think that the easiest way to Delay Estimation
decrease the propagation delay of any stage of a digital Design Perspective
system (and thus increase its speed) is to scale up the

(W/L)’s of that particular stage.
An Important Observation The Digital CMOS
Inverter
Anurup Mitra
Introduction
It might be tempting to think that the easiest way to Delay Estimation
decrease the propagation delay of any stage of a digital Design Perspective
system (and thus increase its speed) is to scale up the

(W/L)’s of that particular stage.
However, this is not straightforward. It should be noted that

a digital system consists of a cascade of inverters or
equivalent inverters. If the j-th stage out of N cascaded
stages is chosen, increasing the (W/L) of that stage will
increase the charging and discharging time of the (j + 1)-th
stage, but it will also increase the load presented to the
(j − 1)-th stage. This might result in an overall increase in
the system delay.
A Word on Capacitive Loading... The Digital CMOS
Inverter
Anurup Mitra
Introduction
All the components of the inverter load cap discussed so far
Delay Estimation
can be split into two broad categories - the intrinsic load
Design Perspective
Cint (diffusion and overlap caps), and the extrinsic load Cext
(wire and connecting gate caps).
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
(wire and connecting gate caps). The propagation delay can
be expressed as

Cext
tp = 0.69Req (Cint + Cext ) = tp0 1 +
Cint
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
be expressed as

Cext
Cint
Here tp0 represents the delay of the inverter loaded only by
its intrinsic capacitance and is hence called the the intrinsic
or unloaded delay.
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
be expressed as

Cext
Cint
Here tp0 represents the delay of the inverter loaded only by
its intrinsic capacitance and is hence called the the intrinsic
or unloaded delay.
It can be empirically established that
Cint = γCg (= Cox Wn Ln + Cox Wp Lp ) and γ is a correction
factor very close to unity.
Inverter
With the approximation we can now write Anurup Mitra
Introduction
Cext f
tp = tp0 1 + = tp0 1 + Delay Estimation
γCg γ Design Perspective
Inverter
Introduction
Cext f
This establishes that the delay of an inverter is purely a

function of the ratio between its external load cap and
its input cap. This ratio f , is termed the effective fan-out.
Inverter
Introduction
Cext f

The fan-out of a digital inverter or equivalent inverter
denotes the number of load gates that are connected to the
output of the driving gate. A large fan-out can deteriorate
the dynamic performance of the gate because of the added
capacitance at the output which needs to be charged or
discharged.
Inverter
Introduction
Cext f

The fan-out of a digital inverter or equivalent inverter
denotes the number of load gates that are connected to the
output of the driving gate. A large fan-out can deteriorate
the dynamic performance of the gate because of the added
capacitance at the output which needs to be charged or
discharged.
It should also be mentioned here that the fan-in of a gate is
defined as the number of inputs to the gate. A large fan-in
tends to make the construction of the gate more complex
and degrades both the static and dynamic performance.
Inverter Sizing... The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
The goal is to minimise the delay of an inverter chain which

is representative of a typical digital system. The input cap is
denoted by Cg 1 and the final load cap is CL .
Inverter Sizing... The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
The goal is to minimise the delay of an inverter chain which

is representative of a typical digital system. The input cap is
denoted by Cg 1 and the final load cap is CL .
The delay of the j-th inverter stage is given by

Cg ,j+1 fj
tp,j = tp0 1 + = tp0 1 +
γCg ,j γ
Hence, the total delay through the system is
N N
X X Cg ,j+1
tp = tp,j = tp0 1+
γCg ,j
j=1 j=1
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
The minimum delay is found by equating N-1 partial

derivatives to 0 and obtaining a set of constraints
Cg ,j+1 Cg ,j
= ; j = 2...N
Cg ,j Cg ,j−1
p
Cg ,j = Cg ,j−1 Cg ,j+1
The optimum size of each inverter is the geometric mean
of its neighbour’s sizes.
Stage Ratio The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
This means that each inverter has a scale-up factor of f with
Design Perspective
respect to the preceding stage, the same effective fan-out
and hence the same delay.
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
Denoting the CL /Cg 1 ratio by F , we have
√
N
f = F
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
√
N
f = F
The minimum delay is achieved as
√
N
!
F
tp = Ntp0 1+
γ
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
√
N
f = F
The minimum delay is achieved as
√
N
!
F
tp = Ntp0 1+
γ
F is called the effective fan-out and f , the stage ratio.
Optimised Number of Stages The Digital CMOS
Inverter
Anurup Mitra
√
N
!
F Introduction
tp = Ntp0 1+ Delay Estimation
γ
Design Perspective
An optimum value has to be chosen for the number of

stages N.
Inverter
Anurup Mitra
√
N
!
F Introduction
γ
Design Perspective

stages N. If N is too large, Ntp0 becomes dominant and the
intrinsic delay of the stages dominates.
Inverter
Anurup Mitra
√
N
!
F Introduction
γ
Design Perspective

intrinsic delay of the stages dominates. If N is too small, the
effective fan-out becomes excessively large.
Inverter
Anurup Mitra
√
N
!
F Introduction
γ
Design Perspective

Differentiating the delay expression with respect to the
number of stages and equating to 0, we attain
√
√
N
N
F ln F
γ+ F− =0
N
γ
or , f = exp 1 +
f
Inverter
Anurup Mitra
√
N
!
F Introduction
γ
Design Perspective

Differentiating the delay expression with respect to the
number of stages and equating to 0, we attain
√
√
N
N
F ln F
γ+ F− =0
N
γ
or , f = exp 1 +
f
This equation has to be solved numerically and gives an
optimum value of 4 for f .
Rise and Fall Times of the Input The Digital CMOS
Inverter
Anurup Mitra
All expressions for delay derived so far assumes zero rise and
Introduction
fall times for the input signal. When the actual rise and fall
Delay Estimation
times are considered the delay expressions also get modified
Design Perspective
accordingly.
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
accordingly.
For a single digital stage, the following correction is often
used.
r
t 2
2 r
tpHL,actual = tpHL,step +
2
r
t 2
2 f
tpLH,actual = tpLH,step +
2
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective
accordingly.
For a single digital stage, the following correction is often
used.
r
t 2
2 r
tpHL,actual = tpHL,step +
2
r
t 2
2 f
tpLH,actual = tpLH,step +
2
For an inverter chain topology, we use
tpi = tp,step
i i−1
+ ηtp,step
where η is an empirical constant around 0.25.
Something The Digital CMOS
Inverter
Anurup Mitra
Introduction
Delay Estimation
Design Perspective

CMOS Inverter - Dynamic Characteristics

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

CMOS Inverter - Dynamic Characteristics

Hochgeladen von

Copyright:

Verfügbare Formate

The Digital CMOS

The delay of the CMOS inverter is a performance metric for Introduction

The output waveform shows a distinct RC charging and

The output waveform shows a distinct RC charging and

The green waveform indicates the short circuit current that

The output waveform shows a distinct RC charging and

The green waveform indicates the short circuit current that

the delay incurred, the capacitances need to be linearised Delay Estimation

and lumped together at the output. Design Perspective

the delay incurred, the capacitances need to be linearised Delay Estimation

and lumped together at the output. Design Perspective

The most fundamental delay in digital circuits is the unit

As the output of an inverter swings from HIGH to LOW or Delay Estimation

might travel through various regions of operation, namely

As the output of an inverter swings from HIGH to LOW or Delay Estimation

might travel through various regions of operation, namely

As the output of an inverter swings from HIGH to LOW or Delay Estimation

might travel through various regions of operation, namely

steady state values. Delay Estimation

steady state values. Delay Estimation

steady state values. Delay Estimation

steady state values. Delay Estimation

steady state values. Delay Estimation

steady state values. Delay Estimation

steady state values. Delay Estimation

Now that we can estimate the capacitance and resistance Introduction

associated with the charging/discharing of the output of an Delay Estimation

viewing the output as a first-order RC network.

Now that we can estimate the capacitance and resistance Introduction

associated with the charging/discharing of the output of an Delay Estimation

viewing the output as a first-order RC network.

Hence, the rise and fall times are estimated as follows:

tpHL = 0.69Reqn Ceq

tpLH = 0.69Reqp Ceq

Assuming velocity saturation, the Req of an MOS device is Introduction

given as Delay Estimation

Assuming velocity saturation, the Req of an MOS device is Introduction

given as Delay Estimation

Assuming velocity saturation, the Req of an MOS device is Introduction

given as Delay Estimation

The charge down is determined by the nMOS device. Thus

The charge down is determined by the nMOS device. Thus

The charge down is determined by the nMOS device. Thus

It might be tempting to think that the easiest way to Delay Estimation

decrease the propagation delay of any stage of a digital Design Perspective

system (and thus increase its speed) is to scale up the

It might be tempting to think that the easiest way to Delay Estimation

decrease the propagation delay of any stage of a digital Design Perspective

system (and thus increase its speed) is to scale up the

However, this is not straightforward. It should be noted that

With the approximation we can now write Anurup Mitra

With the approximation we can now write Anurup Mitra

This establishes that the delay of an inverter is purely a

With the approximation we can now write Anurup Mitra

This establishes that the delay of an inverter is purely a

With the approximation we can now write Anurup Mitra

This establishes that the delay of an inverter is purely a

The goal is to minimise the delay of an inverter chain which

The goal is to minimise the delay of an inverter chain which

The minimum delay is found by equating N-1 partial

An optimum value has to be chosen for the number of

An optimum value has to be chosen for the number of