Ese570 Intro10

1
http://www.seas.upenn.edu/~ese570/
Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

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3
Course Introduction
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● TOPICS
●
Industry Trends
●
● Digital CMOS Basics
● Some VLSI Fundamentals
● Illustrative Design Example

5
Industry Trends
Kenneth R. Laker, University of Pennsylvania

Pennsylvania, updated 19Jan10
6
“Moore's Law” Impact on Intel Micro-Computers
8-Core “Nehalem-
EX” processor –
45nm, 2.3 BT (2010)
1971 1980 1990 2000 2009

7
1st 2B transistor µP (Intel Itanium) chip

targeted for Q1 2010 manufacture.
Serial data links operating at 10 Gbits/sec.
Increased reuse of logic IP, i.e. designs

and cores.
0.032  m
YEAR
2010
8
Moore's Law and More

9
Improvement Trends for VLSI SoCs Enabled by

Geometrical and Equivalent Scaling
TRENDS
1. Higher Integration level -> exponentially increased number of
components/transistors per chip.
2. Performance Scaling -> combination of Geometrical (shrinking of
dimensions) and Equivalent (innovation) Scaling.
3. System implementation -> SoC + increased use of SiP
4. Higher Speed -> CPU clock rate at multiple GHz.
5. Increased Compactness -> Smaller and lighter weight electronic
products
6. Lower Power -> Increased laptop, cell phone and PDA battery
life. Decreasing energy requirement per function.
7. Lower Cost -> Decreasing cost per function.

SOC Multi-Core/Accelerator Engine Architecture 10
for Networking & Server Apps
http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007_SystemDrivers.pdf
● Die area is constant
● Number of cores increases by 1.4X / year
● Core frequency increases by 1.05X / year
● On-demand accelerator engine frequency increases by 1.05X / year
● Underlying fabrics – logic, embedded memory, on-chip switching
fabric, and system interconnect – scale consistently with number of cores.

11
MC/AE SOC Platform Performance with # of Cores
System performance (normalized to 4-core in 2007)

# of cores (4-cores in 2007)
54X system performance
30 cores
http://www.itrs.net/Links/2007ITRS/2007_Chapters/2007
_SystemDrivers.pdf

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Digital CMOS Basics

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Classification of Digital CMOS Circuits
STATIC DYNAMIC
CIRCUITS CIRCUITS
● STATIC CIRCUIT
● In steady-state the output is always at a “1” or “0” via a low-
impedance path to VDD or GND, respectively.

DYNAMIC CIRCUIT
● In steady-state the output is at “1” or “0” due to the presence or
absence of charge, respectively, stored on the output node.

14

15

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Ideal nMOS and pMOS Characteristics
High Impedance or High Z
g=0 g=1
g g
g=1 g=1
g=0 g=0
g g
g=1 g=0
High Impedance or High Z

17
Complementary CMOS Switch
-g
g g
-g -g
g g

18
Ideal CMOS Inverter
Inverter Truth Table

19
Two-Input CMOS NAND Gate
DeMorgan's Theorem
 A⋅B = A B
 A B
F= A⋅B
 A⋅B

20
Two-Input CMOS NOR Gate
DeMorgan's Theorem
 A B= A⋅B
 A⋅B 
 A B

21
Constructing Compound CMOS Gates
F = A⋅BC⋅D
N-Half Circuit F
F = A⋅BC⋅D
F = AB⋅C D

P-Half Circuit
F
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F = A⋅B C⋅D
Combing the N-Half

and P-Half Circuits

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output = A⋅sB⋅s

24
Some VLSI Fundamentals

25
VLSI Hierarchical Representations
fabricated?

26
Typical Digital VLSI Design Abstractions

Consistent Abstractions in Three Domains 27
Application Specs.
Architecture,
e.g. RISC Processor
Architectural
Abstraction
Level
Chip, SoC, SiP

28
Goal of All VLSI Design Enterprises
Convert System Specs into an SOC DESIGN in MINIMUM

TIME and with MAXIMUM LIKLIHOOD that the Design
will PEFORM AS SPECIFIED when fabricated.

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CMOS CHIP MANUFCTURING STEPS

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Basic VLSI Chip Cost Model
mask set, all indirect costs.

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VLSI Design Cycle or Flow

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Illustrative Circuit Design Example
Design a One-Bit Adder Circuit using 00.8

8µmtwin-well
twin-wellCMOS
CMOSTechnology.
technology. The
The
design specifications are:
1. Propagation Delay Times of SUM and CARRY_Out signals: ≤ 1.2 ns
2. Rise and Fall Times of SUM and CARRY_Out signals: ≤ 1.2 ns
3. Circuit Die Area: ≤ 1500  m 2
4. Dynamic Power Dissipation (@ VDD = 5 V and f max = 20 MHz): ≤ 1 mW
5. Functional

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Bit-Sliced Data Path

Control
Bit N
Data IN Data OUT

Register ADDER Shifter Multiplier
Bit 0

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Illustrative Circuit Design Example

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Two-Input Exclusive OR Gate

In Out = F
A A B A+B
output
0 0 0
XOR 0 1 1
B F = A+ B 1 0 1
1 1 0
F = A + B = A⋅B A⋅B
In F1 In Out = F2
Three-Input Exclusive OR Gate A B A+ B C A+ B+ C
0 0 0 0 0
A F1 0 1 1 0 1
XOR output 1 0 1 1 0
B XOR 1 1 0 1 1
C F2 = A + B + C
 AB⋅ AB
F2 = A + B + C = F 1⋅C F 1⋅C = A⋅BA⋅B⋅C A⋅B A⋅B ⋅C
0 0
= A⋅B⋅C A⋅B⋅C A⋅AA⋅BA⋅BB⋅B⋅C
= A⋅B⋅C A⋅B⋅C A⋅B⋅C A⋅B⋅C
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Gate Level Schematic of One-Bit Full Adder Circuit
 A B⋅C  A⋅B
 A BC ⋅CARRYOUT
A⋅B⋅C  A BC ⋅CARRYOUT
Kenneth R. Laker, University of Pennsylvania,

Pennsylvania updated 19Jan10
37
Show SUMOUT = A⋅B⋅C  A BC ⋅CARRYOUT = A+ B+ C
CARRYOUT = AB⋅C A⋅B= A⋅C B⋅C  A⋅B

Using DeMorgan's Theorem
CARRYOUT = A⋅C  B⋅C  A⋅B= A⋅C ⋅B⋅C ⋅ A⋅B

=  A⋅C ⋅ B⋅C ⋅ A⋅B= AC ⋅ BC ⋅ AB
=  A⋅B A⋅C C⋅BC ⋅ A B
=  A⋅B A⋅C  A⋅B⋅C  A⋅C  A⋅B A⋅B⋅C  B⋅C B⋅C 
= A⋅B A⋅C A⋅B⋅C B⋅C
SUMOUT = A⋅B⋅C  A BC ⋅CARRYOUT

= A⋅B⋅C  A BC ⋅ A⋅B A⋅C  A⋅B⋅C B⋅C 
= A⋅B⋅C  A⋅B⋅C  A⋅B⋅C A⋅B⋅C

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8-bit Ripple Adder
a<7:0>
b<7:0>
VDD
cin cout
clk
GND
1-bit sum<7:0>
Adder a b vdd
Cell
cin BFA cout
gnd sum
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Transistor Level Schematic of One-Bit Full Adder Circuit
COUT
 AB⋅C  A⋅B
SUMOUT
COUT  ABC ⋅COUT
A⋅B⋅C ABC ⋅COUT

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Initial Layout of One-Bit Full Adder Circuit
COUT
SUMOUT
N1 N2
N1 N1 N2 N2
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Initial Layout of One-Bit Full Adder Circuit
2
≤ 1500  m

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Simulated Performance of One-Bit Full Adder Circuit
Spec NOT
met.

Ese570 Intro10

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1

Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

● Digital CMOS Basics

● Some VLSI Fundamentals

● Illustrative Design Example

Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

Kenneth R. Laker, University of Pennsylvania

“Moore's Law” Impact on Intel Micro-Computers

1971 1980 1990 2000 2009

Kenneth R. Laker, University of Pennsylvania

1st 2B transistor µP (Intel Itanium) chip

Serial data links operating at 10 Gbits/sec.

Increased reuse of logic IP, i.e. designs

Moore's Law and More

Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

Improvement Trends for VLSI SoCs Enabled by

Kenneth R. Laker, University of Pennsylvania

for Networking & Server Apps

● Core frequency increases by 1.05X / year

● On-demand accelerator engine frequency increases by 1.05X / year

● Underlying fabrics – logic, embedded memory, on-chip switching

fabric, and system interconnect – scale consistently with number of cores.

MC/AE SOC Platform Performance with # of Cores

System performance (normalized to 4-core in 2007)

54X system performance

Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

Digital CMOS Basics

Kenneth R. Laker, University of Pennsylvania

impedance path to VDD or GND, respectively.

absence of charge, respectively, stored on the output node.

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

High Impedance or High Z

Kenneth R. Laker, University of Pennsylvania

Complementary CMOS Switch

Kenneth R. Laker, University of Pennsylvania

Ideal CMOS Inverter

Inverter Truth Table

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

F = AB⋅C D

F = A⋅B C⋅D

Combing the N-Half

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

Some VLSI Fundamentals

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania

Chip, SoC, SiP

Kenneth R. Laker, University of Pennsylvania

Goal of All VLSI Design Enterprises

Convert System Specs into an SOC DESIGN in MINIMUM

Kenneth R. Laker, University of Pennsylvania

CMOS CHIP MANUFCTURING STEPS

Kenneth R. Laker, University of Pennsylvania, updated 19Jan10

Basic VLSI Chip Cost Model

mask set, all indirect costs.

Kenneth R. Laker, University of Pennsylvania

Kenneth R. Laker, University of Pennsylvania