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351
IV B.E Examination May 2009
Electronics and Instrumentation/Electronics and Telecommunication
EI4308/EC4508 VLSI Design .
Duration: 3 Hrs. Maximum Marks : 100
Min Pass Marks : 35

Note:~ Attempt any five questions. Assume suitable assumptions if necessary. Answers
must be brief and to the point.

Q.l(a) Explain PLD based VLSI designing in brief. How the designing process is different from ASIC 10
designing?
(b) Define following terms related to VLSI design in brief. 10
i) EDA tools
ii) Power relationship for IC
iii) FPGA
iv) IP Cores

Q.2(a) Explain the purpose of physical data types. Write a physical data type representing voltage in the 10
range of IJ.!Vto 100V. .
",-....
(b) Differentiate between a 2-dimensional array and an anay of array through suitable example. What 10
are the different ways of assigning values to a part of anay and to the whole array?

Q.3(a) Justify the statement "Signals inside the process statement are updated when the process goes into 10
suspended mode".
(b) What is the alternate ways other than sensitivity list to suspend the process? Write a wait statement 10
that suspends a process until signal ready changes to '1' or until a maximum of Sms has elapsed.

Q.4(a) Explain signal driver in brief. How signal drivers are updated when different types of delay models 10
are used in the VHDL code?
(b) Write a behavioral model for a T-flip flop triggered on rising edge of clock pulse. The fli~flop 10
also includes a reset pin synchronized with clock pulse.

Q.5(a) Develop a dataflow model of a 4-bit full adder using generate statements. 10
(b) Write the equivalent concurrent signal assignment statement for the following process statement. 10
process is
begin
if extendedJeset then
reset<= '1', '0' after 200ns;
~ else
reset<= '1', '0' after SOns;
end if;
wait for extended_reset;
end process;

Q.6(a) Develop a structural model for a 9-bit parity generator circuit using XOR gates. 10
(b) Differentiate between portmap statement and genericmap statement in brief using suitable 10
examples.

Q.7(a) What is meant by binding in VHDL? How late binding offers better flexibility to the programmer 10
regarding modifying the circuit characteristics?
(b) Explain subprogram overloading through suitable examples. What are the rules of resolving them? 10

Q.8 Write short notes on (any two) 20

i) Packages
ii) Concurrent vIs Sequential procedure can
iii) Multiple Processes.
iv) Direct Instantiation
v) VHDL operators.