Inverter DC Performance

CSE 462: VLSI Design

Fall 2000

Resistive Load Inverter

R IR = IDS
IR = (VCC - Vout) / R
Vout = VDS

Vin IDS

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MOSFET IV Characteristics

Load Line

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Voltage Transfer Characteristics

Effects of Load Resistance

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 CMOS Inverter

IDSp IDSp = - IDSn

D
Vin = VGSn Vout
D VDSp = Vout - VDD
= VDD + VGSp
IDSn
VDSn = Vout
S

PMOS Load Lines

IDn
V in = V DD -VGSp
IDn = - IDp
V out = VDD -VDSp

Vout

IDp IDn IDn

Vin=0 Vin=0

V in=3 Vin=3

V DSp VDSp Vout

VGSp=-2

VGSp=-5
Vin = VDD -VGSp Vout = VDD -VDSp
IDn = - IDp

Digital Integrated Circuits © Prentice Hall 1995

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 CMOS Inverter Load Characteristics

In,p
V in = 0 Vin = 5

NMOS
PMOS

Vin = 4 Vin = 1 Vin = 4

Vin = 3 Vin = 2 Vin = 3 Vin = 2

Vin = 4 Vin = 2 Vin = 1

V in = 3
Vin = 0
Vin = 5

Digital Integrated Circuits © Prentice Hall 1995

CMOS “Load Lines”

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Finding CMOS VTC--1

Finding CMOS VTC--2

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Finding CMOS VTC--3

CMOS VTC

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CMOS VTC--Spice Results

CMOS Inverter VTC

Vout NMOS off

PMOS lin
5

NMOS sat
PMOS lin
4

NMOS sat
3

PMOS sat
2

NMOS lin
PMOS sat NMOS lin
1

PMOS off

1 2 3 4 5 V in

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 DIGITAL GATES
Fundamental Parameters

l Functionality
l Reliability, Robustness
l Area
l Performance
» Speed (delay)
» Power Consumption
» Energy

Digital Integrated Circuits © Prentice Hall 1995

Noise in Digital Integrated Circuits

VDD
v(t)
i(t)

(a) Inductive coupling (b) Capacitive coupling (c) Power and ground
noise

Digital Integrated Circuits © Prentice Hall 1995

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 DC Operation:
Voltage Transfer Characteristic

V(y)
V(x) V(y)

V f
OH
V(y)=V(x)

V Switching Threshold
M

VOL

VOL V V(x)
OH

Nominal Voltage Levels

Digital Integrated Circuits © Prentice Hall 1995

Mapping between analog and digital signals

V V(y)
"1" OH Slope = -1
V V
IH OH

Undefined
Region
Slope = -1
V
IL VOL
"0"
V
OL V V V(x)
IL IH

Digital Integrated Circuits © Prentice Hall 1995

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 Definition of Noise Margins

"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"

Gate Output Gate Input

Digital Integrated Circuits © Prentice Hall 1995

The Regenerative Property

...
v0 v1 v2 v3 v4 v5 v6

(a) A chain of inverters.

v1, v3, ... v1, v3, ...

f(v) finv(v)

finv(v) f(v)

v0 , v2 , ... v0, v2, ...

(b) Regenerative gate (c) Non-regenerative gate

Digital Integrated Circuits © Prentice Hall 1995

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 The Ideal Gate

Vout

Ri = ∞

Ro = 0
g= −∞

Vin

Digital Integrated Circuits © Prentice Hall 1995

VTC of Real Inverter

5.0

4.0 NML

3.0
Vout (V)

2.0
VM
NMH
1.0

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

Digital Integrated Circuits © Prentice Hall 1995

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 Derivation of Switching Threshold

Gate Switching Threshold

4.0

3.0
VM

2.0

1.00.1 0.3 1.0 3.2 10.0

kp/kn

Digital Integrated Circuits © Prentice Hall 1995

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Derivation of Vih and Vil

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