Bus and Memory Transfers

A typical digital computer has many register and paths must be provided to transfer
information from one register to another . The number of wires will be excessive if seperate
lines are used between each register and all other registers in the system.A more efficien
scheme for transferring information between registers in a multiple register configuration is
a common bus system. A bus structure consists of a set of common lines one for each bit of
aregister, through which binary informatio is transferred one at a time .control signals
determine which register is selected by the bus during each particular register transfer.
one way of constructing a common bus system is with multiplexers.The multiplexers select
the source registre whose binary information is then placed on the bus.

A shared communication path consist of one and more lines is called bus and data transfer
through this bus is called bus transfer.What a data read from memory or stored in memory is
called memory transfer.When an information is read from memory word is called read
operation and data stored in memory is called write operation.

The computer has a "bus" where all information travels. It connects all the hardware together.
The processor(cpu) calls for a piece of information and it addresses the bus to find that
memory location and retrieve it for the operation that needed it. All of the memory cards are
hardware plugged into the bus.
Read more: http://wiki.answers.com/Q/What_is_bus_memory_transfer#ixzz1JmqCGlYJ

Introduction to the concept of a bus

A bus, in computing, is a set of physical connections (cables, printed circuits, etc.) which can be
shared by multiple hardware components in order to communicate with one another.
The purpose of buses is to reduce the number of "pathways" needed for communication between
the components, by carrying out all communications over a single data channel. This is why the
metaphor of a "data highway" is sometimes used.

If only two hardware components communicate over the line, it is called a hardware port (such
as aserial port or parallel port).
Characteristics of a bus
A bus is characterised by the amount of information that can be transmitted at once. This amount,
expressed in bits, corresponds to the number of physical lines over which data is sent
simultaneously. A 32-wire ribbon cable can transmit 32 bits in parallel. The term "width" is used
to refer to the number of bits that a bus can transmit at once.
Additionally, the bus speed is also defined by its frequency (expressed in Hertz), the number of
data packets sent or received per second. Each time that data is sent or received is called
a cycle.
This way, it is possible to find the maximum transfer speed of the bus, the amount of data which
it can transport per unit of time, by multiplying its width by its frequency. A bus with a width of 16
bits and a frequency of 133 MHz, therefore, has a transfer speed equal to:
16 * 133.106 = 2128*106 bit/s,
or 2128*106/8 = 266*106 bytes/s
or 266*106 /1000 = 266*103 KB/s
or 259.7*103 /1000 = 266 MB/s

Bus subassembly
In reality, each bus is generally constituted of 50 to 100 distinct physical lines, divided into three
subassemblies:

• The address bus (sometimes called the memory bus) transports memory addresses
which the processor wants to access in order to read or write data. It is a unidirectional bus.
• The data bus transfers instructions coming from or going to the processor. It is a
bidirectional bus.
• The control bus (or command bus) transports orders and synchonisation signals coming
from the control unit and travelling to all other hardware components. It is a bidirectional bus,
as it also transmits response signals from the hardware.

The primary buses

There are generally two buses within a computer:

• the internal bus (sometimes called the front-side bus, or FSB for short). The internal bus
allows the processor to communicate with the system's central memory (the RAM).
• the expansion bus (sometimes called the input/output bus) allows various motherboard
components (USB, serial, and parallel ports, cards inserted in PCI connectors, hard drives,
CD-ROM and CD-RW drives, etc.) to communicate with one another. However, it is mainly
used to add new devices using what are called expansion slots connected to the
input/outpur bus.
The chipset
A chipset is the component which routes data between the computer's buses, so that all the
components which make up the computer can communicate with each other.
The chipset originally was made up of a large number of electronic chips, hence the name. It
generally has two components:
• The NorthBridge (also called the memory controller) is in charge of controlling transfers
between the processor and the RAM, which is way it is located physically near the processor.
It is sometimes called the GMCH, forr Graphic and Memory Controller Hub.
• The SouthBridge (also called the input/output controller or expansion controller) handles
communications between peripheral devices. It is also called the ICH (I/O Controller Hub).
The tembridge is generally used to designate a component which connects two buses.

It is interesting to note that, in order to communicate, two buses must have the same width. The
explains why RAM modules sometimes have to be installed in pairs (for example, early Pentium
chips, whose processor buses were 64-bit, required two memory modules each 32 bits wide).
Here is a table which gives the specifications for the most commonly used buses:

Standard Bus width (bits) Bus speed (MHz) Bandwidth (MB/sec)

ISA 8-bit 8 8.3 7.9
ISA 16-bit 16 8.3 15.9
EISA 32 8.3 31.8
VLB 32 33 127.2
PCI 32-bit 32 33 127.2
PCI 64-bit 2.1 64 66 508.6
AGP 32 66 254.3
AGP (x2 Mode) 32 66x2 528
AGP (x4 Mode) 32 66x4 1056
AGP (x8 Mode) 32 66x8 2112
ATA33 16 33 33
ATA100 16 50 100
ATA133 16 66 133
Serial ATA (S-ATA) 1 180
Serial ATA II (S-ATA2) 2 380
USB 1 1.5
USB 2.0 1 60
FireWire 1 100
FireWire 2 1 200
SCSI-1 8 4.77 5
SCSI-2 - Fast 8 10 10
SCSI-2 - Wide 16 10 20
SCSI-2 - Fast Wide 32 bits 32 10 40
SCSI-3 - Ultra 8 20 20
SCSI-3 - Ultra Wide 16 20 40
SCSI-3 - Ultra 2 8 40 40
SCSI-3 - Ultra 2 Wide 16 40 80
SCSI-3 - Ultra 160 (Ultra
16 80 160
3)
SCSI-3 - Ultra 320 (Ultra
16 80 DDR 320
4)
SCSI-3 - Ultra 640 (Ultra
16 80 QDR 640
5)

The memory bus is used to transfer information between the CPU and main memorythe RAM in your system. This
bus is usually connected to the motherboard chipset North Bridge or Memory Controller Hub chip. Depending on
the type of memory your chipset (and therefore motherboard) is designed to handle, the North Bridge runs the
memory bus at various speeds. The best solution is if the memory bus runs at the same speed as the processor
bus. Systems that use PC133 SDRAM have a memory bandwidth of 1066MBps, which is the same as the 133MHz
CPU bus. In another example, Athlon systems running a 266MHz processor bus also run PC2100 DDR-SDRAM,
which has a bandwidth of 2133MBpsexactly the same as the processor bus in those systems. Systems running a
Pentium 4 with its 400MHz processor bus also use dual-channel RDRAM memory, which runs 1600MBps for each
channel, or a combined bandwidth (both memory channels run simultaneously) of 3200MBps, which is exactly
the same as the Pentium 4 CPU bus. Pentium 4 systems with the 533MHz bus run dual-channel DDR PC2100 or
PC2700 modules, which match or exceed the throughput of the 4266MBps processor bus.

Running memory at the same speed as the processor bus negates the need for having cache memory on the
motherboard. That is why when the L2 cache moved into the processor, nobody added an L3 cache to the
motherboard. Some very high-end processors, such as the Itanium and Itanium 2 and the Intel Pentium 4
Extreme Edition, have integrated 2MB4MB of full-core speed L3 cache into the CPU. However, the most recent
high-performance chips, such as the new Pentium Extreme Edition, use only L1 and L2 cache. Thus, it appears
that L2 cache will continue to be the most common type of secondary cache for the foreseeable future.

the need for expansion slots

The I/O bus or expansion slots enable your CPU to communicate with peripheral devices. The bus and its
associated expansion slots are needed because basic systems can't possibly satisfy all the needs of all the people
who buy them. The I/O bus enables you to add devices to your computer to expand its capabilities. The most
basic computer components, such as sound cards and video cards, can be plugged into expansion slots; you also
can plug in more specialized devices, such as network interface cards, SCSI host adapters, and others.

Note

In most modern PC systems, a variety of basic peripheral devices are built in to the motherboard. Most systems
today have at least dual (primary and secondary) IDE interfaces, four USB ports, a floppy controller, two serial
ports, a parallel port, keyboard, and mouse controller built directly into the motherboard. These devices are
usually distributed between the motherboard chipset South Bridge and the Super I/O chip.

Many add even more items, such as a built-in sound card, video adapter, SCSI host adapter, network interface or
IEEE 1394a port, that also are built in to the motherboard. Those items, however, might not be built in to the
motherboard chipset or Super I/O chip; they are sometimes configured as additional chips installed on the
board. Nevertheless, these built-in controllers and ports still use the I/O bus to communicate with the CPU. In
essence, even though they are built in, they act as if they were cards plugged into the system's bus slots,
including using system resources in the same manner.
Direct Memory Access (DMA) Modes and Bus Mastering DMA

As described in the page describing programmed I/O, that method of

transferring data between the hard disk and the rest of the system has a serious
flaw: it requires a fair bit of overhead, as well as the care and attention of the
system's CPU. Clearly, a better solution is to take the CPU out of the picture
entirely, and have the hard disk and system memory communicate
directly. Direct memory access or DMA is the generic term used to refer to a
transfer protocol where a peripheral device transfers information directly to or
from memory, without the system processor being required to perform the
transaction. DMA has been used on the PC for years over the ISA bus, for
devices like sound cards and the floppy disk interface. Conventional DMA uses
regular DMA channels which are a standard system resource. DMA is
discussed in full detail here.

Several different DMA modes have been defined for the IDE/ATA interface;
they are grouped into two categories. The first set of modes are single
word DMA modes. When these modes are used, each transfer moves just a
single word of data (a word is the techie term for two bytes, and recall that the
IDE/ATA interface is 16 bits wide). There are (or were!) three single word
DMA modes, all defined in the original ATA standard:

Maximum
Cycle Time
DMA Mode Transfer Rate Defining Standard
(nanoseconds)
(MB/s)

Single Word
960 2.1 ATA
Mode 0

Single Word
480 4.2 ATA
Mode 1

Single Word
240 8.3 ATA
Mode 2

(As I discussed in the page on PIO, maximum transfer rate is double the
reciprocal of the specific cycle time for each mode.) Obviously, these are not
impressive transfer rate numbers by today's standards. Further, performing
transfers of a single word at a time is horribly inefficient--each and every
transfer requires overhead to set up the transfer. For that reason, single word
DMA modes were quickly supplanted by multiword DMA modes. As the name
implies, under these modes a "burst" of transfers occurs in rapid succession,
one word after the other, saving the overhead of setting up a separate transfer
for each word. Here are the multiword DMA transfer modes:

Maximum
Cycle Time
DMA Mode Transfer Rate Defining Standard
(nanoseconds)
(MB/s)

Multiword
480 4.2 ATA
Mode 0

Multiword
150 13.3 ATA-2
Mode 1

Multiword
120 16.7 ATA-2
Mode 2

Since multiword DMA transfers are more efficient, and also have higher
maximum transfer rates, single word DMA modes were quickly abandoned
after ATA-2 was widely adopted--they were actually removed from the ATA
standards in ATA-3. So all DMA accesses today (including Ultra DMA) are
actually multiword; the term "multiword" is now often assumed and no longer
specifically mentioned.

Another important issue with DMA is that there are in fact two different ways
of doing DMA transfers. Conventional DMA is what is called third-party
DMA, which means that the DMA controllers on the motherboard coordinate
the DMA transfers. (The "third party" is the DMA controller.) Unfortunately,
these DMA controllers are old and very slow--they are basically unchanged
since the earliest days of the PC. They are also pretty much tied to the old ISA
bus, which was abandoned for hard disk interfaces for performance reasons.
When multiword DMA modes 1 and 2 began to become popular, so did the use
of the high-speed PCI bus for IDE/ATA controller cards. At that point, the old
way of doing DMA transfers had to be changed.

Modern IDE/ATA hard disks use first-party DMA transfers. The term "first
party" means that the peripheral device itself does the work of transferring data
to and from memory, with no external DMA controller involved. This is also
called bus mastering, because when such transfers are occurring the device
becomes the "master of the bus". Bus mastering allows the hard disk and
memory to work without relying on the old DMA controller built into the
system, or needing any support from the CPU. It requires the use of the PCI
bus--older buses like MCA also supported bus mastering but are no longer in
common use. Bus-mastering DMA allows for the efficient transfer of data to
and from the hard disk and system memory. Bus mastering DMA keeps CPU
utilization low, which is the amount of work the CPU must do during a transfer.
Interestingly, despite the obvious advantages of bus mastering DMA, the use of
bus-mastering multiword DMA mode 2 never really caught on. There are
several reasons for this. The most important was the poor state of support for
the technology for the first couple of years. Using PIO required no work and
was very simple; DMA was not supported by the first version of Windows 95,
so special drivers had to be used. Problems with implementing bus mastering
DMA on systems in the 1996 to 1998 time frame were numerous: issues with
buggy drivers, software the didn't work properly, CD-ROM drives that
wouldn't work with the drivers, and so on. In the face of these problems, DMA
didn't offer much incentive to make the switch. Sure, the lower CPU utilization
was good, but since the maximum DMA mode's speed was the same as that of
the highest PIO mode (16.7 MB/s) there wasn't a great perception that DMA
offered much of an advantage over PIO. Given little upside potential, many
people (including this author) stayed away from using DMA, to avoid the
compatibility and stability problems that sometimes resulted.

Bus mastering DMA finally came into its own when the industry moved on to
Ultra DMA. Once Ultra DMA/33 doubled the interface transfer rate, DMA had
an obvious speed advantage over PIO in addition to its other efficiency
improvements. Support for DMA was also cleaned up and made native in
Windows 9x, and most of the problems with the old drivers were eliminated.
Today, the use of Ultra DMA is the standard in the industry. See here for
details on the Ultra DMA modes.

What Is a Memory Bus?

he memory bus connects the memory system and the northbridge area of the chipset. This
section of the chipset also connects directly to the central processing unit and the graphics
system. While this means the northbridge is the center of many important computer functions, it is
actually the computer’s memory that determines the bus’s speed. In essence, the speed of the
computer’s memory creates the speed of the memory bus, which determines the speed of the
rest of the system.

In computing, a bus transfers information from one location to another. Most modern computers
have a large number of buses that cross-connect all sorts of different areas. The northbridge area
of the chipset has four main buses. The front side busconnects to the central processing unit, the
graphics bus connects to the graphic system, the internal bus connects to thesouthbridge section
of the chipset, and the memory bus connects to the computer’s memory.

Each of these busses act independently of one another in most cases. The biggest exception to
this is the front side bus and the memory bus. These control the most essential parts of the
computer’s operations, and they are tied directly together. The speed of the
computer’s memory dictates the speed at which information flows across the memory bus. This
means that the processor is only able to send and receive information as quickly as
the memory bus allows.

Using memory that is slower than the processor will have a direct impact on a computer’s speed.
Basic calculations will often sit idle and occupy processor space while they wait for follow-up
information. This can create periods of latency, even on a fast computer. Oddly, more strenuous
operations are rarely affected by a slow memory bus, as the time it takes for the processor to
compete its operations is often greater than the transferal time.

On a technical level, the memory bus is made of two parts. The data bus transfers information
between the memory and the chipset. This portion of the bus is often incorrectly referred to as
the memory bus, as it does the job most often associated with that part.

The second part of the memory bus is the address bus. The address bus tells the system where
information may be stored as it comes into memory and where the information is when it needs to
leave memory. The speed of the address bus affects every action on a computer, since all
applications need some access to the memory. Regardless of how fast that information comes
and goes from the system, it is limited by the speed at which the address bus directs it.

• The largest animal that ever lived is also currently living -- the blue whale.
• The world consumes 2 quarts (approx. 2 liters) of oil per person, per day.
• If Earth was the size of a basketball, the moon would be the size of a
tennis ball and they'd be 25 feet apart.
• Of all the people in history that have reached 65 years of age, half of them
are living right now.
• If Earth's life was compressed into one year, then humans would have
been around for only 2 seconds.
• The Middle East's population almost tripled over the last 30 years.

Apparatus for controlling data transfer between a

bus and memory array and method for operating
same
A structure and method of controlling data transfer between a memory and a bus. For write operations, a
write buffer is coupled between the bus and the memory array. Data that has been transferred into the write
buffer is transferred from the write buffer to the memory array at a faster rate than data is transferred from
the bus to the write buffer. For read operations, a read buffer is coupled between the bus and the memory
array. Data is transferred from the memory array to the read buffer at a faster rate than data is transferred
from the read buffer to the bus.

Memory busI/O busThe I/O bus has historically been the slowest of allbuses,
and the main focus when computer designengineers try to improve bus
speeds.Processor BusThe processor bus is communications path betweenthe
CPU and the main bus. It is also used forcommunications between the
CPU and the processorsupport chipset. The processor support chipset
 includeschips such as an external memory cache and the buscontroller chip
found on some microcomputers. Thesize of the processor bus matches the size
of the datawords used by CPU. For example, the 80486DX chipuses 32-bit
words; therefore the processor bus has 32data lines, 32 address lines, and the
control lines. ThePentium processors have 64-bit words and use 32-
bitaddresses. Processor buses can have a maximum datatransfer rate of the
motherboard clock.Memory BusThe memory bus transfers data between the
RAMand the CPU. This bus can be the processor bus or willbe implemented
by a dedicated chipset that controls thememory bus.In most computers
that have amotherboard clock that is faster then 16MHz, a specialmemory
controller chipset will control the memory bus.Address BusThe address bus
transfers the next memory or I/Oaddress to be used in the next data transfer.
The addressbus in 486 and Pentium systems is 32 bits wide.I/O BusesTo
thoroughly understand the I/O buses used inmodem microcomputer
systems, an understanding ofthe development and evolution of bus systems
isrequired. The microcomputer’s architecture is directlyrelated to the type of
buses in the computer. Originally,microcomputers used a bus system called
the S-100 bus.Using this system, any board could be plugged into anyopen slot.
The S-100 bus has 62 lines, each connect toeach of the 62-pin connectors.
This system dedicatedeight lines for the eight data bits used in the Intel
8088microprocessor.Twenty lines are used for memoryaddressing. The same
20 lines are also used to addressI/O devices. A control line determines whether
the dataon these 20 lines will be a memory address or an I/Oaddress. There are
also several control lines and powerdistribution lines.The S-100 bus also
provided four lines to designatechannels for Direct Memory Accessing (DMA).
ADMA channel allows a device, such as the hard drive,to transfer data directly
into RAM, vice transferringdata to the CPU and then having the CPU transfer it
tothe RAM. The DMA channel number identifies whichdevice is requesting
and transferring data on the databus.Buses also need to be clocked to properly
transferdata. The early microcomputer buses were designed torun at the speed
of the microprocessor that was installedon the board. The 4.7 MHZ 8088
microprocessor clockwas also used to clock the bus. The 7.16
MHZmicroprocessor clocked the bus at the same rate. TheISA standard set the
bus clock speed at 8 MHZ. Tomaintain compatibility with the older
controller boards,this speed is still common in many computers today.This
speed is fine when getting input from a mouse ora keyboard, even for most disk
drives. The biggestproblem with bus speeds has occurred because of
theincrease in video resolution, the development of videocapture boards and
some network interfaces.INDUSTRY STANDARD ARCHITECTURE(ISA). —As the
microcomputer evolved, the eight datalines and 20 address lines became
insufficient to handlethe increased data capacity of the 16-bit processor.
Thisled to the development of the Industry StandardArchitecture (ISA). To
be compatible with the boardsused in eight-bit computers, an additional 36-
wireconnector was added to the circuit boards and the bus.This added eight
more data lines, four more addresslines, four more DMA channels, and five
more IRQchannels.LOCAL BUSES. —A local bus is a bus that is adedicated path between
the processor and a specificboard. There are several local buses built into
varioustypes of computers to increase the speed of datatransfers. Local
buses for expanded memory and videoboards are the most common.Some
high-endcomputers also provide a local bus for the hard drive.The VESA
Local Bus is one of the more popularbuses and was developed to increase the
speed of datatransfer between memory and the video processingboard
(video graphics adapter). VESA stands for VideoElectronics Standards
Association. The VESA LocalBus is a direct bus that connects the video
processor