Assignment No.

– 10
Assignment No.:10 a(i)

Title: Addition of n 8-bit numbers

Aim: To write a program to add n, 8 bits numbers found in internal RAM locations 40H
onwards and store results in R6 and R7.

Objective: i) To perform arithmetic operations using 8051

ii) To learn internal memory access of 8051

Theory: The 8051 memory is divided into the following 4 physical parts as shown in
figure 1.
1. Internal RAM
2. Internal special function registers
3. External RAM
4. Internal and external ROM

Addresses
7F General
Purpose
30 Area
2F Bit
Address
20 Area
1F Register
18 Bank 3
17 Register
10 Bank 2
0F Register
08 Bank 1
07 Register
00 Bank 0
Fig. 1Internal RAM

Here we need to access internal memory to take input and to store the output.

Internal RAM: Internal memory organization is shown in fig.1. It is divided into three
distinct areas:
1) 32 bytes from address 00H to 1FH that make up 32 working registers organized as 4
banks of eight registers each. The 4 registers banks are numbered 0 to 3 and are made up
of 8 registers named R0 to R7. Each register can be addressed by name or by its RAM
address. Bits RS0 and RS1 in the PSW determine which bank of registers is currently in
use at any time when the program is running. Bank 0 is selected on reset.
 7 6 5 4 3 2 1 0
CY AC F0 RS1 RS0 OV ------ P
The Program Status Word (PSW) Special Function Register

Bit Symbol Function

7 CY Carry flag
6 AC Auxiliary Carry flag
5 F0 User flag 0
4 RS1 Register bank select bit 1
3 RS0 Register bank select bit 0
RS1 RS0
0 0 Select register bank 0
0 1 Select register bank 1
1 0 Select register bank 2
1 0 Select register bank 3
2 OV Overflow flag
1 ---- Reserved for future use
0 P Parity flag
Bit addressable as PSW.0 to PSW.7

2) A bit addressable area of 16 bytes occupies RAM byte addresses 20H to 2FH forming
a total of 128 addressable bits. An addressable bit may be specified by its bit address of
00H to 7FH or byte address from 20H to 2FH. Addressable bits are useful when the
program need only remember a binary event.

3) A general purpose RAM area above the bit area from 30H to 7FH, addressable as
bytes.

Instructions used:

1) MOV dest, src

This instruction copies a byte from source location to the destination. There are fifteen
possible combinations for the instruction. It does not affect flags.

MOV A, Rr Copy data from register Rr to register A

MOV Rr, A Copy data from register A to register Rr.
Rr can be any register from R0 to R7
Here register addressing mode is used. A data MOV does not alter the contents of the
data source address. A copy of the data is made from source and moved to the
destination address. The contents of the destination are replaced by the source contents.

e. g. MOV R1, A Copy data from register A to register R1

MOV A, R1 Copy data from register R1 to register A
2) ADD A, src
This instruction adds the source byte to the accumulator (A) and places the result in A.
Since A register is one byte in size, the source operands must also be one byte. All
addition is done with the A register as the destination of the result.

ADD A, Rr Add A and register Rr put the sum in A

If there is a carry out of bit position 7, it is cleared to 0 otherwise
AC flag is set to 1 if there is a carry out of bit position 3, it is cleared otherwise
OV flag is set to 1 if there is a carry out of position 7 but none from D6 to D7
And if there is a carry from D6 to D7 and no carry out of D7.
e. g. ADD A, R4 Add A and register R4 put the sum in A

Some instructions include the carry flag as an additional source of a single bit that is
included in the operation at the least significant bit position.

ADDC A, #n Add the contents of A, the immediate number n and the C flag, put the
sum in A
C, AC and OV flags behave exactly as they do for the ADD commands.
e .g. MOV A, #1AH
ADDC A, #10H if C=1,A=2BH
ADDC is normally used to add a carry after the LSBY addition in a multi-byte process.
3) INC byte
This instruction adds 1 to the register or memory location specified by the operand.Cy is
not affected even if value FF is incremented to 00. It supports accumulator, register,
direct and register indirect addressing modes.

INC A Add a 1 to the register A

INC Rr Add a 1 to the register Rr
DEC Rr Subtract a 1 from the register R0
There are simple arithmetic operations involving adding or subtracting a binary 1 and a
number.
e.g. INC R0 Add a 1 to the register R0
DEC R0 Subtract a 1 from the register R0

4) JNC target
Jump if no carry. The instruction examines the CY flag and if it is zero it will jump to
target address.
e.g. JNC radd Jump relative address if the Carry flag is reset to 0.

5) DJNZ byte, target

Decrement and jump if not zero. In this instruction a byte is decremented and if result is
not zero, it will jump to the target address.
e.g. DJNZ Rr,radd
Decrement register Rr by 1 and jump to the relative address if the result is not 0
6) RET
Return from subroutine. This instruction is used to return from a subroutine previously
entered by instructions LCALL or ACALL. The top two bytes of the stack are popped
into program counter (PC) and program address at new location is executed. After
popping, stack contents, the stack pointer (SP) is decremented by 2.

Input: n 8 bit numbers stored in internal RAM location 40H onwards. First location
should contain value of n.

Output: Result of addition of n 8 bit numbers stored in R6 and R7.

Algorithm:

1) Take the count of numbers to be added into one of internal registers.

2) Initialize pointer to access internal memory to access numbers to be added.
3) Initialize accumulator with zero value for addition
4) Go on adding numbers in internal memory till counter becomes zero.
Decrement count with each addition
5) Store the result of addition in respective registers

Program (With comments):

Calculations:
i) Do calculation for addition of 5(n) numbers stored in internal memory.

ii)Write signed offset calculations for jump instructions.

Conclusion: Internal memory accesses are studied by performing addition of 8 bit

numbers stored in internal memory

FAQs.
1) What is the difference between the following two instructions in terms of
addressing mode and function performed?
MOV A, #46H
MOV A, 46H
2) What address is assigned to register A?
3) How to change register bank in 8051?

References:
1. Ayala,”The 8051 Micro Controller 3rd Edition”, IE
2. Mazidi M.Gillipse J. “The 8051 Microcontroller and Embedded Systems”, Pearson
 Education, 2002, ISBN-81-7808-574-7

Prepared By: M. I. T., Pune

Assignment No.-10 (a ii)

Title: 16-bit x 8-bit multiplication

Aim: To write a program to multiply 16 bit number by 8 bit number and store the result
in internal memory location.

Objective: i) To learn internal memory access

ii) To perform 16 bit by 8 bit multiplication using 8 bit registers.

Theory:

16 bit x 8 bit Multiplication

Normal multiplication

Consider 25 x 16
Step1: First multiply by the least significant digit 25 x 6= 150
Here take 15 as a carry since it exceeds the number of digits in “6” i. e. 1
Keep 0 as the least significant digit of the answer.

Step 2: Now multiply 25 by the most significant digit 25 x 1= 25

Step 3: Now add the carry to this number 25+15=40

Therefore the answer becomes 400.

Now consider it in hex. Consider FFFF x FF

Step 1: FF x FF=FE01
Keep FE as carry and 01 as the lower byte of answer.

Step 2: FF x FF= FE01

Step 3: Add carry FE01 + FE= FEFF It is addition of a 16 bit number and an 8 bit
number. Therefore addition will take two steps if carry gets generated by addition of
lower byte.

Instructions used:

1) MOV Rr, #n Copy the 8 bit number n into register Rr of the current register
bank
For e.g. MOV R0, #40H Put 8-bit memory address in register R0
 Where 40H is internal memory location
Here immediate addressing mode is used.

2) MOV A, @Rp Copy the contents of the address in Rp to A

MOV @Rp, A Copy the data in A to the address in Rp

Here indirect addressing mode is used. Any register R0 to R7 can be used to hold address
of the data. Here register R0 or R1 is often called a data pointer to hold address of one of
the data locations in RAM from address 00H to 7FH
For e.g. MOV A,@R0 Copy the contents of the address in R0 to the A register
MOV @R0, A Copy the data in A to internal memory address in R0

3) MOV A, Rr Copy data from register Rr to register A

MOV Rr, A Copy data from register A to register Rr.
Rr can be any register from R0 to R7
Here register addressing mode is used. A data MOV does not alter the contents of the
data source address. A copy of the data is made from source and moved to the destination
address. The contents of the destination are replaced by the source contents.
e. g. MOV R1, A Copy data from register A to register R1
MOV A, R1 Copy data from register R1 to register A

4) Incrementing and Decrementing

INC A Add a 1 to the register A
INC Rr Add a 1 to the register Rr
DEC Rr Subtract a 1 from the register R0
There are simple arithmetic operations involving adding or subtracting a binary 1 and a
number.
e.g. INC R0 Add a 1 to the register R0
DEC R0 Subtract a 1 from the register R0

5) Addition
All addition is done with the A register as the destination of the result.
ADD A, Rr Add A and register Rr put the sum in A
If there is a carry out of bit position 7, it is cleared to 0 otherwise
AC flag is set to 1 if there is a carry out of bit position 3, it is cleared otherwise
OV flag is set to 1 if there is a carry out of position 7.
e.g. ADD A, R4 Add A and register R4 put the sum in A

Some instructions include the carry flag as an additional source of a single bit that is
included in the operation at the least significant bit position.

ADDC A, #n Add the contents of A, the immediate number n and the C flag, put the
sum in A
C, AC and OV flags behave exactly as they do for the ADD commands.
e .g. MOV A, #1AH
ADDC A, #10H if C=1, A=2BH
ADDC is normally used to add a carry after the LSBY addition in a multi-byte process.

6) Multiplication
Multiplication operations use registers A and B as both source and destination addresses
for the operation. The unsigned number in register A is multiplied by the unsigned
number in register B as follows

MUL AB Multiply A by B; Put the low order byte of the product in A.

Put the high order byte in B
The OV flag will be set if A x B>FFh. It signals that the number is larger than 8 bits and
the programmer needs to inspect register B for the high order byte of the multiplication
operation. The carry flag is always cleared to 0.
e.g. MOV A, #7BH A=7BH
MOV 0F0H, #02H B=02H
MUL AB A=F6H and B=00H, OV=0
MOV B, #0FE B=FEH
MUL AB A=14H and B=F4H, OV=1

Input: 16 bit and 8 bit number stored in internal memory locations.

16 bit number=BBEEH
8 bit number=FFH

Memory Location Value Stored

40 BBH (Higher byte of 16 bit number)
41 EE H (Lower byte of 16 bit number)
42 FFH

Output: Result of 16 bit x 8 bit multiplication stored at internal memory locations from
50H onwards
BBEE x FF = BB3212

Memory Location Value Stored

50 BBH (First byte of result)
51 32H (Second byte of result)
52 12H (Third byte of result)

Algorithm:
Input is in 40H to 42H
Output is in internal memory 50H to 52H

1) Initialize pointer to internal memory and copy the memory location content
(input)of corresponding location to corresponding internal registers
2) Initialize memory pointer to internal memory to store the output
 3) Load the lower byte of the 16 bit number into accumulator A and 8 bit number
into register B
4) Multiply them using instruction MUL AB
5) Store lower byte of product in internal memory
6) Store the higher byte of product in one of general purpose register
7) Get higher byte of 16 bit number into accumulator and 8 bit number into register B
8) Multiply them using instruction MUL AB.
9) Add lower byte of the product with higher byte of previous multiplication.
10) Store the result into internal memory
11) Add carry with the higher byte and store it into memory

Program (with comments):

Calculations:

i) Calculations for 16 bitx8 bit multiplication

16 bit number= BBEEH
8 bit number= FFH

Multiplication of BBEE x FF
Step 1: EE x FF= ED12H
Keep ED as carry and 12 as the lower byte of the answer.

Step 2: BB x FF=BA45H

Step 3: Add the carry BA45 + ED= BB32

Therefore the answer is BB3212

ii) Write signed offset calculations for jump instructions.

Conclusion: Internal memory accesses are studied by multiplying 16 bit number with 8
bit number

FAQs:
1) Give significance of MUL instruction.
2) How to check zero flag in 8051?
3) What is bit addressable area? How many bits are addressable? What is their
significance?

References:
1. Ayala,”The 8051 Micro Controller 3rd Edition”, IE
2. Mazidi M.Gillipse J. “The 8051 Microcontroller and Embedded Systems”, Pearson
Education, 2002, ISBN-81-7808-574-7
Prepared By: M. I. T., Pune
Assignment No.10 (b)

Aim: Write a program on 8051 microcontroller using hardware or Kits for

1) Block transfer internal RAM to internal RAM memory.
2) Block transfer internal RAM to external RAM memory.
3) Block transfer external RAM to internal RAM.

Objective: To study the various concept of internal/ external memory and there
addressing mode.

Theory: In 8051 microcontroller data stored at a source address and moved to a

destination address.
The following four addressing modes are used to access data.
1) Immediate addressing mode
2) Register addressing mode
3) Direct addressing mode
4) In direct addressing mode

A) Related Theory: The 8051 architecture consists of Internal ROM and RAM.
1. Internal RAM of 128 bytes
2. Internal ROM or EPROM, 0-4K.
1. Internal RAM of 128 byte:
a) Four register bank, each contain eight registers (Working Register).
b) Sixteen byte, which may be addressed at the bit level (Bit Addressable)
c) Eighty byte of general purpose data memory. (General Purpose)
Internal RAM is organized into three areas. Thirty-two bytes from address 00h to 1fh
that makes up 32 working registers organized as four bank of eight registers each.
The four register banks are numbered 0 to 3 and are made up of eight registers name
R0 to R7.
A bit- addressable area of 16 byte occupies RAM byte addresses 20h to 2F, forming a
total of 128 addressable bits. An addressable bit may be specified by its bit address of
00h to 7Fh.A general purpose RAM area above the bit area, from 30h to 7Fh,
addressable as bytes.

2. Internal ROM or EPROM, 0-4K:

The internal ROM occupies code address space 0000h to 0FFFH.The PC is ordinarily
used to address program code byte from addresses 0000h to FFFFH. Program
addresses higher then 0FFFH, which exceed the internal ROM capacity, will cause
the 8051 automatically fetch code byte from external program memory. Code byte
can also be fetched exclusively from an external memory, addresses 0000h to
FFFFh by connecting the external access pin EA (pin 31) to ground.The PC does not
care where the code is; the circuit design decide whether the code is found totally in
internal ROM, totally in external ROM, or in a combination of internal and external
 ROM.

Instructions Used:

1) MOV: This instruction is used to move immediate / indirect data from register
to register or register to accumulator or register to a memory location.

Ex. MOV A, @ R0
MOV @ R1,A

2) DPTR: This is 16- bit data pointer, use full to hold the address of the data byte
in external RAM. DPTR registers can address the maximum RAM space of
0000h to 0FFFFh.

Ex MOVX A, @ Rp
MOVX A, @ DPTR
MOVX @ Rp, A
MOVX @ DPTR, A
MOVX is normally used with external RAM or I/O addresses.

3) DJNZ Rr, target: DJNZ decrement the register by one and jump to the relative
address if the result is not zero, no flages are affected

Ex DJNZ Rr, Label1

Input: The number of bytes in the block to be transfer for source address location
to destination address location of internal memory.

Output: The data has been transferred from source address location to destination

Algorithm: A) Block transfer internal RAM to internal RAM memory.

1) Start with starting address.
2) Load block of data in registers with internal memory location.
3) Initialize the counter for size of block transfer.
4) Move the data from internal memory pointed by register to
accumulator.
5) Move the data from accumulator to memory location pointed by
register.
6) Increment registers (input, output) point to next location.
7) Decrement register by one and check for count is zero, if not jump
back to 4th step.
8) Display the result.
9) Stop
 B) Block transfer internal RAM to external RAM memory.

1) Start with starting address.

2) Load block of data in Rn/DPTR with internal/ external memory
location.
3) Initialize the counter for size of block transfer.
4) Move the data from internal memory pointed by register to
accumulator.
5) Move the data from accumulator to the external address in DPTR.
6) Increment DPTR and register pointed to next location.
7) Decrement register by one and check for count is zero, if not jump
back to 4th step.
8) Display the result.
9) Stop

C) Block transfer external RAM to internal RAM memory.

1) Start with starting address.

2) Load block of data in DPTR/Rn with external/ internal memory
location.
3) Initialize the counter for size of block transfer.
4) Move the data from external memory pointed by DPTR to
accumulator.
5) Move the data from accumulator to the internal register address.
6) Increment DPTR and register pointed to next location.
7) Decrement register by one and check for count is zero, if not jump
back to 4th step.
8) Display the result.
10) Stop

Conclusion: Thus we have transfer 8-bit data from internal RAM to another location in
RAM, internal memory to external memory location , external memory
location to internal memory, but external to external memory data transfer
is not possible because two DPTR is not available in microcontroller.

FAQ: Q.1) What is size of RAM and ROM IN 8051 microcontroller.

Q.2) Difference between MOV, MOVX, MOVC.
Q.3) List different addressing mode with one example each.

References: The 8051 Microcontroller “Ayala” chapter no. 5.

Prepared By: M. I. T., Pune