Tas 5706

TAS5706
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SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007
20-W Stereo Digital Audio Power Amplifier with EQ and DRC

1FEATURES – Programmable Input and Output Mixers
• Audio Input/Output
23 – Loudness Compensation for Subwoofer
– 20-W into an 8-Ω Load From an 18-V Supply – Automatic Sample-Rate Detection and
– Two Serial Audio Inputs (Four Audio Coefficient Banking
Channels) • General Features
– Supports Multiple Output Configurations: – Serial Control Interface Operational Without
– 2-Ch Bridged Outputs (20 W × 2) MCLK
– 4-Ch Single-Ended Outputs (10 W × 4) – Factory-Trimmed Internal Oscillator Avoids
– 2-Ch Single-Ended + 1-Ch Bridged (2.1) the Need for External Crystal
(10 W × 2 + 20 W) – Surface Mount, 64-Terminal, 10-mm ×
• Closed Loop Power Stage Architecture 10-mm HTQFP Package
– Improved PSRR Reduces Power Supply – Thermal and Short-Circuit Protection
Performance Requirements
DESCRIPTION
– Higher Damping Factor Provides for
Tighter, More Accurate Sound With The TAS5706 is a 20-W, efficient, digital audio power
Improved Bass Response amplifier for driving stereo bridged-tied speakers. Two
serial data inputs allow processing of up to four
– Constant Output Power Over Variation in discrete audio channels and seamless integration to
Supply most digital audio processors and MPEG decoders,
• Wide PVCC Range From (10 V to 26 V) accepting a wide range of input data and clock rates.
– No Separate Supply Required for Gate A fully programmable data path allows these
Drive channels to be routed to the internal speaker drivers
or output via the subwoofer or headphone PWM
• Supports 32-kHz–192-kHz Sample Rates outputs.
(LJ/RJ/I2S)
The TAS5706 is a slave-only device receiving all
• Headphone PWM Outputs clocks from external sources. The TAS5706 operates
• Subwoofer PWM Outputs at a 384-kHz switching rate for 32-, 48-, 96-, and
• AM Interference Avoidance Support 192-kHz data, and at a 352.8 kHz switching rate for
44.1-, 88.2-, and 176.4-kHz data. The 8×
• Audio/PWM Processing
oversampling combined with the fourth-order noise
– Independent Channel Volume Controls With shaper provides a flat noise floor and excellent
24-dB to –100-dB Range—Soft Mute (50% dynamic range from 20 Hz to 20 kHz.
Duty Cycle)
– Programmable Dynamic Range Control
– 16 Programmable Biquads for Speaker
Equalization
– Adaptive Biquad Coefficients for EQ and
DRC Filters
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PurePath Digital is a trademark of Texas Instruments.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas Copyright © 2007, Texas Instruments Incorporated
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAMS
Bridge-Tied Load (BTL) Mode

3.3 V 10 V–26 V
DVDD/AVDD AVCC/PVCC
OUT_A
LRCLK
SCLK BST_A
Digital
Audio MCLK LCBTL* Left
Source BST_B
SDIN1
SDIN2
OUT_B
2 OUT_C
I C SDA
Control SCL
BST_C
LCBTL* Right
BST_D
MUTE
Control HPSEL OUT_D
Inputs RESET
PDN TAS5601 10 V–26 V
SUB_PWM+ PWM_AP
OUT_A
PWM_AN
SUB_PWM– PWM_BP BST_A
PLL_FLTP LCBTL* Subwoofer
Loop BST_B
Filter PWM_BN
PLL_FLTM OUT_B
BKND_ERR FAULT
VALID RESET
HPR_PWM
RC
Filter
HPL_PWM
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for BTL (AD/BD mode) configuration.
B0264-02
2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TAS5706

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Single-Ended (SE) 2.1 Mode

3.3 V 10 V–26 V
DVDD/AVDD AVCC/PVCC
OUT_A LCSE*
LRCLK
SCLK BST_A
Digital
Audio MCLK
Source
SDIN1
BST_B
SDIN2
OUT_B LCSE*
2 SDA
I C
Control SCL
MUTE OUT_C
Control HPSEL
Inputs RESET BST_C
LCBTL*
PDN
BST_D
OUT_D
PLL_FLTP
Loop
Filter SUB_PWM+
PLL_FLTM SUB_PWM–
BKND_ERR
VALID
HPR_PWM
RC
Filter
HPL_PWM
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for SE or BTL configuration.

B0264-05
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3

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Single-Ended (SE) 4.0 Mode

3.3 V 10 V–26 V
DVDD/AVDD AVCC/PVCC
OUT_A LCSE*
LRCLK
SCLK BST_A
Digital
Audio MCLK
Source
SDIN1
BST_B
SDIN2
OUT_B LCSE*
2 SDA
I C
Control SCL
MUTE OUT_C LCSE*
Control HPSEL
Inputs RESET BST_C
PDN
BST_D
OUT_D LCSE*
PLL_FLTP
Loop
Filter SUB_PWM+
PLL_FLTM SUB_PWM–
BKND_ERR
VALID
HPR_PWM
RC
Filter
HPL_PWM
TPA6110A2
(HP Amplifier)
* Refer to TI Application Note (SLOA119) on LC filter design for SE configuration.

B0264-04

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FUNCTIONAL VIEW

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64-TERMINAL, HTQFP PACKAGE (TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL TYPE 5-V TERMINATION
(1) (2) DESCRIPTION
NAME NO. TOLERANT
AGND 57 P Analog ground for power stage
AVCC 58 P Analog power supply for power stage. Connect externally to same
potential as PVCC.
AVDD 10 P 3.3-V analog power supply
AVSS 11 P Analog 3.3-V supply ground
BKND_ERR 35 DI Pullup Active-low. A back-end error sequence is generated by applying logic
LOW to this terminal. This terminal is connected to an external power
stage. If no external power stage is used, connect this terminal directly
to DVDD.
(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

(2) All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pulldowns. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input). Devices that drive
inputs with pullups must be able to sink 20 µA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20 µA while maintaining a logic-1 drive level.

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TERMINAL FUNCTIONS (continued)

(1) (2) DESCRIPTION
NAME NO. TOLERANT
BST_A 59 P High-side bootstrap supply for half-bridge A
BST_B 61 P High-side bootstrap supply for half-bridge B
BST_C 53 P High-side bootstrap supply for half-bridge C
BST_D 55 P High-side bootstrap supply for half-bridge D
BYPASS 56 O Nominally equal to VCC/8. Internal reference voltage for analog cells
DVDD 15, P 3.3-V digital power supply
33
DVSS 20, P Digital ground
26
HPL_PWM 37 DO Headphone left-channel PWM output.
HPR_PWM 38 DO Headphone right-channel PWM output.
HPSEL 30 DI 5-V Headphone select, active high. When a logic HIGH is applied, device
enters headphone mode and speakers are HARD MUTED. When a
logic LOW is applied, device is in speaker mode and headphone
outputs become line outputs or are disabled.
LRCLK 22 DI 5-V Input serial audio data left/right clock (sampling rate clock)
MCLK 34 DI 5-V MCLK is the clock master input. The input frequency of this clock can
range from 4.9 MHz to 49 MHz.
MUTE 21 DI 5-V Pullup Performs a soft mute of outputs, active-low. A logic low on this
terminal sets the outputs equal to 50% duty cycle. A logic high on this
terminal allows normal operation. The mute control provides a
noiseless volume ramp to silence. Releasing mute provides a
noiseless ramp to previous volume.
OSC_RES 19 AO Oscillator trim resistor. Connect an 18.2-kΩ resistor to GND.
OUT_A 4, 5 O Output, half-bridge A
OUT_B 1, 64 O Output, half-bridge B
OUT_C 49, O Output, half-bridge C
50
OUT_D 45, O Output, half-bridge D
46
PDN 17 DI 5-V Pullup Power down, active-low. PDN powers down all logic, stops all clocks,
and outputs stops switching. When PDN is released, the device
powers up all logic, starts all clocks, and performs a soft start that
returns to the previous configuration determined by register settings.
PGND_A 6, 7 P Power ground for half-bridge A
PGND_B 2, 3 P Power ground for half-bridge B
PGND_C 47, P Power ground for half-bridge C
48
PGND_D 43, P Power ground for half-bridge D
44
PLL_FLTM 12 AO PLL negative input
PLL_FLTP 13 AI PLL positive input
PVCC_A 8, 9 P Power supply input for half-bridge output A
PVCC_B 62, P Power supply input for half-bridge output B
63
PVCC_C 51, P Power supply input for half-bridge output C
52
PVCC_D 41, P Power supply input for half-bridge output D
42

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TERMINAL FUNCTIONS (continued)

(1) (2) DESCRIPTION
NAME NO. TOLERANT
RESET 16 DI 5-V Pullup Reset, active-low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that
restores the DAP to its default conditions, sets the VALID outputs low,
and places the PWM in the hard-mute state (stops switching). Master
volume is immediately set to full attenuation. Upon the release of
RESET, if PDN is high, the system performs a 4- to 5-ms device
initialization and sets the volume at mute.
SCL 29 DI 5-V I2C serial control clock input
SCLK 23 DI 5-V Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
SDA 28 DIO 5-V I2C serial control data interface input/output
SDIN1 25 DI 5-V Serial audio data-1 input is one of the serial data input ports. SDIN1
supports three discrete (stereo) data formats.
SDIN2 24 DI 5-V Serial audio data-2 input is one of the serial data input ports. SDIN2
supports three discrete (stereo) data formats.
STEST 31 DI Test terminal. Connect directly to GND.
SUB_PWM– 39 DO Subwoofer negative PWM output
SUB_PWM+ 40 DO Subwoofer positive PWM output
TEST2 32 DI Test terminal. Connect directly to DVDD.
VALID 36 DO Output indicating validity of ALL PWM channels, active-high. This
terminal is connected to an external power stage. If no external power
stage is used, leave this terminal floating.
VCLAMP_AB 60 P Internally generated voltage supply for channels A and B gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VCLAMP_CD 54 P Internally generated voltage supply for channels C and D gate drive.
Not to be used as a supply or connected to any component other than
the decoupling capacitor
VR_ANA 14 P Internally regulated 1.8-V analog supply voltage. This terminal must
not be used to power external devices.
VR_DIG 27 P Internally regulated 1.8-V digital supply voltage. This terminal must not
be used to power external devices.
VREG_EN 18 DI Pulldown Voltage regulator enable. Connect directly to GND.
ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
Supply voltage DVDD, AVDD –0.3 to 3.6 V
PVCC -0.3 to 30 V
Input voltage 3.3-V digital input –0.5 to DVDD + 0.5 V
5-V tolerant (2) digital input –0.5 to 6 V
Input clamp current, IIK (VI < 0 or VI > 1.8 V ±20 mA
Output clamp current, IOK (VO < 0 or VO > 1.8 V ±20 mA
Operating free-air temperature 0 to 85 °C
Operating junction temperature range 0 to 150 °C
Storage temperature range, Tstg –40 to 125 °C
(1) Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
(2) 5-V tolerant inputs are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.

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DISSIPATION RATINGS
TA = 25°C TA = 45°C TA = 70°C
PACKAGE (1) DERATING FACTOR
POWER RATING POWER RATING POWER RATING
10-mm × 10-mm QFP 29 mW/°C 2.89 W 2.31 W 1.59 W
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Digital/analog supply voltage DVDD 3 3.3 3.6 V
Half-bridge supply voltage PVCC_xx 10 26 V
VIH High-level input voltage 3.3-V TTL, 5-V tolerant 2 V
VIL Low-level input voltage 3.3-V TTL, 5-V tolerant 0.8 V
TA Operating ambient temperature range 0 85 °C
TJ Operating junction temperature range 0 150 °C
RL (BTL) 6.0 8
RL (SE) Load impedance Output filter: L = 22 µH, C = 680 nF. 3.2 4 Ω
RL (PBTL) 3.2 4
LO (BTL) 10
Minimum output inductance under
LO (SE) Output-filter inductance 10 µH
short-circuit condition
LO (PBTL) 10
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PARAMETER TEST CONDITIONS MODE VALUE UNITS
32–kHz data rate ±2% 12× sample rate 384 kHz
Output sample rate 2×–1×
44.1-, 88.2-, 176.4-kHz data rate ±2% 8×, 4×, and 2× sample rates 352.8 kHz
oversampled
48-, 96-, 192-kHz data rate ±2% 8×, 4×, and 2× sample rates 384 kHz
PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fMCLKI Frequency, MCLK (1 / tcyc2) 4.9 49 MHz
MCLK duty cycle 40% 50% 60%
≥2-V MCLK = 49.152 MHz, within the
MCLK minimum high time 8 ns
min and max duty cycle constraints
≤0.8-V MCLK = 49.152 MHz, within the
MCLK minimum low time 8 ns
min and max duty cycle constraints
LRCLK allowable drift before LRCLK reset 10 MCLKs
External PLL filter capacitor C1 SMD 0603 Y5V 47 nF
External PLL filter capacitor C2 SMD 0603 Y5V 4.7 nF
External PLL filter resistor R SMD 0603, metal film 470 Ω

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ELECTRICAL CHARACTERISTICS
DC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, RL = 8 Ω (unless otherwise noted)
(1)
VOH High-level output voltage 3.3-V TTL and 5-V tolerant IOH = –4 mA 2.4 V
(1)
VOL Low-level output voltage 3.3-V TTL and 5-V tolerant IOL = 4 mA 0.5 V
| VOS | Class-D output offset voltage ±26 mV
VBYPASS PVCC/8 reference for analog section No load 2.2 2.26 2.3 V
3.3-V TTL VI = VIL ±2
IIL Low-level input current µA
5-V tolerant (1) VI = 0 V, DVDD = 3 V ±2
3.3-V TTL VI = VIH ±2
IIH High-level input current µA
5-V tolerant VI = 5.5 V, DVDD = 3 V ±20
Normal mode 43 65 80
Power down 2 8 16
IDD Input supply current Supply voltage (DVDD, AVDD) mA
(PDNZ = LOW)
Reset (RESET = LOW) 11 23 33
ICC Quiescent supply current No load 14 33 57 mA
ICC(RESET) Quiescent supply current in reset mode No load 58 176 µA
ICC(PDNZ) Quiescent supply current in power down mode No load 58 176 µA
PSRR DC power-supply rejection ratio PVCC = 17.5 V to 18.5 V 60 dB
Drain-source on-state resistance, high-side VCC = 18 V , IO = 500 mA, 240
TJ = 25°C
RDS(on) Low-side 240 mΩ
Total 480 850
Turnon time (SE mode) (Set Reg 0x1A bit 7 to 1) C(BYPASS) = 1 µF, 500
tON Time required for the ms
Turnon time (BTL mode) (Set Reg 0x1A bit 7 to 0) 30
C(BYPASS) to reach its final
Turnoff time (SE mode) (Set Reg 0X1A bit 7 to 1) value 500
tOFF ms
Turnoff time (BTL mode) (Set Reg 0X1A bit 7 to 0) 30
(1) 5-V tolerant pins are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDA, SCL, and HPSEL.

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AC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless

otherwise noted) (1)
KSVR Supply ripple rejection 100-mVPP ripple at 20 Hz–20 kHz, BTL, 50% –60 dB
duty cycle PWM
PO Continuous output BTL (RL = 8 Ω, THD+N = 10%, f = 1 kHz, 20.6 W
power PVCC = 18 V)
BTL (RL = 8 Ω, THD+N = 7%, f = 1 kHz, 19.3 W
PVCC = 18 V)
SE (RL = 4 Ω, THD+N = 10%, f = 1 kHz, 18.1 W
PVCC = 24 V)
SE (RL = 4 Ω, THD+N = 7%, f = 1 kHz, PVCC 17.3 W
= 24 V)
THD+N Total harmonic distortion VCC = 24 V, RL = 4 Ω, f = 1 kHz, PO = 10 W 0.08%
+ noise (SE) (half-power)
Total harmonic distortion VCC = 18 V, RL = 8 Ω, f = 1 kHz, PO = 10 W 0.05%
+ noise (BTL) (half-power)
Vn Output integrated noise 20 Hz to 22 kHz (BD mode) 115 µV
A-weighted filter; MUTE = LOW –82 dBV
Crosstalk PO = 1 W, f = 1 kHz –69 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, 99 dB
A-weighted
Thermal trip point 150 °C
(output shutdown,
unlatched fault)
Thermal hysteresis 15 °C
(1) All measurement in AD mode.
AC Characteristics, TA = 25°C, PVCC_X, AVCC = 12 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless

otherwise noted) (1)
KSVR Supply ripple rejection 100-mVpp ripple at 20 Hz–20 kHz, BTL, –60 dB
50% duty cycle PWM
PO Continuous output power BTL (RL = 8 Ω, THD+N = 10%, f = 1 kHz) 9.2 W
BTL (RL = 8 Ω, THD+N = 7%, f = 1 kHz) 8.7 W
SE (RL = 4 Ω, THD+N = 10%, f = 1 kHz) 4.5 W
SE (RL = 4 Ω, THD+N = 7%, f = 1 kHz) 4.2 W
THD+N Total harmonic distortion VCC = 12 V, RL = 8 Ω, f = 1 kHz, 0.07%
+ noise (BTL) PO = 5 W (half-power)
Vn Output integrated noise 20 Hz to 22 kHz (BD mode) 115 µV
A-weighted filter –82 dBV
Crosstalk PO = 1 W, f = 1 kHz –75 dB
SNR Signal-to-noise ratio Maximum output at THD+N < 1%, 96 dB
f = 1 kHz, A-weighted
Thermal trip point (output 150 °C
shutdown, unlatched fault)
Thermal hysteresis 15 °C
(1) All measurement in AD mode.

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SERIAL AUDIO PORTS SLAVE MODE

over recommended operating conditions (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS CL = 30 pF 1.024 12.288 MHz
tsu1 Setup time, LRCLK to SCLK rising edge 10 ns
th1 Hold time, LRCLK from SCLK rising edge 10 ns
tsu2 Setup time, SDIN to SCLK rising edge 10 ns
th2 Hold time, SDIN from SCLK rising edge 10 ns
LRCLK frequency 32 48 192 kHz
SCLK duty cycle 40% 50% 60%
LRCLK duty cycle 40% 50% 60%
SCLK
SCLK rising edges between LRCLK rising edges 32 64
edges
t(edge) SCLK
LRCLK clock edge with respect to the falling edge of SCLK –1/4 1/4
period
Figure 1. Slave Mode Serial Data Interface Timing

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I2C SERIAL CONTROL PORT OPERATION

Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fSCL Frequency, SCL No wait states 400 kHz
tw(H) Pulse duration, SCL high 0.6 µs
tw(L) Pulse duration, SCL low 1.3 µs
tr Rise time, SCL and SDA 300 ns
tf Fall time, SCL and SDA 300 ns
tsu1 Setup time, SDA to SCL 100 ns
th1 Hold time, SCL to SDA 0 ns
t(buf) Bus free time between stop and start condition 1.3 µs
tsu2 Setup time, SCL to start condition 0.6 µs
th2 Hold time, start condition to SCL 0.6 µs
tsu3 Setup time, SCL to stop condition 0.6 µs
CL Load capacitance for each bus line 400 pF
tw(H) tw(L) tr tf
SCL
tsu1 th1
SDA
T0027-01
Figure 2. SCL and SDA Timing
SCL
th2 t(buf)
tsu2 tsu3
SDA
Start Stop
Condition Condition
T0028-01
Figure 3. Start and Stop Conditions Timing

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RESET TIMING (RESET)

Control signal parameters over recommended operating conditions (unless otherwise noted)
td(VALID_LOW) Time to assert VALID (reset to power stage) low 300 ns
tw(RESET) Pulse duration, RESET active 1 ms
td(I2C_ready) Time to enable I2C 3.5 ms
td(run) Device start-up time (after start-up command via I2C) 10 ms
RESET Earliest time

that hard mute
could be exited
tw(RESET)
VALID
td(I2C_ready)
td(VALID_LOW) £ 300 ns td(run)
System initialization. Start system

2
Enable via I C.
T0029-05
Figure 4. Reset Timing
POWER-DOWN (PDN) TIMING

td(VALID_LOW) Time to assert VALID (reset to power stage) low 725 µs
td(STARTUP) Device startup time 120 ms
tw Minimum pulse duration required 800 ns
PDN
tw
VALID
td(VALID_LOW) £ 300 ms td(STARTUP)

T0030-04
Figure 5. Power-Down Timing
BACK-END ERROR (BKND_ERR)

tw(ER) Pulse duration, BKND_ERR active (active-low) 350 None ns
tp(valid_high) Programmable. Time to stay in the OUT_x low state. After tp(valid_high), the TAS5706
attempts to bring the system out of the OUT_x low state if BKND_ERR is high. Refer ms
Reg 0x1C
tp(valid_low) Time TAS5706 takes to bring OUT_x low after BKND_ERR assertion. 350 ns

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tw(ER)
BKND_ERR
VALID Normal Normal

Operation Operation
tp(valid_high)
tp(valid_low)
T0031-04
Figure 6. Error Recovery Timing
MUTE TIMING (MUTE)

td(VOL) Volume ramp time. Ramp Time = Number of Steps (programmable number of steps, refer 1024 steps
register 0x0E) × Stepsize (1)
(1) Stepsize = 4 LRCLKs (for 32–48 kHz sample rate); 8 LRCLKs (for 88.2–96 kHz sample rate); 16 LRCLKs (for 176.4–192 kHz sample
rate)
MUTE
VOLUME Normal Normal

Operation Operation
td(VOL) td(VOL)
50-50
Duty Cycle
T0032-03
Figure 7. Mute Timing

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HEADPHONE SELECT (HPSEL)

PARAMETER MIN MAX UNIT
tw(MUTE) Pulse duration, HPSEL active 350 None ns
(1)
td(VOL) Soft volume update time See ms
t(SW) Switch-over time 0.2 1 ms
(1) Defined by rate setting. See the Volume Configuration Register section.
Figure 8 and Figure 9 show functionality when bit 4 in HP configuration register is set to DISABLE line output from HP_PWM outputs. If
bit 4 is not set, than the HP PWM outputs are not disabled when HPSEL is brought low.
HPSEL
Spkr Volume
td(VOL)
HP Volume
td(VOL)
t(SW)
VALID
T0267-01
Figure 8. HPSEL Timing for Headphone Insertion
HPSEL
HP Volume
td(VOL)
Spkr Volume
td(VOL)
t(SW)
VALID
T0268-01
Figure 9. HPSEL Timing for Headphone Extraction

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE (BTL) TOTAL HARMONIC DISTORTION + NOISE (BTL)
vs vs
FREQUENCY FREQUENCY
10 10
THD+N − Total Harmonic Distortion + Noise − %

VCC = 12 V VCC = 18 V
RL = 8 Ω RL = 8 Ω
P = 10 W
1 P=5W 1
P = 2.5 W P=5W
0.1 0.1
0.01 0.01
P = 0.5 W P=1W
0.001 0.001
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G001 G002
Figure 10. Figure 11.
vs vs
FREQUENCY OUTPUT POWER
10 10
VCC = 24 V VCC = 12 V
RL = 8 Ω RL = 8 Ω
1 P = 10 W 1
f = 10 kHz
P=5W f = 1 kHz
0.1 0.1
0.01 0.01
P=1W
f = 20 Hz
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 40
f − Frequency − Hz PO − Output Power − W
G003 G004

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
vs vs
OUTPUT POWER OUTPUT POWER
10 10

VCC = 18 V VCC = 24 V
RL = 8 Ω RL = 8 Ω
1 1
f = 10 kHz f = 10 kHz
f = 1 kHz f = 1 kHz
0.1 0.1
0.01 0.01
f = 20 Hz f = 20 Hz
0.001 0.001
0.01 0.1 1 10 40 0.01 0.1 1 10 40
PO − Output Power − W PO − Output Power − W
G005 G006
EFFICIENCY SUPPLY CURRENT

vs vs
OUTPUT POWER TOTAL OUTPUT POWER
100 3.0
90 RL = 8 Ω
2.5 VCC = 18 V
80
ICC − Supply Current − A
70 VCC = 24 V
VCC = 18 V 2.0 VCC = 12 V
Efficiency − %
60 VCC = 12 V
50 1.5
40
1.0
30
20 VCC = 24 V
0.5
10 RL = 8 Ω
0 0.0
0 5 10 15 20 25 30 0 5 10 15 20 25 30 35 40
PO − Output Power (Per Channel) − W PO − Total Output Power − W
G007 G008

TAS5706
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OUTPUT POWER PSRR

vs vs
SUPPLY VOLTAGE PVCC
40 0
RL = 8 Ω −10
35
−20
30
−30
PO − Output Power − W
25 THD+N = 10%
−40
PSRR − dB
20 −50
−60
15 THD+N = 1%
−70
10
−80
5
−90
0 −100
10 12 14 16 18 20 22 24 26 10 12 14 16 18 20 22 24 26
VCC − Supply Voltage − V PVCC − V
G009 G010
A-WTD NOISE CROSSTALK

vs vs
PVCC FREQUENCY
−75 −40
−76 −50
−77 −60
Right to Left
−78 −70
A-Wtd Noise − dBV
Crosstalk − dB
−79 −80 Left to Right

−80 −90
−81 −100
−82 −110
−83 −120
−84 −130 RL = 8 Ω
VCC = 12 V
−85 −140
10 12 14 16 18 20 22 24 26 20 100 1k 10k 20k
PVCC − V f − Frequency − Hz
G011 G012

TAS5706
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CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
−40 −40
−50 −50
−60 −60
Right to Left Right to Left
−70 −70
Crosstalk − dB
Crosstalk − dB
−80 −80 Left to Right
Left to Right
−90 −90
−100 −100
−110 −110
−120 −120
−130 RL = 8 Ω −130 RL = 8 Ω
VCC = 18 V VCC = 24 V
−140 −140
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
G013 G014
TYPICAL CHARACTERISTICS, SE CONFIGURATION

TOTAL HARMONIC DISTORTION + NOISE (SE) TOTAL HARMONIC DISTORTION + NOISE (SE)
vs vs
FREQUENCY OUTPUT POWER
10 10
PO = 1 W
f = 1 kHz
RL = 4 Ω RL = 4 Ω
1 1
VCC = 12 V
VCC = 12 V
0.1 0.1
VCC = 24 V
VCC = 24 V
0.01 0.01
VCC = 18 V VCC = 18 V
0.001 0.001
20 100 1k 10k 20k 0.01 0.1 1 10 40
f − Frequency − Hz PO − Output Power − W
G015 G016

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TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued)
EFFICIENCY SUPPLY CURRENT

vs vs
OUTPUT POWER TOTAL OUTPUT POWER
100 2.0
90 RL = 4 Ω
VCC = 18 V
80
1.5
VCC = 24 V
ICC − Supply Current − A

70 VCC = 12 V
VCC = 18 V
Efficiency − %
60
VCC = 12 V
50 1.0
40 VCC = 24 V
30
0.5
20
10 RL = 4 Ω
0 0.0
0 5 10 15 20 25 0 5 10 15 20 25 30 35 40
PO − Output Power (Per Channel) − W PO − Total Output Power − W
G017 G018
OUTPUT POWER
vs
SUPPLY VOLTAGE
20
18 RL = 4 Ω
16
14
PO − Output Power − W
12 THD+N = 10%
10
8
THD+N = 1%
6
0
10 12 14 16 18 20 22 24 26
VCC − Supply Voltage − V
G019
Figure 28.

TAS5706
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DETAILED DESCRIPTION
POWER SUPPLY
The digital portion of the chip requires 3.3 V, and the power stages can work from 10 V to 26 V.
CLOCK, AUTO DETECTION, AND PLL

The TAS5706 DAP is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register.
The TAS5706 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×
fS LRCLK. The timing relationship of these clocks to SDIN1/2 is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the internal clock.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for the frequencies of
32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or
192 kHz). The automatic sample rate detection can be disabled and the values set via I2C in the clock control
register.
The DAP also supports an AM interference-avoidance mode during which the clock rate is adjusted, in concert
with the PWM sample rate converter, to produce a PWM output at 7 × fS, 8 × fS, or 6 × fS.
The sample rate must be set manually during AM interference avoidance and when de-emphasis is enabled.
SERIAL DATA INTERFACE

Serial data is input on SDIN1/2. The PWM outputs are derived from SDIN1/2. The TAS5706 DAP accepts 32-,
44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in left-justified, right-justified,
and I2S serial data formats.
PWM Section
The TAS5706 DAP device uses noise-shaping and sophisticated error correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper that
has >100-dB SNR performance from 20 Hz to 20 kHz. The PWM section accepts 24-bit PCM data from the DAP
and outputs four PWM audio output channels. TAS5706 PWM section output supports bridge-tied loads.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 32-, 44.1-, and 48-kHz are included and
can be enabled and disabled.
Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
I2C COMPATIBLE SERIAL CONTROL INTERFACE

The TAS5706 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
The I2C interface supports a special mode which permits I2C write operations to be broken up into multiple-data
write operations that are multiples of 4 data bytes. These are 6-, 10-, 14-, 18-, ... etc., -byte write operations that
are composed of a device address, read/write bit, subaddress, and any multiple of 4 bytes of data. This permits
the system to write large register values incrementally without blocking other I2C transactions.

0x20 Drc1_dis
0x25
0x21<12> 0x08 0x20<23>
LF+ 6
Drc1_en PWM1
www.ti.com
LF Noise Out_A
1 7 0x11
Vol1 Shaper LF–
BQ
AD/BD
drc1_ coeff
DRC1
0x21<11> 0x09 0x20<19>

RF+ 6
RF Drc1_en Noise PWM2 Out_B
2 7 0x12
Vol 2 Shaper RF–
BQ
AD/BD
drc1_ coeff
Copyright © 2007, Texas Instruments Incorporated

0x20<14:12>
0x0A B 6
Drc1_en Noise T
PWM3 Out_C
LS L 0x13
3 Vol 3 Shaper
AD
drc1_ coeff
Master Volume 0x07

Drc2_dis
0x20<10:8>
0x0B B 6
Drc1_en Noise T
PWM4 Out_D
RS L 0x14
4 Vol 4 Shaper
AD
drc1_ coeff
0x20<6:4>
Sub–

L' R' 6
0x04 B PWM5
(L'+R')/2 T Sub–
SDIN1L Down Mix L 0x15
SDIN1 0x21<3:0>
SDIN1R 0x21<9:8> 0x20<3>
SDI SDIN2L 0x0D
SDIN2R Drc2_en Noise
SDIN2 Bass 2
Vol6 Shaper Sub+ 6
Management BQ PWM6
AD/BD Sub+
0x16
BQ (0x24)
SUB drc2_ coeff

Loudness (0x23)
DRC2
6
Figure 29. TAS5706 DAP Data Flow Diagram With I2C Registers
HPL
6
HPR
Submit Documentation Feedback

B0263-01
TAS5706
23
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I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks 32 Clks
LRCLK (Note Reversed Phase) Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 9 8 5 4 1 0 23 22 9 8 5 4 1 0
20-Bit Mode
19 18 5 4 1 0 19 18 5 4 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 30. I2S 64-fS Format

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2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
24 Clks 24 Clks
LRCLK Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 17 16 9 8 5 4 3 2 1 0 23 22 17 16 9 8 5 4 3 2 1
20-Bit Mode
19 18 13 12 5 4 1 0 19 18 13 12 5 4 1 0
16-Bit Mode
15 14 9 8 1 0 15 14 9 8 1 0
T0092-01
2
2-Channel I S (Philips Format) Stereo Input
16 Clks 16 Clks
LRCLK Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

16-Bit Mode
15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1
T0266-01

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Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks 32 Clks
LRCLK
Left Channel Right Channel
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 9 8 5 4 1 0 23 22 9 8 5 4 1 0
20-Bit Mode
19 18 5 4 1 0 19 18 5 4 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-02
Figure 33. Left-Justified 64-fS Format

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2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks 24 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 21 17 16 9 8 5 4 1 0 23 22 21 17 16 9 8 5 4 1 0
20-Bit Mode
19 18 17 13 12 5 4 1 0 19 18 17 13 12 5 4 1 0
16-Bit Mode
15 14 13 9 8 1 0 15 14 13 9 8 1 0
T0092-02
2-Channel Left-Justified Stereo Input
16 Clks 16 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

16-Bit Mode
15 14 13 12 11 10 9 8 5 4 3 2 1 0 15 14 13 12 11 10 9 8 5 4 3 2 1 0
T0266-02

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Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks 32 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 19 18 15 14 1 0 23 22 19 18 15 14 1 0
20-Bit Mode
19 18 15 14 1 0 19 18 15 14 1 0
16-Bit Mode
15 14 1 0 15 14 1 0
T0034-03
Figure 36. Right Justified 64-fS Format

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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks 24 Clks
LRCLK
SCLK SCLK
MSB LSB MSB LSB

24-Bit Mode
23 22 19 18 15 14 6 5 2 1 0 23 22 19 18 15 14 6 5 2 1 0
20-Bit Mode
19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0
16-Bit Mode
15 14 6 5 2 1 0 15 14 6 5 2 1 0
T0092-03

TAS5706
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I2C SERIAL CONTROL INTERFACE
The TAS5706 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation

The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and stop
conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal
data bit transitions must occur within the low time of the clock period. These conditions are shown in Figure 39.
The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5706 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
R/ 8-Bit Register Data For 8-Bit Register Data For

SDA 7-Bit Slave Address A 8-Bit Register Address (N) A A A
W Address (N) Address (N)
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
SCL
Start Stop
T0035-01
2
Figure 39. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 39.
The 7-bit address for TAS5706 is 0011 011 (0x36).
Single- and Multiple-Byte Transfers

The serial control interface supports both single-byte and multiple-byte read/write operations for status registers
and the general control registers associated with the PWM. However, for the DAP data processing registers, the
serial control interface supports only multiple-byte (4-byte) read/write operations.
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. If a write command is received for a biquad subaddress, the DAP
expects to receive five 32-bit words. If fewer than five 32-bit data words have been received when a stop
command (or another start command) is received, the data received is discarded. Similarly, if a write command is
received for a mixer coefficient, the DAP expects to receive one 32-bit word.

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Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5706
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5706. For I2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 40, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5706 internal memory address being accessed. After receiving
the address byte, the TAS5706 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5706 again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition Acknowledge Acknowledge Acknowledge
A6 A5 A4 A3 A2 A1 A0 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
2 Stop
I C Device Address and Subaddress Data Byte
Read/Write Bit Condition
T0036-01
Figure 40. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 41. After receiving each data byte, the
TAS5706 responds with an acknowledge bit.
Start
Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A3 A1 A0 ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
2 Stop
I C Device Address and Subaddress First Data Byte Other Data Bytes Last Data Byte
Read/Write Bit Condition
T0036-02
Figure 41. Multiple-Byte Write Transfer

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Single-Byte Read
As shown in Figure 42, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5706 address
and the read/write bit, TAS5706 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5706 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5706 again responds with an acknowledge bit. Next, the TAS5706
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Repeat Start
Condition
Start Not
Condition Acknowledge Acknowledge Acknowledge Acknowledge
A6 A5 A1 A0 R/W ACK A7 A6 A5 A4 A0 ACK A6 A5 A1 A0 R/W ACK D7 D6 D1 D0 ACK
2 2
I C Device Address and Subaddress I C Device Address and Data Byte Stop
Read/Write Bit Read/Write Bit Condition
T0036-03
Figure 42. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5706 to the master device as shown in Figure 43. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start Not
Condition Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge Acknowledge
A6 A0 R/W ACK A7 A6 A5 A0 ACK A6 A0 R/W ACK D7 D0 ACK D7 D0 ACK D7 D0 ACK
2 2
I C Device Address and Subaddress I C Device Address and First Data Byte Other Data Bytes Last Data Byte Stop
Read/Write Bit Read/Write Bit Condition
T0036-04
Figure 43. Multiple Byte Read Transfer

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Dynamic Range Control (DRC)

The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
left/right channels and one DRC for the subwoofer channel.
The DRC input/output diagram is shown in Figure 44.
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• One DRC for left/right and one DRC for subwoofer
• Each DRC has adjustable threshold, offset, and compression levels
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 44. Dynamic Range Control
Attack
Audio Input Energy Compression and
DRC Coefficient
Filter Control Decay
Filters
a, w T, K, O aa, wa / ad, wd
DRC1 0x3A 0x40, 0x41, 0x42 0x3B / 0x3C
DRC2 0x3D 0x43, 0x44, 0x45 0x3E / 0x3F
Alpha Filter Structure
S
a –1
w
Z
B0265-01
Figure 45. DRC Structure

TAS5706
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Loudness Function
The TAS5706 provides a direct form I biquad for loudness on the subwoofer channel. The first biquad is
contained in a gain-compensation circuit that maintains the overall system gain at 1 or less to prevent clipping at
loud volume settings. This gain compensation is shown in Figure 46
1 if Vol £ 1/G
0 if Vol ³ 1/G + 1/Scale
1 - Scale (Vol - 1/G) otherwise
From To
Input Output
Mux Loudness Mux
Volume Biquad (0x23) Biquad (0x24)
Gain = G
Scale = 1/(1 - 1/G)

0 if Vol £ 1/G
1 if Vol ³ 1/G + 1/Scale
Scale (Vol - 1/G) otherwise
B0273-01
Figure 46. Biquad Gain Control Structure
Table 1. Loudness Table Example for Gain = 4, 1/G = 0.25, Scale = 1.33
Volume 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2
Biquad path 1 1 0.833 0.666 0.5 0.333 0.166 0 0 0 0 0 0 0 0 0
Direct path 0 0 0.166 0.333 0.5 0.666 0.833 1 1 1 1 1 1 1 1 1
Total gain 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
The biquads are implemented in a direct form-I architecture. The direct form-I structure provides a separate delay
element and mixer (gain coefficient) for each node in the biquad filter.
The five 26-bit (3.23) coefficients for the biquad are programmable via the I2C interface.
The following steps are involved in using a loudness biquad with the volume compensation feature:
1. Program the biquad with a loudness filter.
2. Program 0x26 (1/G) and 0x28 (scale).
3. Enable volume compensation in register 0x0E.

TAS5706
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b0
x(n) Magnitude y(n)

S Truncation
b1 a1
–1 –1
z z
b2 a2
–1 –1
z z
M0012-02
Figure 47. Biquad Filter

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BANK SWITCHING
The TAS5706 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in the TAS5706. The
TAS5706 has three full banks storing information, one for 32 kHz, one for 44.1/48 kHz, and one for all other data
rates. Combined with the clock-rate autodetection feature, bank switching allows the TAS5706 to detect
automatically a change in the input sample rate and switch to the appropriate bank without any MCU
intervention.
The TAS5706 supports three banks of coefficients to be updated during the initialization. One bank is for 32 kHz
, a second bank is for 44.1/48 kHz, and a third bank is for all other sample rates. An external controller updates
the three banks (see the I2C register mapping table for bankable locations) during the initialization sequence.
If the autobank switch is enabled (register 0x50, bits 2:0) , then the TAS5706 automatically swaps the
coefficients for subsequent sample rate changes, avoiding the need for any external controller intervention for a
sample rate change.
By default, bits 2:0 have the value 000; that means the bank switch is disabled. In that state, any update to
locations 0x29–0x3F go into the DAP. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to locations 0x29-0x3F updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank update. In automatic bank update, the TAS5706 automatically swaps banks
based on the sample rate.
In the headphone mode, speaker equalization and DRC are disabled, and they are restored upon returning to the
speaker mode.
Command sequences for initialization can be summarized as follows:
1. Enable factory trim for internal oscillator: Write to register 0x1B with a value 0x00.
2. Update coefficients: Coefficients can be loaded into DAP RAM using the manual bank mode.
OR
Use automatic bank mode.
a. Enable bank-1 mode: Write to register 0x50 with 0x01. Load the 32-kHz coefficients. TI ALE
can generate coefficients.
b. Enable bank-2 mode: Write to register 0x50 with 0x02. Load the 48-kHz coefficients.
c. Enable bank-3 mode: Write to register 0x50 with 0x03. Load the other coefficients.
d. Enable automatic bank switching by writing to register 0x50 with 0x04.
3. Bring the system out of all-channel shutdown: Write 0 to bit 6 of register 0x05.
4. Issue master volume: Write to register 0x07 with the volume value (0 db = 0x30).

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APPLICATION INFORMATION
Recovery From Error
Protection Mechanisms in the TAS5706

• SCP (short-circuit protection, OCP) protects against shorts across the load, to GND, and to PVCC.
• OTP turns off the device if Tdie (typical) > 150°C.
• UVP turns off the device if PVCC (typical) < 8.4 V
• OVP turns off the device if PVCC (typical) > 27.5 V
A short-circuit condition can be detected also by an external controller. The SCP error from the external power
stage is also fed into TAS5706. The VALID pin goes low in the event of a short circuit. The VALID pin can be
monitored by an external µC. The TAS5706 initiates a back-end error sequence by itself to recover from the
error, which involves settling VALID low for a programmable amount of time and then retrying to check whether
the SCP condition still exists.
• OTP turns on the device back when Tdie(typical) < 135°C.
• UVP turns on the device if PVCC (typical) is > 8.5 V.
• OVP turns on the device if PVCC (typical) is < 27.2 V.
Interchannel Delay (ICD) Settings
Recommended ICD Settings

Mode Description ICD1 ICD2 ICD3 ICD4 ICD5 ICD6
2.0 ch BD BTL 2 BTL channels, internal A(L+) = 19 C(R+) = 13 B(L–) = 7 D(R–) = 25 SM(S–) = –12 SP(S+) = –28
power stage only, BD (0x4C) (0x34) (0x1C) (0x64) (0xD0) (0x90)
mode
2.1 ch AD BTL 2 internal BTL channels, A(L+) = 23 C(R+) = 9 B(L–) = 21 D(R–) = 11 SM(S–) = –23 SP(S+) = –21
1 external BTL channel (0x5C) (0x24) (0x54) (0x2C) (0xA4) (0xAC)
using PBTL TAS5601,
AD mode
2.1 ch AD SE 2 internal SE channels (2 A(L+) = 15 B(R–) = –15 B(0) = 0 D(0) = 0 SM(S–) = –30 SP(S+) = –32
unused), 1 external BTL (0x3C) (0xC4) (0x00) (0x00) (0x88) (0x80)
channel using PBTL
TAS5601, AD mode
2.1 ch BD BTL 2 internal BTL channels, A(L+) = 19 C(R+) = 13 B(L–) = 7 D(R–) = 25 SM(S–) = –12 SP(S+) = –28
1 external BTL channel (0x4C) (0x34) (0x1C) (0x64 ) (0xD0) (0x90)
using PBTL TAS5601,
BD mode
3.0 ch AD 2SE + 2 internal SE channels + A(L+) = 15 B(R–) = –16 SM(0) = 0 SP(0) = 0 D(S–) = 0 C(S+) = 2
1 BTL 1 internal BTL channel, (0x3C) (0xC0) (0x00) (0x00) (0x00) (0x08)
AD mode
4.0 ch AD SE 4 internal SE channels A(L1+) = 8 B(R1–) = –24 C(L2+) = –8 D(R2–) = 24 SM(0) = 1 SP(0) = –1
(=0x20) (0xA0) (0xE0) (0x60) (0x04) (0xFC)
4.1 ch AD SE 4 internal SE channels + A(L1+) = 8 B(R1–) = –24 C(L2+) = –8 D(R2–)= 24 SM(S–) = 1 SP(S+) = –1
1 external BTL channel, (0x20) (0xA0) (xE0) (0x60) (0x04) (0xFC)
using PBTL TAS5601,
AD mode.
Calculation of Output Signal Level of TAS5706 Feedback Power Stage

(Gain Is independent of PVCC)
The gain of the TAS5706 is the total digital gain of the controller multiplied by the gain of the power stage.
For a half-bridge channel of the TAS5706 power stage, the gain is simply:
Power stage gain = 13 × VRMS / Modulation Level
Modulation level = fraction of full-scale modulation of the PWM signal at the input of the power stage.
VRMS = Audio voltage level at the output of the power stage = 13 × Modulation Level

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For the TAS5706 controller, the gain is the programmed digital gain multiplied by a scaling factor, called the
maximum modulation level. The maximum modulation level is derived from the modulation limit programmed in
the controller, which limits duty cycle to a set number of percent above 0% and below 100%. Setting the
modulation limit to 97.7% (default) limits the duty cycle between 2.3% and 97.7%.
Controller gain = digital gain × maximum modulation level × (modulation level/digital FFS)
Digital FFS = digital input fraction of full scale
Modulation limit = 97.7%
Maximum modulation level = 2 × modulation limit – 1 = 0.954
The output signal level of the TAS5706 can now be calculated.
VRMS = digital FFS × digital gain × maximum modulation level × 13
With the modulation limit set at the default level of 97.7%, this becomes:
VRMS = digital FFS × digital gain × 12.4 (Single-ended)
VRMS = digital FFS × digital gain × 24.8 (BTL)
Example: Input = –20 dbFS; volume = 0 dB; biquads = ALL PASS; modulation index = 97.7%; mode = BTL
Output VRMS = 24.8 × 0.1 × 1 = 2.48 V

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I2C SERIAL CONTROL COMMAND CHARACTERISTICS

The DAP has two groups of I2C commands. One set is commands that are designed specifically to be operated
while audio is streaming and that have built-in mechanisms to prevent noise, clicks, and pops. The other set
does not have this built-in protection.
Commands that are designed to be adjusted while audio is streaming:
• Master volume
• Master mute
• Individual channel volume
• Individual channel mute
Commands that are normally issued as part of initialization:
• Serial data interface format
• De-emphasis
• Sample-rate conversion
• Input multiplexer
• Output multiplexer
• Biquads
• Down mix
• Channel delay
• Enable/disable dc blocking
• Hard/soft unmute from clock error
• Enable/disable headphone outputs
(1)
Table 2. Serial Control Interface Register Summary
NO. OF INITIALIZATION
SUBADDRESS REGISTER NAME CONTENTS
BYTES VALUE
A u indicates unused bits.
0x00 Clock control register 1 Description shown in subsequent section 0x6C
0x01 Device ID register 1 Description shown in subsequent section 0x28
0x02 Error status register 1 Description shown in subsequent section 0x00
0x03 System control register 1 1 Description shown in subsequent section 0xA0
0x04 Serial data interface 1 Description shown in subsequent section 0x05
register
0x05 System control register 2 1 Description shown in subsequent section 0x40
0x06 Soft mute register 1 Description shown in subsequent section 0x00
0x07 Master volume 1 Description shown in subsequent section 0xFF (mute)
0x08 Channel 1 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x09 Channel 2 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0A Channel 3 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0B Channel 4 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0C HP volume 1 Description shown in subsequent section 0x30 (0 dB)
0x0D Channel 6 vol 1 Description shown in subsequent section 0x30 (0 dB)
0x0E Volume configuration 1 Description shown in subsequent section 0x91
register
0x0F 1 Reserved (2)
0x10 Modulation limit register 1 Description shown in subsequent section 0x02
0x11 IC delay channel 1 1 Description shown in subsequent section 0x4C
0x12 IC delay channel 2 1 Description shown in subsequent section 0x34
0x13 IC delay channel 3 1 Description shown in subsequent section 0x1C
(1) Biquad definition is given in Figure 47.

(2) Reserved registers should not be accessed.

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Table 2. Serial Control Interface Register Summary (continued)

BYTES VALUE
0x15 IC delay channel 5 1 Description shown in subsequent section 0xB0
0x17 Offset register 1 Reserved 0x00
0x18 1 Reserved (2)
0x19 PWM shutdown group 1 0x30
register
0x1A Start/stop period register 1 0x0A
0x1B Oscillator trim register 1 0x82
0x1C BKND_ERR register 1 0x02
0x1D–0x1F Reserved (2)
0x20 Input MUX register 4 Description shown in subsequent section 0x0089 777A
0x21 Downmix input MUX 4 Description shown in subsequent section 0x0000 4203
register
0x22 AM tuned frequency 4 Description shown in subsequent section 0x0000 0000
0x23 ch6_bq[2] (Loudness BQ) 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x24 ch6_bq[3] (post volume 20 u[31:26], b0[25:0] 0x0080 0000
BQ)
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x25 PWM MUX register Description shown in subsequent section 0x0102 1345
0x26 1/G register 4 u[31:26], x[25:0] 0x0080 0000
0x27 1 Reserved (3)
0x28 Scale register 4 u[31:26], x[25:0] 0x0080 0000
0x29 ch1_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2A ch1_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2B ch1_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000

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BYTES VALUE
0x2C ch1_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2D ch1_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2E ch1_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x2F ch1_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x30 ch2_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x31 ch2_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x32 ch2_bq[2] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x33 ch2_bq[3] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x34 ch2_bq[4] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000

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BYTES VALUE
0x35 ch2_bq[5] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x36 ch2_bq[6] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x37 ch6_bq[0] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x38 ch6_bq[1] 20 u[31:26], b0[25:0] 0x0080 0000
u[31:26], b1[25:0] 0x0000 0000
u[31:26], b2[25:0] 0x0000 0000
u[31:26], a1[25:0] 0x0000 0000
u[31:26], a2[25:0] 0x0000 0000
0x39 4 Reserved (4)
0x3A DRC1 ae 8 u[31:26], ae[25:0] 0x0080 0000
DRC1 (1 – ae) u[31:26], (1 – ae)[25:0] 0x0000 0000
0x3B DRC1 aa 8 u[31:26], aa[25:0] 0x0080 0000
DRC1 (1 – aa) u[31:26], (1 – aa)[25:0] 0x0000 0000
0x3C DRC1 ad 8 u[31:26], ad[25:0] 0x0080 0000
DRC1 (1 – ad) u[31:26], (1 – ad)[25:0] 0x0000 0000
0x3D DRC2 ae 8 u[31:26], ae[25:0] 0x0080 0000
DRC 2 (1 – ae) u[31:26], (1 – ae)[25:0] 0x0000 0000
0x3E DRC2 aa 8 u[31:26], aa[25:0] 0x0080 0000
DRC2 (1 – aa) u[31:26], (1 – aa)[25:0] 0x0000 0000
0x3F DRC2 ad 8 u[31:26], ad[25:0] 0x0080 0000
DRC2 (1 – ad) u[31:26], (1 – ad)[27::0] 0x0000 0000
0x40 DRC1-T 4 T1[31:0] 0xFDA2 1490
0x41 DRC1-K 4 u[31:26], k1[25:0] 0x0384 2109
0x42 DRC1-O 4 u[31:24], O[23:16], O1[15:0] 0x0008 4210
0x43 DRC2-T 4 T2[31:0] 0xFDA2 1490
0x44 DRC2-K 4 u[31:24], k2'[22:0] 0x0384 2109
0x45 DRC2-O 4 u[31:24], O2[25:0] 0x0008 4210
0x46 DRC control 4 u[31:2], ch6[1], ch1_5[0] 0x0000 0000
0x47–0x49 4 Reserved (4) 0x0000 0000
0x50 4 Bank update command register 0x0000 0000
(4)
0x51–0xFF 4 Reserved 0x0000 0000

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CLOCK CONTROL REGISTER (0x00)

In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates based on the sample rate and associated clock frequencies. In the auto-detect mode, the clocks
are automatically determined by the TAS5706. In this case, the clock control register contains the auto-detected
clock status as automatically detected (D7–D2). Bits D7–D5 selects the sample rate. Bits D4–D2 select the
MCLK frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must be
written to D0 to inform the DAP that the written clocks are valid.
Table 3. Clock Control Register (0x00)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 – – – – – fS = 32-kHz sample rate
0 1 0 – – – – – fS = 44.1-kHz sample rate
(1)
– – – 0 0 0 – – MCLK frequency = 64 × fS (2)
– – – 0 1 0 – – MCLK frequency = 192 × fS

– – – 1 1 1 – – Reserved
– – – – – – – – Reserved
– – – – – – 1 – Bit clock (SCLK) frequency = 48 × fS (5)
Bit clock (SCLK) frequency = 64 × fS or 32 × fS (selected in register
– – – – – – 0 –
0x04) (1)
(1)
– – – – – – – 0 Clock not valid (in manual mode only)
– – – – 1 Clock valid (in manual mode only)
(1) Default values are in bold.

(2) Rate not available for 32-, 44.1-, and 48-kHz data rates
(3) Rate not available for 32-kHz data rate
(4) Rate not available for 176.4-kHz and 192-kHz data rates
(5) Rate only available for 192-fS and 384-fS MCLK frequencies
DEVICE ID REGISTER (0x01)

The device ID register contains the ID code for the firmware revision.
Table 4. General Status Register (0x01)

(1)
0 – – – – – – – Default
– 0 1 0 1 0 0 0 Identification code

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ERROR STATUS REGISTER (0x02)

Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 5. Error Status Register (0x02)

– – – – – – – – MCLK error
– 1 – – – – – – PLL autolock error
– – 1 – – – – – SCLK error
– – – 1 – – – – LRCLK error
– – – – 1 – – – Frame slip
(1)
0 0 0 0 0 0 0 0 No errors
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 6. Error Status Register (0x02)

– 1 – – – – – – PLL autolock error
– – 1 – – – – – SCLK error
– – – 1 – – – – LRCLK error
– – – – 1 – – – Frame slip
(1)
0 0 0 0 0 0 0 0 No errors
SYSTEM CONTROL REGISTER 1 (0x03)

The system control register 1 has several functions:
Bit D7: If 0, the dc-blocking filter for each channel is disabled.

If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).
Bit D5: If 0, use soft unmute on recovery from clock error. This is a slow recovery.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery.
Bit D3: If 0, clock autodetect is enabled (default).
If 1, clock autodetect is disabled.
Bit D2: If 0, soft start is enabled (default).
If 1, soft start is disabled.
Bits D1–D0: Select de-emphasis
Table 7. System Control Register 1 (0x03)

0 – – – – – – – PWM high-pass (dc blocking) disabled
(1)
1 – – – – – – – PWM high-pass (dc blocking) enabled
(1)
– 0 – – – – – – Reserved
– – 0 – – – – – Soft unmute on recovery from clock error
(1)
– – 1 – – – – – Hard unmute on recovery from clock error
(1)
– – – 0 – – – – Reserved
(1)
– – – – 0 – – – Enable clock autodetect

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Table 7. System Control Register 1 (0x03) (continued)

– – – – 1 – – – Disable clock autodetect
(1)
– – – – – 0 – – Enable soft start
– – – – – 1 – – Disable soft start
(1)
– – – – – – 0 0 No de-emphasis
– – – – – – 0 1 Reserved
– – – – – – 1 0 De-emphasis for fS = 44.1 kHz
– – – – – – 1 1 De-emphasis for fS = 48 kHz
SERIAL DATA INTERFACE REGISTER (0x04)

As shown in NoLabel , TAS5706 supports 21 serial data modes. The default is 24-bit, I2S mode,
Serial Data Interface Control Register (0x04) Format

RECEIVE SERIAL DATA WORD
D7–D5 D4 D3 D2 D1 D0
INTERFACE FORMAT LENGTH
Right-justified 16 000 0 0 0 0 0
I2S 16 000 0 0 0 1 1
2
I S 20 000 0 0 1 0 0
I2S (1)
24 000 0 0 1 0 1
Left-justified 16 000 0 0 1 1 0
Reserved 000 0 1 0 0 1
Reserved 000 0 1 0 1 1
Reserved 000 0 1 1 0 0
Reserved 000 0 1 1 0 1
Reserved 000 0 1 1 1 0
Reserved 000 0 1 1 1 1
Reserved 000 1 0 0 0 0
2
I S (32 fS SCLK) 16 000 1 0 0 1 1
Left-justified (32 fS SCLK) 000 1 0 1 1 0
Reserved 000 1 1 0 0 1
Reserved 000 1 1 0 1 1
Reserved 000 1 1 1 0 1
SYSTEM CONTROL REGISTER 2 (0x05)

Bit D6 is a control bit and bit D5 is a configuration bit.
When bit D6 is set low, the system starts playing; otherwise, the outputs are shut down.
Bit D5 defines the configuration of the system, that is, it determines what configuration the system runs in when
bit D6 is set low. When this bit is asserted, all channels are switching. Otherwise, only a subset of the PWM
channels will run. The channels to shut down are defined in the shutdown group register (0x19). Bit D5 should
only be changed when bit D6 is set, meaning that it is only possible to switch configurations by resetting the DAP
and then restarting it again in the new configuration.

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Bit D3 defines which volume register is used to control the volume of the HP_PWMx outputs when in headphone
mode. When set to 0, the HP volume register (0x0C) controls the volume of the headphone outputs when in
headphone mode. When bit D3 is set to 1, the channel volume registers (0x08–0x0B, 0x0D) are used for all
modes (line out, headphone, speaker).
Bits D2–D1 define the output modes. The default is speaker mode with the headphone mode selectable via the
external HPSEL terminal. The device can also be forced into headphone mode by asserting bit D1 (all other
PWM channels are muted). Asserting bit D2 puts the device into a pseudo-line-out mode where the HP_PWMx
and all other PWM channels are active. Bit D3 must also be asserted in this mode, and the HP_PWMx volume is
controlled with the main speaker output volume controls via registers 0x08–0x0B and 0x0D..
Table 8. System Control Register 2 (0x05)

(1)
0 – – – – – – – Reserved
– 1 0 – – – – – All channels are shut down (hard mute). VALID1 = 0.
(2)
– 1 1 – – – – – All channels are shut down (hard mute). VALID1 = 0
When D6 is deasserted, all channels not belonging to shutdown group (SDG) are started.
– 0 0 – – – – –
SDG register is 0x19.
– 0 1 – – – – – When D6 is deasserted, all channels are started. VALID1 = 1. No channels in SDG1.
(2)
– – – 0 – – – – Reserved
Use HP volume register (0x0C) for adjusting headphone volume when in
– – – – 0 – – –
headphone mode. (2)
– – – – 1 – – – Use channel volume registers (0x08–0x0B, 0x0D) for all modes.
(2)
– – – – – 0 0 – Speaker mode. Hardware pin, HPSEL = 1, forces device into headphone mode.
– – – – – 0 1 – HP mode. This setting is logically ORed with external HPSEL pin.
Line out mode. Hardware pin, HPSEL, is ignored for this setting. HP_PWMx pins are
– – – – – 1 0 –
active.
– – – – – 1 1 – Reserved
(2)
– – – – – – – 0 Reserved

SOFT MUTE REGISTER (0x06)

Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle. Default is
0x00.
Table 9. Soft Mute Register (0x06)

– – – – – – – 1 Soft mute channel 1
– – – – – – 1 – Soft mute channel 2
– – – – – 1 – – Soft mute channel 3
– – – – 1 – – – Soft mute channel 4
– – 1 – – – – – Soft mute subwoofer channel (channel 6)
(1)
0 0 0 0 0 0 0 0 Unmute all channels

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VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D)

Step size is 0.5 dB.
Master volume – 0x07 (default is mute)

Channel-1 volume – 0x08 (default is 0 dB)
Channel-2 volume – 0x09 (default is 0 dB)
Channel-3 volume – 0x0A (default is 0 dB)
Channel-4 volume – 0x0B (default is 0 dB)
Headphone volume – 0x0C (default is 0 dB)
Channel-6 volume – 0x0D (default is 0 dB)
(subwoofer)
Table 10. Volume Register

0 0 0 0 0 0 0 0 24 dB
(1)
0 0 1 1 0 0 0 0 0 dB (default for individual channel volume)
1 1 1 1 1 1 1 0 –100 dB
(1)
1 1 1 1 1 1 1 1 MUTE (default for master volume); 50% duty cycle at output – SOFT MUTE
VOLUME CONFIGURATION REGISTER (0x0E)
Bit D7: Reserved = 1

Bit D6: If 0, then biquad 1 (BQ1) volume compensation part only is disabled (default). If 1, then BQ1
volume compensation is enabled.
Bit D4: Reserved = 1
Bit D3: Reserved
Bits D2–D0: Volume slew rate (Used to control volume change and MUTE ramp rates)
Table 11. Volume Control Register (0x0E)

1 – – – – – – – Reserved (must be 1)
(1)
– 0 – – – – – – Disable biquad volume compensation
– 1 – – – – – – Enable biquad volume compensation
(1)
– – 0 – – – – – Reserved
(1)
– – – 1 – – – – Reserved (must be 1)
(1)
– – – – 0 – – – Reserved
– – – – – 0 0 0 Volume slew 512 steps (44 ms volume ramp time)
– – – – – 0 0 1 Volume slew 1024 steps (1) (88 ms volume ramp time)
– – – – – 1 X X Reserved

TAS5706
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MODULATION LIMIT REGISTER (0x10)

Set modulation limit. See the appropriate power stage data sheet for recommended modulation limits.
Table 12. Modulation Limit Register (0x10)

LIMIT
D7 D6 D5 D4 D3 D2 D1 D0 MIN WIDTH [DCLKs] MODULATION LIMIT
[DCLKs]
– – – – – 0 0 0 1 2 99.2%
– – – – – 0 0 1 2 4 98.4%
– – – – – 0 1 0 3 6 97.7%
– – – – – 0 1 1 4 8 96.9%
– – – – – 1 0 0 5 10 96.1%
– – – – – 1 0 1 6 12 95.3%
– – – – – 1 1 0 7 14 94.5%
– – – – – 1 1 1 8 16 93.8%
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, 0x14, 0x15, 0x16)

Internal PWM Channels 1, 2, 3, 4, 5, and 6 are mapped into registers 0x11, 0x12 ,0x13, 0x14, 0x15, and 0x16.
Table 13. Channel Interchannel Delay Register Format

BITS DEFINITION D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
Minimum absolute delay, 0 DCLK cycles, default for
0 0 0 0 0 0 0 0
channel 0 (1)
0 1 1 1 1 1 0 0 Maximum positive delay, 31 × 4 DCLK cycles
1 0 0 0 0 0 0 0 Maximum negative delay, –32 × 4 DCLK cycles
0 0 Unused bits
A
SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Delay = (value) × 4 DCLKs

(1)
0x11 0 1 0 0 1 1 0 0 Default value for channel 1 19
(1)
(1)
(1)
(1)
0x15 1 1 0 1 0 0 0 0 Default value for channel 5 –12
(1)
0x16 1 0 0 1 0 0 0 0 Default value for channel 6 -28
OFFSET REGISTER (0x17)

The offset register is mapped into 0x17.
Table 14. Channel Offset Register Format

(1)
0 0 0 0 0 0 0 0 Minimum absolute offset, 0 DCLK cycles, default for channel 0
1 1 1 1 1 1 1 1 Maximum absolute offset, 255 DCLK cycles

TAS5706
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PWM SHUTDOWN GROUP REGISTER (0x19)

Settings of this register determine which PWM channels are active. The default is 0x30 for two BTL output
channels and no external subwoofer output. The functionality of this register is tied to the state of bit D5 in the
system control register.
This register defines which channels belong to the shutdown group (SDG). If a 1 is set in the shutdown group
register, that particular channel is not started following an exit out of all-channel shutdown command (if bit D5 is
set to 0 in system control register 2, 0x05).
Table 15. Shutdown Group Register

(1)
0 – – – – – – – Reserved
(1)
– 0 – – – – – – Reserved
– – 1 – – – – – Channel 6 belongs to shut down group.
(1)
– – 0 – – – – – Channel 6 does not belong to shutdown group.
– – – 1 – – – – Channel 5 belongs to shutdown group.
(1)
– – – 0 – – – – Channel 5 does not belong to shutdown group.
– – – – 1 – – – Channel 4 belongs to shutdown group.
(1)
– – – – 0 – – – Channel 4 does not belong to shutdown group.
– – – – – 1 – – Channel 3 belongs to shutdown group.
(1)
– – – – – 0 – – Channel 3 does not belong to shutdown group.
– – – – – – 1 – Channel 2 belongs to shutdown group.
(1)
– – – – – – 0 – Channel 2 does not belong to shutdown group.
– – – – – – – 1 Channel 1 belongs to shutdown group.
(1)
– – – – – – – 0 Channel 1 does not belong to shutdown group.

TAS5706
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START/STOP PERIOD REGISTER (0x1A)

This register is used to control the soft-start and soft-stop period when starting up or shutting down channels.
The value in this register determines the time for which the PWM inputs switch at 50% duty cycle. This helps
reduce pops and clicks at start-up and shutdown.
D7 is used to configure the output stage in a bridge-tied mode or a single-ended mode.
Table 16. Start/Stop Period Register (0x1A)

0 – – – – – – – Bridge-tied load (BTL)
1 – – – – – – – Single-ended load (SE)
– – – 0 0 – – – No 50% duty cycle start/stop period
– – – 0 1 0 0 0 16.5-ms 50% duty cycle start/stop period
– – – 1 1 1 1 1 13,196.4-ms 50% duty cycle start/stop period

TAS5706
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OSCILLATOR TRIM REGISTER (0x1B)

The TAS5706 PWM processor contains an internal oscillator for PLL reference. This reduces system cost
because an external reference is not required. Currently, TI recommends a trim resistor value of 18.2 kΩ (1%).
This should be connected between OSC_RES and DVSS.
The factory-trim procedure simply enables the factory trim that was previously done at the factory.
Note that trim always must be run following reset of the device.
Oscillator Trim Enable Procedure Example

Write data 0x00 to register 0x1B (enable factory trim).
Table 17. Oscillator Trim Register (0x1B)

(1)
1 – – – – – – – Reserved
(1)
– 0 – – – – – – Oscillator trim not done (read-only)
– 1 – – – – – – Oscillator trim done (read only)
(1)
– – 0 0 0 0 – – Reserved
– – – – – – 0 – Select factory trim (Write a 0 to select factory trim; default is 1.)
(1)
– – – – – – 1 – Factory trim disabled
(1)
– – – – – – – 0 Reserved
BKND_ERR REGISTER (0x1C)

When a back-end error signal is received (BKND_ERR = LOW), all the output stages are reset by setting all
PWM, VALID1, and VALID2 signals LOW. Subsequently, the modulator waits approximately for the time listed in
Table 18 before initiation of a reset.
Table 18. BKND_ERR Register (0x1C)

– – – – 0 0 0 0 Set back-end reset period to 0 ms (Reserved)
– – – – 0 0 0 1 Set back-end reset period to 150 ms (Reserved)
(1)
– – – – 0 0 1 0 Set back-end reset period to 299 ms
– – – – 1 1 – – Set back-end reset period to 1496 ms

TAS5706
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INPUT MULTIPLEXER REGISTER (0x20)

The hex value for each nibble is the channel number. For each input multiplexer, any input from SDIN1, SDIN2
can be mapped to any internal TAS5706 channel.
Table 19. Input Multiplexer Register (0x20)

0 0 0 0 0 0 0 0 Reserved = 0x00

0 – – – – – – – Channel-1 AD mode
(1)
1 – – – – – – – Channel-1 BD mode
(1)
– 0 0 0 – – – – SDIN1-L to channel 1
– 0 0 1 – – – – SDIN1-R to channel 1
– 0 1 0 – – – – SDIN2-L to channel 1
– 0 1 1 – – – – SDIN2-R to channel 1
– 1 0 0 – – – – Reserved
– 1 0 1 – – – – Reserved
– 1 1 0 – – – – Ground (0) to channel 1
– 1 1 1 – – – – Reserved
– – – – 0 – – – Channel 2 AD mode
(1)
– – – – 1 – – – Channel 2 BD mode
– – – – – 0 0 0 SDIN1-L to channel 2
(1)
– – – – – 0 0 1 SDIN1-R to channel 2
– – – – – 0 1 0 SDIN2-L to channel 2
– – – – – 0 1 1 SDIN2-R to channel 2
– – – – – 1 0 0 Reserved
– – – – – 1 0 1 Reserved
– – – – – 1 1 0 Ground (0) to channel 2
– – – – – 1 1 1 Reserved

TAS5706
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Table 19. Input Multiplexer Register (0x20) (continued)

0 – – – – – – – Reserved
– 0 0 0 – – – – SDIN1-L to channel 3
– 0 0 1 – – – – SDIN1-R to channel 3
– 0 1 0 – – – – SDIN2-L to channel 3
– 0 1 1 – – – – SDIN2-R to channel 3
– 1 0 0 – – – – Reserved
– 1 0 1 – – – – Reserved
(2)
– 1 1 1 – – – – Ch1 (BTL–) to channel 3—BTL pair for channel 1
(2)
– – – – 0 – – – Reserved
– – – – – 0 0 0 SDIN1-L to channel 4
– – – – – 0 0 1 SDIN1-R to channel 4
– – – – – 0 1 0 SDIN2-L to channel 4
– – – – – 0 1 1 SDIN2-R to channel 4
– – – – – 1 0 0 Reserved
– – – – – 1 0 1 Reserved
(2)
– – – – – 1 1 1 Ch2 (BTL–) to channel 4—BTL pair for channel 2
0 – – – – – – – Reserved
– 1 0 0 – – – – Reserved
– 1 0 1 – – – – Reserved
– 1 1 1 – – – – Ch6 (BTL–) to channel 5—BTL pair to channel 6
(2)
– – – – 0 – – – Channel 6 AD mode
– – – – 1 – – – Channel 6 BD mode
– – – – – 0 0 0 SDIN1-L to channel 6
– – – – – 0 0 1 SDIN1-R to channel 6
(2)
– – – – – 0 1 0 SDIN2-L to channel 6
– – – – – 0 1 1 SDIN2-R to channel 6
– – – – – 1 0 0 Reserved
– – – – – 1 0 1 Reserved
(2)
– – – – – 1 1 1 Reserved

TAS5706
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DOWNMIX INPUT MULTIPLEXER REGISTER (0x21)
Bits D31–D16: Unused

Bits D15–D13: Reserved
Bit D12: If 1, selects downmix data L’ to internal channel L
If 0, selects channel 1 data (from input mux 1) to DAP internal channel 1
Bit D11: If 1, selects downmix data R’ to the DAP internal channel 2
If 0, selects channel 2 data (from input mux 2) to DAP internal channel 2
Bit D1: If 1, enable data from input mux 2 to downmix block
If 0, disable data from input mux 2 to downmix block
Bit D0: If 1, enable data from input mux 1 to downmix block
If 0, disable data from input mux 1 to downmix block
Table 20. Downmix Input Multiplexer Register

– – – – – – – – Unused

– – – – – – – – Unused

(1)
0 1 0 – – – – – Reserved
– – – 1 – – – – Enable downmix data L’ to channel 1
(1)
– – – 0 – – – – Enable channel 1 data to channel 1
– – – – 1 – – – Enable downmix data R’ to channel 2
(1)
– – – – 0 – – – Enable channel 2 data to channel 2
– – – – – 0 – – Reserved
– – – – – – 0 0 Enable channel 6 data to channel 6
– – – – – – 0 1 Enable bass management on channel 6
(1)
– – – – – – 1 0 Enable (L'+R')/2 downmix data on channel 6
– – – – – – 1 1 Reserved
(1)
– – – – – – – 1 Enable data from input multiplexer 1 to downmix block
– – – – – – – 0 Disable data from input multiplexer 1 to downmix block
(1)
– – – – – – 1 – Enable data from input multiplexer 2 to downmix block
– – – – – – 0 – Disable data from input multiplexer 2 to downmix block
(1)
0 0 0 0 0 0 – – Reserved

TAS5706
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AM MODE REGISTER (0x22)

See the PurePath Digital™ AM Interference Avoidance application note (SLEA040).
Table 21. AM Mode Register (0x22)

D20 D19 D18 D17 D16 FUNCTION
(1)
0 – – – – AM mode disabled
1 – – – – AM mode enabled
(1)
– 0 0 – – Select sequence 1
(1)
– – – 0 – IF frequency = 455 kHz
– – – 1 – IF frequency = 262.5 kHz
(1)
– – – – 0 Use BCD tuned frequency
– – – – 1 Use binary tuned frequency
Table 22. AM Tuned Frequency Register in BCD Mode

0 0 0 X – – – – BCD frequency (1000s kHz)
– – – – X X X X BCD frequency (100s kHz)
(1)
0 0 0 0 0 0 0 0 Default value
X X X X – – – – BCD frequency (10s kHz)
– – – – X X X X BCD frequency (1s kHz)
(1)
OR
Table 23. AM Tuned Frequency Register in Binary Mode

0 0 0 0 0 X X X Binary frequency
(1)
X X X X X X X X Binary frequency
(1)

TAS5706
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PWM OUTPUT MUX REGISTER (0x25)

This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D30–D25: Selects which PWM channel is output to HPL_PWM and HPR_PWM
Bits D23–D20: Selects which PWM channel is output to OUT_A
Bits D19–D16: Selects which PWM channel is output to OUT_B
Bits D15–D12: Selects which PWM channel is output to OUT_C
Bits D11–D08: Selects which PWM channel is output to OUT_D
Bits D07–D04: Selects which PWM channel is output to SUB_PWM–
Bits D03–D00: Selects which PWM channel is output to SUB_PWM+
Note that channels are encoded so that channel 1 = 0x00, channel 2 = 0x01, …, channel 6 = 0x05.
Table 24. PWM Output Mux Register (0x25)

(1)
0 – – – – – – – Reserved
(1)
– 0 0 0 – – – – Multiplex channel 1 to HPL_PWM
– – – – 0 – – – Reserved
– – – – – 0 0 0 Multiplex channel 1 to HPR_PWM
(1)

(1)
0 0 0 0 – – – – Multiplex channel 1 to OUT_A
– – – – 0 0 0 0 Multiplex channel 1 to OUT_B
(1)

0 0 0 0 – – – – Multiplex channel 1 to OUT_C
(1)

TAS5706
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Table 24. PWM Output Mux Register (0x25) (continued)

– – – – 0 0 0 0 Multiplex channel 1 to OUT_D
(1)
0 0 0 0 – – – Multiplex channel 1 to SUB_PWM–
0 0 0 1 – – – – Multiplex channel 2 to SUB_PWM–
(2)
– – – – 0 0 0 0 Multiplex channel 1 to SUB_PWM+
(2)
LOUDNESS BIQUAD GAIN INVERSE REGISTER (0x26)

Bit D6 of the volume configuration register (0x0E) enables/disables gain compensation for BQ1. D6 = 0 disables
gain compensation (default); D6 = 1 enables gain compensation. Max/min biquad gain = ±4.
Table 25. Loudness Biquad Gain Inverse Register (3.23 Format)

CONTENT DEFINITION
(1)
u[31:26], x[25:0] 1/G
(1) G = gain of the biquad
LOUDNESS SCALE REGISTER (0x28)
Table 26. Loudness Scale Register (3.23 Format)

CONTENT DEFINITION
(1)
u[31:26], x[25:0] Scale = 1/(1 – 1/G)
(1) G = gain of the biquad

TAS5706
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DRC CONTROL (0x46)

(1)
– – – – – – – 0 DRC1 (satellite channels) turned OFF
– – – – – – – 1 DRC1 (satellite channels) turned ON
(1)
– – – – – – 0 – DRC2 (subchannel ) turned OFF
– – – – – – 1 – DRC2 (subchannel ) turned ON
(1)
– – – – – 0 – – DRC1 independent of channel 3
– – – – – 1 – – DRC1 dependent of channel 3
(1)
– – – – 0 – – – DRC1 independent of channel 4
– – – – 1 – – – DRC1 dependent of channel 4
BANK SWITCH AND HEADPHONE DRC/EQ CONTROL (0x50)
Table 27. Bank Switching Command

(1)
– – – – – 0 0 0 No bank switching. All updates to DAP
– – – – – 0 0 1 Configure bank 1 (32 kHz)
– – – – – 0 1 0 Configure bank 2 (44.1/48 kHz)
– – – – – 0 1 1 Configure bank 3 (88.2/96 kHz and above)
– – – – – 1 0 0 Automatic bank selection
– – 0 0 0 – – – Reserved
(1)
– 0 – – – – – – DRC disabled in headphone mode
– 1 – – – – – – DRC enabled in headphone mode
(1)
0 – – – – – – – EQ disabled in headphone mode
1 – – – – – – – EQ enabled in headphone mode

PACKAGE OPTION ADDENDUM
www.ti.com 29-Apr-2009
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
TAS5706PAP NRND HTQFP PAP 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5706PAPG4 NRND HTQFP PAP 64 160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5706PAPR NRND HTQFP PAP 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5706PAPRG4 NRND HTQFP PAP 64 1000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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20-W Stereo Digital Audio Power Amplifier with EQ and DRC

SIMPLIFIED APPLICATION DIAGRAMS

Bridge-Tied Load (BTL) Mode

2 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): TAS5706

Single-Ended (SE) 2.1 Mode

* Refer to TI Application Note (SLOA119) on LC filter design for SE or BTL configuration.

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 3

Single-Ended (SE) 4.0 Mode

MUTE OUT_C LCSE*

* Refer to TI Application Note (SLOA119) on LC filter design for SE configuration.

4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

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Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5

64-TERMINAL, HTQFP PACKAGE (TOP VIEW)

(1) TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output

6 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): TAS5706

TERMINAL FUNCTIONS (continued)

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 7

TERMINAL FUNCTIONS (continued)

ABSOLUTE MAXIMUM RATINGS

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RECOMMENDED OPERATING CONDITIONS

PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS

PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9

10 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

Product Folder Link(s): TAS5706

AC Characteristics, TA = 25°C, PVCC_X, AVCC = 18 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless

(1) All measurement in AD mode.

AC Characteristics, TA = 25°C, PVCC_X, AVCC = 12 V, AVDD, DVDD = 3.3 V, RL = 8 Ω (unless

(1) All measurement in AD mode.

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 11

SERIAL AUDIO PORTS SLAVE MODE

Figure 1. Slave Mode Serial Data Interface Timing

12 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated

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I2C SERIAL CONTROL PORT OPERATION

Figure 2. SCL and SDA Timing

Figure 3. Start and Stop Conditions Timing

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 13

RESET TIMING (RESET)

RESET Earliest time

td(VALID_LOW) £ 300 ns td(run)

System initialization. Start system

Figure 4. Reset Timing

POWER-DOWN (PDN) TIMING

td(VALID_LOW) £ 300 ms td(STARTUP)

Figure 5. Power-Down Timing

BACK-END ERROR (BKND_ERR)

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VALID Normal Normal

Figure 6. Error Recovery Timing

MUTE TIMING (MUTE)

VOLUME Normal Normal

Figure 7. Mute Timing

Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 15

HEADPHONE SELECT (HPSEL)

Figure 8. HPSEL Timing for Headphone Insertion