A B C D E

1 1

Compal Confidential
2 2

HBL51 Schematics Document

Intel Yonah Processor with 945GM/945PM + DDRII + ICH7M

3
2005-11-03 3

REV: 0.2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 1 of 47
A B C D E
 A B C D E

Compal Confidential
Thermal Sensor Clock Generator
Model Name : HBL50 Fan Control
page 47
Yonah
F75383M ICS9LPRS325
page 4 page 14
File Name : LA-2921 uPGA-478 Package
page 4,5
1 1
PSB
H_A#(3..31) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 17 page 15 page 16

DVI LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2

Intel 945PM/GM Dual Channel BANK 0, 1, 2, 3 page 12,13
CH7307C SDVO
page 17 1.8V DDRII 400/533
uFCBGA-1466
page 6,7,8,9,10,11

DMI New Card LAN(GbE) MINI CARD x2 USB conn x4 Bluetooth

BCM5789
Socket page 29 page 26 page 28 page 29 Conn page 34
PCI Express USB port 3, 7 USB port 0, 2 USB port5
PCI BUS USB port 1
2
3.3V 33 MHz Intel ICH7-M 3.3V 48MHz 2

IDSEL:AD16 IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 3.3V 24.576MHz/48Mhz HD Audio

(PIRQE#, (PIRQG/H#, (PIRQF#, (PIRQA#, BGA-652
GNT#2, GNT#3, GNT#3, GNT#2, 3.3V ATA-100
REQ#2) REQ#3) REQ#3) REQ#2) IDE
S-ATA
page 18,19,20,21
IEEE 1394 Mini PCI LAN (10/100) CardBus
VT6311S socket BCM4401E ENE CB714 CDROM MDC 1.5 HDA Codec
page 30 (WLAN) page 26 page 24 port 0 port 0 Conn. Conn ALC883
page 23 page 42 page 36
(TV-Tuner)
page 28

1394 Conn. RJ45 6 in 1 S-ATA HDD SATA-to-IDE HDD

Slot 0 socket SPIF3811-HV096
page 30 page 27
page 25 page 25
Conn.page 22 page 22
Conn.
page 22
Audio AMP Subwoofer
LPC BUS page 37 page 37
3 3

RTC CKT. Super I/O TPM1.2 Phone Jack x3

page 35
ENE KB910Q page 37
SMsC LPC47N207 SLB9635 TT 1.2
page 32 page 31 page 31

Power On/Off CKT. Switch/B Conn.

USB port4, 6
page 35
page 34
Touch Pad Int.KBD
page 35 page 33 FIR
TFDU6102-TR3
page 31
DC/DC Interface CKT. LCM Conn. EC I/O Buffer BIOS
page 34
page 40 page 33 page 33

Power Circuit DC/DC MEDIA/B Conn.

page 34
page 40,41,42,43 CIR
44,45,46,47 page 34
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 2 of 47
A B C D E
 A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VSB VSB always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2

BOARD ID Table BTO Option Table

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 UMA's DVI 7307@
CardBus(SD) AD20 2 PIRQA/PIRQB
1 LAN(10/100) 4401@
13 94 AD16 0 PIRQE
2 LAN(GIGA) 5789@
LAN(10/100) AD17 3 PIRQF
3 MINI CARD1 MINI1@
Mini-PCI(WLAN/TV-Tuner) AD18 1 PIRQG/PORQH
4 MINI CARD2 MINI2@
5 SATA-to-IDE 8040@
6 PATA PATA@
7 GRAPEVINE GRA@
MEDIA/B MEDIA@
SKU ID Table CIR CIR@
EC SM Bus1 address EC SM Bus2 address FIR FIR@
3
Device Address Device Address
SKU ID SKU GENEVA GEN@ 3

Smart Battery 0001 011X b Fintek F75383M 1001 100X b

0 LCM LCM@
EEPROM(24C16/02) 1010 000X b
1 GM TVOUT TVOUT@
GMT G781-1 1001 101X b
2 1394 6311S@
3 CARDREADER 4IN1@
4 Sub-woofer SUB@
5 5789&5787 8789@
6 4401&5789 0189@
ICH7M SM Bus address 7
Device Address

Clock Generator 1101 001Xb

(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 3 of 47
A B C D E
 5 4 3 2 1

JP18A H_D#[0..63]
H_D#[0..63] (6)
H_A#[3..31] H_A#3 J4 E22 H_D#0
(6) H_A#[3..31]
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 +3VS
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 C624
H_A#7 A6# D3# H_D#4 0.1U_0402_16V4Z
M1 A7# D4# F23
D H_A#8 H_D#5 D
N2 A8# D5# G25 1 2
H_A#9 J1 E25 H_D#6
H_A#10 A9# D6# H_D#7
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 1 U37
H_A#14 A13# D10# H_D#11 C625
P4 A14# D11# J23 1 VDD SCLK 8 EC_SMB_CK2 (32)
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13 2200P_0402_50V7K THERMDA
R1 A16# D13# F26 2 D+ SDATA 7 EC_SMB_DA2 (32)
H_A#17 H_D#14 2
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15 THERMDC 3 6
H_A#19 A18# D15# H_D#16 D- ALERT#
R3 A19# D16# N22
H_A#20 W6 K25 H_D#17 4 5
H_A#21 A20# D17# H_D#18 THERM# GND
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20 ADM1032ARMZ-2REEL_MSOP8
U2 A23# D20# L25
H_A#24 R4 L22 H_D#21
H_A#25 A24# D21# H_D#22 F75383M_MSOP8
T5 A25# ADDR GROUP DATA GROUP D22# L23
H_A#26 T3 M23 H_D#23
H_A#27 A26# D23# H_D#24
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27
H_A#31 A30# D27# H_D#28
Y1 A31# D28# R24
L26 H_D#29
H_REQ#[0..4] H_REQ#0 D29# H_D#30
(6) H_REQ#[0..4] K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34 +1.05VS
L5 REQ4# D34# V24
V26 H_D#35
D35# H_D#36
(6) H_ADSTB#0 L2 ADSTB0# D36# W25
C H_D#37 C
(6) H_ADSTB#1 V4 ADSTB1# D37# U23
U25 H_D#38
D38# H_D#39 ITP_TDI R15 56_0402_5%
D39# U22 2 1
AB25 H_D#40
D40# H_D#41 ITP_TDO R17 56_0402_5%
D41# W22 2 1
Y23 H_D#42
D42# H_D#43 ITP_TMS R16 56_0402_5%
(14) CLK_CPU_BCLK A22 BCLK0 D43# AA26 2 1
A21 HOST CLK Y26 H_D#44
(14) CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45 H_PROCHOT# R500 2 1 75_0402_5%
D45# H_D#46
D46# AC26
AA24 H_D#47 ITP_BPM#5 R18 2 1 56_0402_5%
D47# H_D#48
(6) H_ADS# H1 ADS# D48# AC22
E2 AC23 H_D#49 H_IERR# R501 2 1 56_0402_5%
(6) H_BNR# BNR# D49#
G5 AB22 H_D#50
(6) H_BPRI# BPRI# D50# H_D#51
(6) H_BR0# F1 BR0# D51# AA21
H5 AB21 H_D#52
(6) H_DEFER# DEFER# D52# H_D#53
(6) H_DRDY# F21 DRDY# D53# AC25
G6 AD20 H_D#54
(6) H_HIT# HIT# D54#
E4 CONTROL AE22 H_D#55
(6) H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
IERR# D56# H_D#57
(6) H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
(6) H_RESET# RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
H_RS#[0..2] H_RS#0 D60# H_D#61
(6) H_RS#[0..2] F3 RS0# D61# AF25
H_RS#1 F4 AF22 H_D#62
H_RS#2 RS1# D62# H_D#63 ITP_TRST# R19 56_0402_5%
G3 RS2# D63# AF26 2 1
(6) H_TRDY# G2 TRDY# ITP_TCK R20 2 1 56_0402_5%
DINV0# J26 H_DINV#0 (6)
M26 TEST1 R513 2 1 @ 1K_0402_5%
DINV1# H_DINV#1 (6)
PAD ITP_BPM#0 AD4 V23
B T5 BPM0# DINV2# H_DINV#2 (6) B
PAD ITP_BPM#1 AD3 AC20 TEST2 R512 2 1 51_0402_5%
T3 BPM1# DINV3# H_DINV#3 (6)
PAD ITP_BPM#2 AD1
T1 BPM2#
PAD ITP_BPM#3 AC4
T4 BPM3#
DSTBN0# H23 H_DSTBN#0 (6)
ITP_DBRRESET# C20 M24
(20) ITP_DBRESET# DBR# DSTBN1# H_DSTBN#1 (6)
(6) H_DBSY# E1 DBSY# DSTBN2# W24 H_DSTBN#2 (6)
(19) H_DPSLP# B5 DPSLP# DSTBN3# AD23 H_DSTBN#3 (6)
(19,47) H_DPRSTP# E5 DPRSTP# DSTBP0# G22 H_DSTBP#0 (6)
(6) H_DPWR# D24 DPWR# DSTBP1# N25 H_DSTBP#1 (6)
PAD ITP_BPM#4 AC2 MISC Y25
T2 PRDY# DSTBP2# H_DSTBP#2 (6)
ITP_BPM#5 AC1 AE24
PREQ# DSTBP3# H_DSTBP#3 (6)
H_PROCHOT# D21
PROCHOT#
H_PW RGOOD D6
(19) H_PWRGOOD PWRGOOD
H_CPUSLP# D7
(6) H_CPUSLP# SLP#
ITP_TCK AC5
ITP_TDI TCK
AA6 TDI A20M# A6 H_A20M# (19)
ITP_TDO AB3 A5
TDO FERR# H_FERR# (19)
TEST1 C26 C4
TEST1 IGNNE# H_IGNNE# (19)
TEST2 D25 B3
TEST2 INIT# H_INIT# (19)
ITP_TMS AB5 C6
TMS LINT0 H_INTR (19)
ITP_TRST# AB6 B4
TRST# LINT1 H_NMI (19)
LEGACY CPU
THERMAL
THERMDA A24 D5
THERMDC THERMDA DIODE STPCLK# H_STPCLK# (19)
A25 THERMDC SMI# A3 H_SMI# (19)
(6,19) H_THERMTRIP# C7 THERMTRIP#

FOX_PZ47903-2741-42_YONAH

A A

Layout Note:
THERMDA & THERMDC Trace / Space = 10 / 10 mil
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah (1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 4 of 47
5 4 3 2 1
 5 4 3 2 1

Layout Note:
Route VCCSENSE and VSSSENSE traces at 27.4Ohms
with 50 mil spacing.
Place PU and PD wihin 1 inch of CPU.

+CPU_CORE
+CPU_CORE JP18B +CPU_CORE JP18C
(47) VCCSENSE
R499 1 100_0402_1% VCCSENSE
3 x 330uF(9mOhm/3)
2 AF7 VCCSENSE VSS AB26 AE18 VCC VSS K1
R498 1 2 100_0402_1% VSSSENSE AE7 AA25 1 1 1 AE17 J2
D VSSSENSE VSS @ VCC VSS D
(47) VSSSENSE VSS AD25 AB15 VCC VSS M2
+ C614 + C609 + C621
20mils VSS AE26 AA15 VCC VSS N1
+1.5VS B26 VCCA VSS AB23 AD15 VCC VSS T1
AC24 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 AC15 R2
VSS 2 2 2 VCC VSS
1 1 +1.05VS K6 VCCP VSS AF24 2005/11/02 AF15 VCC VSS V2
C628 C626 J6 AE23 AE15 W1
VCCP VSS VCC VSS
M6 VCCP VSS AA22 South Side Secondary AB14 VCC VSS A26
10U_0805_10V4Z 0.01U_0402_16V7K N6 AD22 AA13 D26
2 2
T6
VCCP
VCCP
YONAH VSS
VSS AC21 AD14
VCC
VCC
VSS
VSS C25
R6 VCCP VSS AF21 AC13 VCC VSS F25
K21 AB19 +CPU_CORE AF14 B24
VCCP VSS VCC VSS
J21 VCCP VSS AA19 3 x 330uF(9mOhm/3) AE13 VCC VSS A23
Layout Note: M21 VCCP VSS AD19 AB12 VCC VSS D23
N21 AC19 2005/11/02 AA12 E24
Place C14 near Pin B26 T21
VCCP
VCCP
VSS
VSS AF19
1
+ C620
2005/11/02
+ C608
1
+ C619
1
AD12
VCC
VCC
YONAH VSS
VSS B21
R21 VCCP VSS AE19 AC12 VCC VSS C22
V21 AB16 @ AF12 F22
VCCP VSS VCC VSS

POWER, GROUNG, RESERVED SIGNALS AND NC

W21 AA16 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 AE12 E21
VCCP VSS 2 2 2 VCC VSS
V6 VCCP VSS AD16 AB10 VCC VSS B19
G21 VCCP VSS AC16 AB9 VCC VSS A19
VSS AF16 North Side Secondary AA10 VCC VSS D19
VSS AE16 AA9 VCC VSS C19
(47) PSI# AE6 PSI# VSS AB13 AD10 VCC VSS F19
AA14 +CPU_CORE AD9 E19
VSS VCC VSS
(47) CPU_VID0 AD6 VID0 VSS AD13 AC10 VCC VSS B16
+1.05VS (47) CPU_VID1 AF5 AC14 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AC9 A16
VID1 VSS VCC VSS
(47) CPU_VID2 AE5 VID2 VSS AF13 1 1 1 1 1 1 1 1 AF10 VCC VSS D16
(47) CPU_VID3 AF4 AE14 C31 C33 C35 C32 C30 C28 C26 C24 AF9 C16
VID3 VSS VCC VSS
1

(47) CPU_VID4 AE3 VID4 VSS AB11 AE10 VCC POWER, GROUND VSS F16
R511 (47) CPU_VID5 AF2 AA11 AE9 E16
1K_0402_1% VID5 VSS 2 2 2 2 2 2 2 2 VCC VSS
(47) CPU_VID6 AE2 VID6 VSS AD11 AB7 VCC VSS B13
AC11 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M AA7 A14
C VSS (Place these capacitors on South side,Secondary Layer) VCC VSS C
AF11 AD7 D13
2

GTL_REF0 VSS VCC VSS

1 2 AD26 GTLREF VSS AE11 AC7 VCC VSS C14
R510 2K_0402_1% AB8 +CPU_CORE B20 F13
VSS VCC VSS
(14) CPU_BSEL0 B22 BSEL0 VSS AA8 A20 VCC VSS E14
(14) CPU_BSEL1 B23 AD8 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M F20 B11
BSEL1 VSS VCC VSS
(14) CPU_BSEL2 C21 BSEL2 VSS AC8 1 1 1 1 1 1 E20 VCC VSS A11
AF8 C623 C618 C616 C613 C22 C20 B18 D11
COMP0 VSS VCC VSS
R26 COMP0 VSS AE8 B17 VCC VSS C11
COMP1 U26 AA5 A18 F11
COMP2 COMP1 VSS 2 2 2 2 2 2 VCC VSS
U1 COMP2 VSS AD5 A17 VCC VSS E11
COMP3 V1 AC6 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M D18 B8
COMP3 VSS (Place these capacitors on South side,Secondary Layer) VCC VSS
VSS AF6 D17 VCC VSS A8
VSS AB4 C18 VCC VSS D8
E7 AC3 +CPU_CORE C17 C8
+CPU_CORE VCC VSS VCC VSS
AB20 VCC VSS AF3 F18 VCC VSS F8
AA20 AE4 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M F17 E8
VCC VSS VCC VSS
AF20 VCC VSS AB1 1 1 1 1 1 1 E18 VCC VSS G26
AE20 AA2 C611 C607 C29 C27 C25 C23 E17 K26
VCC VSS VCC VSS
AB18 AD2 B15 J25
BSEL2 BSEL1 BSEL0 BCLK AB17
VCC VSS
AE1 A15
VCC VSS
M25
VCC VSS 2 2 2 2 2 2 VCC VSS
AA18 VCC VSS B6 D15 VCC VSS N26
AA17 C5 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C15 T26
VCC VSS (Place these capacitors on North side,Secondary Layer) VCC VSS
0 0 1 133 AD18 VCC VSS F5 F15 VCC VSS R25
AD17 VCC VSS E6 E15 VCC VSS V25
AC18 H6 +CPU_CORE B14 W26
VCC VSS VCC VSS
0 1 1 166 AC17 VCC VSS J5
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
A13 VCC VSS H24
AF18 VCC VSS M5 D14 VCC VSS G23
AF17 VCC VSS L6 1 1 1 1 1 1 1 1 C13 VCC VSS K23
P6 C21 C19 C622 C617 C615 C612 C610 C606 F14 L24
VSS VCC VSS
VSS R5 E13 VCC VSS P24
D2 RSVD VSS V5 B12 VCC VSS N23
2 2 2 2 2 2 2 2
F6 RSVD VSS U6 A12 VCC VSS T23
B 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M B
D3 RSVD VSS Y6 D12 VCC VSS U24
C1 A4 (Place these capacitors on North side,Secondary Layer) C12 Y24
RSVD VSS VCC VSS
AF1 RSVD VSS D4 F12 VCC VSS W23
D22 RSVD VSS E3 E12 VCC VSS H21
C23 RSVD VSS H3 B10 VCC VSS J22
C24 RSVD VSS G4 +CPU-CORE C,uF ESR, mohm ESL,nH B9 VCC VSS M22
AA1 K4 A10 L21
AA4
RSVD VSS
L3 Decoupling A9
VCC VSS
P21
RSVD VSS VCC VSS
AB2 RSVD VSS P3 SPCAP,Polymer 6X330uF 9m ohm/6 1.8nH/6 D10 VCC VSS R22
AA3 RSVD VSS N4 D9 VCC VSS V22
M4 RSVD VSS T4 MLCC 0805 X5R 32X22uF 3m ohm/32 0.6nH/32 C10 VCC VSS U21
N5 RSVD VSS U3 C9 VCC VSS Y21
R515 1 2 27.4_0402_1% COMP0 T2 Y3 F10
RSVD VSS VCC
V3 RSVD VSS W4 F9 VCC
R514 1 2 54.9_0402_1% COMP1 B2 D1 E10
RSVD VSS VCC
C3 RSVD VSS C2 E9 VCC
R13 1 2 27.4_0402_1% COMP2 T22 F2 +1.05VS B7
RSVD VSS VCC
B25 RSVD VSS G1 A7 VCC
R14 1 2 54.9_0402_1% COMP3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z F7 VCC
1
1 1 1 1 1 1 1 1
FOX_PZ47903-2741-42_YONAH C13 + C34 C36 C38 C37 C16 C18 C17 C15 FOX_PZ47903-2741-42_YONAH
@ @
220U_D2_2VMR15
2 2 2 2 2 2 2 2 2
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
COMP1, COMP3 layout : Space 25mils (55Ohms)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Yonah (2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 5 of 47
5 4 3 2 1
 5 4 3 2 1

945GM(A-1)(QJ15)[ES2]: SA000005970
945GM(A-2)(QK44)[ES3]: SA000005980
945PM(A-2)(QK46)[ES3]: SA00000UV10

(4) H_D#[0..63] H_A#[3..31] (4) Description at page10

U40A U40B
H_D#0 F1 H9 H_A#3
H_D#1 HD0# HA3# H_A#4 DMI_ITX_MRX_N0 MCH_CLKSEL0
J1 HD1# HA4# C9 (20) DMI_ITX_MRX_N0 AE35 DMIRXN0 CFG0 K16 MCH_CLKSEL0 (14)
H_D#2 H1 E11 H_A#5 DMI_ITX_MRX_N1 AF39 K18 MCH_CLKSEL1
HD2# HA5# (20) DMI_ITX_MRX_N1 DMIRXN1 CFG1 MCH_CLKSEL1 (14)
H_D#3 J6 G11 H_A#6 DMI_ITX_MRX_N2 AG35 J18 MCH_CLKSEL2
HD3# HA6# (20) DMI_ITX_MRX_N2 DMIRXN2 CFG2 MCH_CLKSEL2 (14)
H_D#4 H3 F11 H_A#7 DMI_ITX_MRX_N3 AH39 F18 CFG3 PAD
HD4# HA7# (20) DMI_ITX_MRX_N3 DMIRXN3 CFG3 T15
H_D#5 K2 G12 H_A#8 E15 CFG4 PAD
D HD5# HA8# CFG4 T8 D
H_D#6 G1 F9 H_A#9 F15 CFG5
HD6# HA9# CFG5 CFG5 (10)
H_D#7 G2 H11 H_A#10 DMI_ITX_MRX_P0 AC35 E18 CFG6 PAD
HD7# HA10# (20) DMI_ITX_MRX_P0 DMIRXP0 CFG6 T14
H_D#8 K9 J12 H_A#11 DMI_ITX_MRX_P1 AE39 D19 CFG7
HD8# HA11# (20) DMI_ITX_MRX_P1 DMIRXP1 CFG7 CFG7 (10)
H_D#9 K1 G14 H_A#12 DMI_ITX_MRX_P2 AF35 D16 CFG8 PAD
HD9# HA12# (20) DMI_ITX_MRX_P2 DMIRXP2 CFG8 T11

DMI
H_D#10 K7 D9 H_A#13 DMI_ITX_MRX_P3 AG39 G16 CFG9
HD10# HA13# (20) DMI_ITX_MRX_P3 DMIRXP3 CFG9 CFG9 (10)
H_D#11 J8 J14 H_A#14 E16 CFG10 PAD
HD11# HA14# CFG10 T12
H_D#12 H4 H13 H_A#15 D15 CFG11
HD12# HA15# CFG11 CFG11 (10)
H_D#13 J3 J15 H_A#16 DMI_MTX_IRX_N0 AE37 G15 CFG12
HD13# HA16# (20) DMI_MTX_IRX_N0 DMITXN0 CFG12 CFG12 (10)
H_D#14 K11 F14 H_A#17 DMI_MTX_IRX_N1 AF41 K15 CFG13
HD14# HA17# (20) DMI_MTX_IRX_N1 DMITXN1 CFG13 CFG13 (10)

CFG
H_D#15 G4 D12 H_A#18 DMI_MTX_IRX_N2 AG37 C15 CFG14 PAD
HD15# HA18# (20) DMI_MTX_IRX_N2 DMITXN2 CFG14 T7
H_D#16 T10 A11 H_A#19 DMI_MTX_IRX_N3 AH41 H16 CFG15 PAD
HD16# HA19# (20) DMI_MTX_IRX_N3 DMITXN3 CFG15 T13
H_D#17 W11 C11 H_A#20 G18 CFG16
HD17# HA20# CFG16 CFG16 (10)
H_D#18 T3 A12 H_A#21 H15 CFG17 PAD
HD18# HA21# CFG17 T9
H_D#19 U7 A13 H_A#22 DMI_MTX_IRX_P0 AC37 J25 CFG18
HD19# HA22# (20) DMI_MTX_IRX_P0 DMITXP0 CFG18 CFG18 (10)
H_D#20 U9 E13 H_A#23 DMI_MTX_IRX_P1 AE41 K27 CFG19
HD20# HA23# (20) DMI_MTX_IRX_P1 DMITXP1 CFG19 CFG19 (10)
H_D#21 U11 G13 H_A#24 DMI_MTX_IRX_P2 AF37 J26 CFG20
HD21# HA24# (20) DMI_MTX_IRX_P2 DMITXP2 CFG20 CFG20 (10)
H_D#22 T11 F12 H_A#25 DMI_MTX_IRX_P3 AG41
HD22# HA25# (20) DMI_MTX_IRX_P3 DMITXP3
H_D#23 W9 B12 H_A#26
H_D#24 HD23# HA26# H_A#27 CLK_MCH_3GPLL
T1 HD24# HA27# B14 G_CLKP AG33 CLK_MCH_3GPLL (14)
H_D#25 T8 C12 H_A#28 AY35 AF33 CLK_MCH_3GPLL#
HD25# HA28# (12) DDRA_CLK0 SM_CK0 G_CLKN CLK_MCH_3GPLL# (14)
H_D#26 T4 A14 H_A#29 AR1
HD26# HA29# (12) DDRA_CLK1 SM_CK1
H_D#27 W7 C14 H_A#30 AW7 A27 CLK_DREF_96M#

CLK
HD27# HA30# (13) DDRB_CLK0 SM_CK2 D_REF_CLKN CLK_DREF_96M# (14)
H_D#28 U5 D14 H_A#31 AW40 A26 CLK_DREF_96M
HD28# HA31# (13) DDRB_CLK1 SM_CK3 D_REF_CLKP CLK_DREF_96M (14)
H_D#29 T9
H_D#30 HD29# CLK_DREF_SSC#
W6 HD30# (12) DDRA_CLK0# AW35 SM_CK0# D_REF_SSCLKN C40 CLK_DREF_SSC# (14)
H_D#31 T5 AT1 D41 CLK_DREF_SSC
H_D#32 AB7
HD31#
HD32#
HOST HREQ#0 D8 H_REQ#0
H_REQ#[0..4] (4) (12)
(13)
DDRA_CLK1#
DDRB_CLK0# AY7
SM_CK1#
SM_CK2#
D_REF_SSCLKP CLK_DREF_SSC (14)
H_D#33 AA9 G8 H_REQ#1 AY40 H32 MCH_CLKREQ#
HD33# HREQ#1 (13) DDRB_CLK1# SM_CK3# CLK_REQ# MCH_CLKREQ# (14)
H_D#34 W4 B8 H_REQ#2
H_D#35 HD34# HREQ#2 H_REQ#3
W3 HD35# HREQ#3 F8 (12) DDRA_CKE0 AU20 SM_CKE0

DDR MUXING
H_D#36 Y3 A8 H_REQ#4 AT20
HD36# HREQ#4 (12) DDRA_CKE1 SM_CKE1
H_D#37 Y7 BA29 A3
C HD37# (13) DDRB_CKE0 SM_CKE2 NC0 C
H_D#38 W5 AY29 A39
HD38# (13) DDRB_CKE1 SM_CKE3 NC1
H_D#39 Y10 B9 H_ADSTB#0 A4
HD39# HADSTB#0 H_ADSTB#0 (4) NC2
H_D#40 AB8 C13 H_ADSTB#1 AW13 A40
HD40# HADSTB#1 H_ADSTB#1 (4) (12) DDRA_SCS#0 SM_CS0# NC3
H_D#41 W2 AW12 AW1
HD41# (12) DDRA_SCS#1 SM_CS1# NC4
H_D#42 AA4 AG1 CLK_MCH_BCLK# AY21 AW41
HD42# HCLKN CLK_MCH_BCLK# (14) (13) DDRB_SCS#0 SM_CS2# NC5
H_D#43 AA7 AG2 CLK_MCH_BCLK AW21 AY1
HD43# HCLKP CLK_MCH_BCLK (14) (13) DDRB_SCS#1 SM_CS3# NC6
H_D#44 AA2 BA1

NC
H_D#45 HD44# H_DSTBN#0 M_OCDOCMP0 NC7
AA6 HD45# HDSTBN#0 K4 H_DSTBN#0 (4) T17 PAD AL20 SM_OCDCOMP0 NC8 BA2
H_D#46 AA10 T7 H_DSTBN#1 PAD M_OCDOCMP1 AF10 BA3
HD46# HDSTBN#1 H_DSTBN#1 (4) T6 SM_OCDCOMP1 NC9
H_D#47 Y8 Y5 H_DSTBN#2 BA39
H_D#48 HD47# HDSTBN#2 H_DSTBN#3 H_DSTBN#2 (4) NC10
AA1 HD48# HDSTBN#3 AC4 H_DSTBN#3 (4) (12) DDRA_ODT0 BA13 SM_ODT0 NC11 BA40
H_D#49 AB4 K3 H_DSTBP#0 BA12 BA41
HD49# HDSTBP#0 H_DSTBP#0 (4) (12) DDRA_ODT1 SM_ODT1 NC12
H_D#50 AC9 T6 H_DSTBP#1 AY20 C1
HD50# HDSTBP#1 H_DSTBP#1 (4) +1.8V (13) DDRB_ODT0 SM_ODT2 NC13
H_D#51 AB11 AA5 H_DSTBP#2 AU21 AY41
HD51# HDSTBP#2 H_DSTBP#2 (4) (13) DDRB_ODT1 SM_ODT3 NC14
H_D#52 AC11 AC5 H_DSTBP#3 B2
H_D#53 HD52# HDSTBP#3 H_DSTBP#3 (4) R47 SMRCOMPN NC15
AB3 HD53# 1 2 80.6_0402_1% AV9 SM_RCOMPN NC16 B41
+1.05VS H_D#54 AC2 R46 1 2 80.6_0402_1% SMRCOMPP AT9 C41
H_D#55 HD54# H_DINV#0 SM_RCOMPP NC17
AD1 HD55# HDINV#0 J7 H_DINV#0 (4) NC18 D1
H_D#56 AD9 W8 H_DINV#1 AK1
H_D#57 HD56# HDINV#1 H_DINV#2 H_DINV#1 (4) SMVREF SM_VREF0
AC1 HD57# HDINV#2 U3 H_DINV#2 (4) AK41 SM_VREF1
H_D#58 AD7 AB10 H_DINV#3 T32
HD58# HDINV#3 H_DINV#3 (4) RESERVED1
2

2
54.9_0402_1%

54.9_0402_1%

H_D#59 AC6 R32

H_D#60 HD59# PM_BMBUSY# RESERVED2
AB5 HD60# (20) PM_BMBUSY# G28 PM_BMBUSY# RESERVED3 F3
R530

R532

H_D#61 AD10 B7 H_RESET# PM_EXTTS#0 F25 F7

HD61# HCPURST# H_RESET# (4) (12,13) PM_EXTTS#0 PM_EXTTS0# RESERVED4

RESERVED
PM
H_D#62 AD4 E8 H_ADS# PM_EXTTS#1 H26 AG11
HD62# HADS# H_ADS# (4) PM_EXTTS1# RESERVED5
H_D#63 AC8 E7 H_TRDY# (4,19) H_THERMTRIP# H_THERMTRIP# G6 AF11
H_TRDY# (4)
1

HD63# HTRDY# H_DPWR# GMCH_PWROK AH33 PM_THERMTRIP# RESERVED6

HDPWR# J9 H_DPWR# (4) PWROK RESERVED7 H7
H8 H_DRD Y# 1 2 PLTRST_R# AH34 J19
HDRDY# H_DRDY# (4) (18,20,23,26,31,32) PLT_RST# RSTIN# RESERVED8
J13 C3 H_DEFER# R128 100_0402_1% A41
HVREF0 HDEFER# H_DEFER# (4) RESERVED9
H_VREF K13 D4 H_HITM# (18) MCH_ICH_SYNC# K28 A34
HVREF1 HHITM# H_HITM# (4) ICH_SYNC# RESERVED10
H_XRCOMP E1 D3 H_HIT# D28
HXRCOMP HHIT# H_HIT# (4) RESERVED11
H_XSCOMP E2 B3 H_LOCK# D27
B HXSCOMP HLOCK# H_LOCK# (4) RESERVED12 B
H_YRCOMP Y1 C7 H_BR0# A35
HYRCOMP HBREQ0# H_BR0# (4) RESERVED13
H_YSCOMP U1 C6 H_BNR#
HYSCOMP HBNR# H_BNR# (4)
H_SWNG0 E4 F6 H_BPRI# CALISTOGA_FCBGA1466~D
HXSWING HBPRI# H_BPRI# (4)
H_SWNG1 W1 A7 H_DBSY#
HYSWING HDBSY# H_DBSY# (4)
E3 H_CPUSLP# Layout Note:
HCPUSLP# H_CPUSLP# (4)
24.9_0402_1%

24.9_0402_1%

SMVREF trace
1

width and spacing

R531

R529

B4 H_RS#0
HRS0# H_RS#1
HRS1# E6 is 20/20.
D6 H_RS#2
HRS2# R127 @ 0_0402_5%
H_RS#[0..2] (4)
2

GMCH_PWROK 1 2 VGATE
+1.8V VGATE (14,20,47)
CALISTOGA_FCBGA1466~D
R130 0_0402_5%
1 2 SYS_PWROK
SYS_PWROK (20,35)

2
R577
100_0402_1%
Layout Note:

1
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / SMVREF
H_SWNG1 trace width and spacing is 10/20.
2
0.1U_0402_16V4Z

+3VS
1 R578 R111
+1.05VS +1.05VS 100_0402_1% 10K_0402_5%
C46

PM_EXTTS#0 1 2
+1.05VS
1

2 R100
1

1
221_0603_1%

221_0603_1%

10K_0402_5%
2

100_0402_1%

1 2 PM_EXTTS#1 1 2
(20,47) PM_DPRSLPVR
R528

R527

R121 0_0402_5% @
R60

A A
2

H_SWNG0 H_SWNG1
1

H_VREF
0.1U_0402_16V4Z

0.1U_0402_16V4Z
2

2
100_0402_1%

100_0402_1%
0.1U_0402_16V4Z

1 1
1

200_0603_1%

1
R53

R44

C48

R526

C641
C66

2 2 Security Classification Compal Secret Data Compal Electronics, Inc.

1

2 2005/06/20 2006/06/20 Title

Issued Date Deciphered Date
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (1/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 6 of 47
5 4 3 2 1
 5 4 3 2 1

DDRB_SDQ[0..63]
(13) DDRB_SDQ[0..63]
DDRA_SDQ[0..63]
(12) DDRA_SDQ[0..63] DDRB_SMA[0..13]
(13) DDRB_SMA[0..13]
DDRA_SMA[0..13]
D
(12) DDRA_SMA[0..13] D

U40D U40E

AU12 AJ35 DDRA_SDQ0 AT24 AK39 DDRB_SDQ0

(12) DDRA_SBS0# SA_BS0 SA_DQ0 (13) DDRB_SBS0# SB_BS0 SB_DQ0
AV14 AJ34 DDRA_SDQ1 AV23 AJ37 DDRB_SDQ1
(12) DDRA_SBS1# SA_BS1 SA_DQ1 (13) DDRB_SBS1# SB_BS1 SB_DQ1
BA20 AM31 DDRA_SDQ2 AY28 AP39 DDRB_SDQ2
(12) DDRA_SBS2# SA_BS2 SA_DQ2 (13) DDRB_SBS2# SB_BS2 SB_DQ2
AM33 DDRA_SDQ3 AR41 DDRB_SDQ3
SA_DQ3 DDRA_SDQ4 SB_DQ3 DDRB_SDQ4
SA_DQ4 AJ36 SB_DQ4 AJ38
(12) DDRA_SDM[0..7] AK35 DDRA_SDQ5 (13) DDRB_SDM[0..7] AK38 DDRB_SDQ5
DDRA_SDM0 SA_DQ5 DDRA_SDQ6 DDRB_SDM0 SB_DQ5 DDRB_SDQ6
AJ33 SA_DM0 SA_DQ6 AJ32 AK36 SB_DM0 SB_DQ6 AN41
DDRA_SDM1 AM35 AH31 DDRA_SDQ7 DDRB_SDM1 AR38 AP41 DDRB_SDQ7
DDRA_SDM2 SA_DM1 SA_DQ7 DDRA_SDQ8 DDRB_SDM2 SB_DM1 SB_DQ7 DDRB_SDQ8
AL26 SA_DM2 SA_DQ8 AN35 AT36 SB_DM2 SB_DQ8 AT40
DDRA_SDM3 AN22 AP33 DDRA_SDQ9 DDRB_SDM3 BA31 AV41 DDRB_SDQ9
DDRA_SDM4 SA_DM3 SA_DQ9 DDRA_SDQ10 DDRB_SDM4 SB_DM3 SB_DQ9 DDRB_SDQ10
AM14 SA_DM4 SA_DQ10 AR31 AL17 SB_DM4 SB_DQ10 AU38
DDRA_SDM5 AL9 AP31 DDRA_SDQ11 DDRB_SDM5 AH8 AV38 DDRB_SDQ11
DDRA_SDM6 SA_DM5 SA_DQ11 DDRA_SDQ12 DDRB_SDM6 SB_DM5 SB_DQ11 DDRB_SDQ12
AR3 SA_DM6 SA_DQ12 AN38 BA5 SB_DM6 SB_DQ12 AP38
DDRA_SDM7 AH4 AM36 DDRA_SDQ13 DDRB_SDM7 AN4 AR40 DDRB_SDQ13
SA_DM7 SA_DQ13 DDRA_SDQ14 SB_DM7 SB_DQ13 DDRB_SDQ14
SA_DQ14 AM34 SB_DQ14 AW38
AN33 DDRA_SDQ15 AY38 DDRB_SDQ15
SA_DQ15 DDRA_SDQ16 SB_DQ15 DDRB_SDQ16
SA_DQ16 AK26 SB_DQ16 BA38
AL27 DDRA_SDQ17 AV36 DDRB_SDQ17
DDRA_SDQS0 SA_DQ17 DDRA_SDQ18 DDRB_SDQS0 SB_DQ17 DDRB_SDQ18
(12) DDRA_SDQS0 AK33 SA_DQS0 SA_DQ18 AM26 (13) DDRB_SDQS0 AM39 SB_DQS0 SB_DQ18 AR36
DDRA_SDQS1 AT33 AN24 DDRA_SDQ19 DDRB_SDQS1 AT39 AP36 DDRB_SDQ19
(12) DDRA_SDQS1 DDRA_SDQS2 SA_DQS1 SA_DQ19 DDRA_SDQ20 (13) DDRB_SDQS1 DDRB_SDQS2 SB_DQS1 SB_DQ19 DDRB_SDQ20
AN28 AK28 AU35 BA36

DDR SYS MEMORY A

DDR SYS MEMORY B

(12) DDRA_SDQS2 DDRA_SDQS3 SA_DQS2 SA_DQ20 DDRA_SDQ21 (13) DDRB_SDQS2 DDRB_SDQS3 SB_DQS2 SB_DQ20 DDRB_SDQ21
(12) DDRA_SDQS3 AM22 SA_DQS3 SA_DQ21 AL28 (13) DDRB_SDQS3 AR29 SB_DQS3 SB_DQ21 AU36
C DDRA_SDQS4 DDRA_SDQ22 DDRB_SDQS4 DDRB_SDQ22 C
(12) DDRA_SDQS4 AN12 SA_DQS4 SA_DQ22 AM24 (13) DDRB_SDQS4 AR16 SB_DQS4 SB_DQ22 AP35
DDRA_SDQS5 AN8 AP26 DDRA_SDQ23 DDRB_SDQS5 AR10 AP34 DDRB_SDQ23
(12) DDRA_SDQS5 DDRA_SDQS6 SA_DQS5 SA_DQ23 DDRA_SDQ24 (13) DDRB_SDQS5 DDRB_SDQS6 SB_DQS5 SB_DQ23 DDRB_SDQ24
(12) DDRA_SDQS6 AP3 SA_DQS6 SA_DQ24 AP23 (13) DDRB_SDQS6 AR7 SB_DQS6 SB_DQ24 AY33
DDRA_SDQS7 AG5 AL22 DDRA_SDQ25 DDRB_SDQS7 AN5 BA33 DDRB_SDQ25
(12) DDRA_SDQS7 SA_DQS7 SA_DQ25 DDRA_SDQ26 (13) DDRB_SDQS7 SB_DQS7 SB_DQ25 DDRB_SDQ26
SA_DQ26 AP21 SB_DQ26 AT31
AN20 DDRA_SDQ27 AU29 DDRB_SDQ27
DDRA_SDQS0# SA_DQ27 DDRA_SDQ28 DDRB_SDQS0# SB_DQ27 DDRB_SDQ28
(12) DDRA_SDQS0# AK32 SA_DQS0# SA_DQ28 AL23 (13) DDRB_SDQS0# AM40 SB_DQS0# SB_DQ28 AU31
DDRA_SDQS1# AU33 AP24 DDRA_SDQ29 DDRB_SDQS1# AU39 AW31 DDRB_SDQ29
(12) DDRA_SDQS1# DDRA_SDQS2# SA_DQS1# SA_DQ29 DDRA_SDQ30 (13) DDRB_SDQS1# DDRB_SDQS2# SB_DQS1# SB_DQ29 DDRB_SDQ30
(12) DDRA_SDQS2# AN27 SA_DQS2# SA_DQ30 AP20 (13) DDRB_SDQS2# AT35 SB_DQS2# SB_DQ30 AV29
DDRA_SDQS3# AM21 AT21 DDRA_SDQ31 DDRB_SDQS3# AP29 AW29 DDRB_SDQ31
(12) DDRA_SDQS3# DDRA_SDQS4# SA_DQS3# SA_DQ31 DDRA_SDQ32 (13) DDRB_SDQS3# DDRB_SDQS4# SB_DQS3# SB_DQ31 DDRB_SDQ32
(12) DDRA_SDQS4# AM12 SA_DQS4# SA_DQ32 AR12 (13) DDRB_SDQS4# AP16 SB_DQS4# SB_DQ32 AM19
DDRA_SDQS5# AL8 AR14 DDRA_SDQ33 DDRB_SDQS5# AT10 AL19 DDRB_SDQ33
(12) DDRA_SDQS5# DDRA_SDQS6# SA_DQS5# SA_DQ33 DDRA_SDQ34 (13) DDRB_SDQS5# DDRB_SDQS6# SB_DQS5# SB_DQ33 DDRB_SDQ34
(12) DDRA_SDQS6# AN3 SA_DQS6# SA_DQ34 AP13 (13) DDRB_SDQS6# AT7 SB_DQS6# SB_DQ34 AP14
DDRA_SDQS7# AH5 AP12 DDRA_SDQ35 DDRB_SDQS7# AP5 AN14 DDRB_SDQ35
(12) DDRA_SDQS7# SA_DQS7# SA_DQ35 DDRA_SDQ36 (13) DDRB_SDQS7# SB_DQS7# SB_DQ35 DDRB_SDQ36
SA_DQ36 AT13 SB_DQ36 AN17
AT12 DDRA_SDQ37 AM16 DDRB_SDQ37
SA_DQ37 DDRA_SDQ38 SB_DQ37 DDRB_SDQ38
SA_DQ38 AL14 SB_DQ38 AP15
DDRA_SMA0 AY16 AL12 DDRA_SDQ39 DDRB_SMA0 AY23 AL15 DDRB_SDQ39
DDRA_SMA1 SA_MA0 SA_DQ39 DDRA_SDQ40 DDRB_SMA1 SB_MA0 SB_DQ39 DDRB_SDQ40
AU14 SA_MA1 SA_DQ40 AK9 AW24 SB_MA1 SB_DQ40 AJ11
DDRA_SMA2 AW16 AN7 DDRA_SDQ41 DDRB_SMA2 AY24 AH10 DDRB_SDQ41
DDRA_SMA3 SA_MA2 SA_DQ41 DDRA_SDQ42 DDRB_SMA3 SB_MA2 SB_DQ41 DDRB_SDQ42
BA16 SA_MA3 SA_DQ42 AK8 AR28 SB_MA3 SB_DQ42 AJ9
DDRA_SMA4 BA17 AK7 DDRA_SDQ43 DDRB_SMA4 AT27 AN10 DDRB_SDQ43
DDRA_SMA5 SA_MA4 SA_DQ43 DDRA_SDQ44 DDRB_SMA5 SB_MA4 SB_DQ43 DDRB_SDQ44
AU16 SA_MA5 SA_DQ44 AP9 AT28 SB_MA5 SB_DQ44 AK13
DDRA_SMA6 AV17 AN9 DDRA_SDQ45 DDRB_SMA6 AU27 AH11 DDRB_SDQ45
DDRA_SMA7 SA_MA6 SA_DQ45 DDRA_SDQ46 DDRB_SMA7 SB_MA6 SB_DQ45 DDRB_SDQ46
AU17 SA_MA7 SA_DQ46 AT5 AV28 SB_MA7 SB_DQ46 AK10
DDRA_SMA8 AW17 AL5 DDRA_SDQ47 DDRB_SMA8 AV27 AJ8 DDRB_SDQ47
DDRA_SMA9 SA_MA8 SA_DQ47 DDRA_SDQ48 DDRB_SMA9 SB_MA8 SB_DQ47 DDRB_SDQ48
AT16 SA_MA9 SA_DQ48 AY2 AW27 SB_MA9 SB_DQ48 BA10
DDRA_SMA10 AU13 AW2 DDRA_SDQ49 DDRB_SMA10 AV24 AW10 DDRB_SDQ49
DDRA_SMA11 SA_MA10 SA_DQ49 DDRA_SDQ50 DDRB_SMA11 SB_MA10 SB_DQ49 DDRB_SDQ50
AT17 SA_MA11 SA_DQ50 AP1 BA27 SB_MA11 SB_DQ50 BA4
DDRA_SMA12 AV20 AN2 DDRA_SDQ51 DDRB_SMA12 AY27 AW4 DDRB_SDQ51
DDRA_SMA13 SA_MA12 SA_DQ51 DDRA_SDQ52 DDRB_SMA13 SB_MA12 SB_DQ51 DDRB_SDQ52
AV12 SA_MA13 SA_DQ52 AV2 AR23 SB_MA13 SB_DQ52 AY10
AT3 DDRA_SDQ53 AY9 DDRB_SDQ53
B SA_DQ53 DDRA_SDQ54 SB_DQ53 DDRB_SDQ54 B
SA_DQ54 AN1 SB_DQ54 AW5
AL2 DDRA_SDQ55 AY5 DDRB_SDQ55
SA_DQ55 DDRA_SDQ56 SB_DQ55 DDRB_SDQ56
(12) DDRA_SCAS# AY13 SA_CAS# SA_DQ56 AG7 (13) DDRB_SCAS# AR24 SB_CAS# SB_DQ56 AV4
AW14 AF9 DDRA_SDQ57 AU23 AR5 DDRB_SDQ57
(12) DDRA_SRAS# SA_RAS# SA_DQ57 (13) DDRB_SRAS# SB_RAS# SB_DQ57
AY14 AG4 DDRA_SDQ58 AR27 AK4 DDRB_SDQ58
(12) DDRA_SWE# SA_WE# SA_DQ58 (13) DDRB_SWE# SB_WE# SB_DQ58
PAD SA_RCVENIN# AK23 AF6 DDRA_SDQ59 PAD SB_RCVENIN# AK16 AK3 DDRB_SDQ59
T18 SA_RCVENIN# SA_DQ59 T10 SB_RCVENIN# SB_DQ59
PAD SA_RCVENOUT# AK24 AG9 DDRA_SDQ60 PAD SB_RCVENOUT# AK18 AT4 DDRB_SDQ60
T19 SA_RCVENOUT# SA_DQ60 T16 SB_RCVENOUT# SB_DQ60
AH6 DDRA_SDQ61 AK5 DDRB_SDQ61
SA_DQ61 DDRA_SDQ62 SB_DQ61 DDRB_SDQ62
SA_DQ62 AF4 SB_DQ62 AJ5
AF8 DDRA_SDQ63 AJ3 DDRB_SDQ63
SA_DQ63 SB_DQ63
check layout check layout
CALISTOGA_FCBGA1466~D CALISTOGA_FCBGA1466~D

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (2/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 7 of 47
5 4 3 2 1
 5 4 3 2 1

D D

U40C
H27 D40 PEG_COMP 1 2 +1.5VS_PCIE
(17) SDVO_SDAT SDVOCTRL_DATA EXP_COMPI
H28 D38 10mils R138 24.9_0402_1%
(17) SDVO_SCLK SDVOCTRL_CLK EXP_COMPO
F34 PCIE_GTX_C_MRX_N0
TXOUT0+ EXP_RXN0 PCIE_GTX_C_MRX_N1 T32 PAD
(15) TXOUT0+ B37 LA_DATA0 EXP_RXN1 G38
TXOUT1+ B34 H34 PCIE_GTX_C_MRX_N2
(15) TXOUT1+ LA_DATA1 EXP_RXN2
TXOUT2+ A36 J38 PCIE_GTX_C_MRX_N3 T33 PAD
(15) TXOUT2+ LA_DATA2 EXP_RXN3
L34 PCIE_GTX_C_MRX_N4 T34 PAD
TXOUT0- EXP_RXN4 PCIE_GTX_C_MRX_N5 T35 PAD
(15) TXOUT0- C37 LA_DATA#0 EXP_RXN5 M38
TXOUT1- B35 N34 PCIE_GTX_C_MRX_N6 T36 PAD
(15) TXOUT1- LA_DATA#1 EXP_RXN6
TXOUT2- A37 P38 PCIE_GTX_C_MRX_N7 T37 PAD
(15) TXOUT2- LA_DATA#2 EXP_RXN7
R34 PCIE_GTX_C_MRX_N8 T38 PAD
TZOUT0+ EXP_RXN8 PCIE_GTX_C_MRX_N9 T39 PAD
(15) TZOUT0+ F30 LB_DATA0 EXP_RXN9 T38
TZOUT1+ PCIE_GTX_C_MRX_N10 T40 PAD

LVDS
(15) TZOUT1+ D29 LB_DATA1 EXP_RXN10 V34
TZOUT2+ F28 W38 PCIE_GTX_C_MRX_N11 T41 PAD
(15) TZOUT2+ LB_DATA2 EXP_RXN11
Y34 PCIE_GTX_C_MRX_N12 T42 PAD
TZOUT0- EXP_RXN12 PCIE_GTX_C_MRX_N13 T43 PAD
(15) TZOUT0- G30 LB_DATA#0 EXP_RXN13 AA38
TZOUT1- D30 AB34 PCIE_GTX_C_MRX_N14 T44 PAD
(15) TZOUT1- LB_DATA#1 EXP_RXN14
TZOUT2- F29 AC38 PCIE_GTX_C_MRX_N15 T45 PAD
(15) TZOUT2- LB_DATA#2 EXP_RXN15 T46 PAD
TXCLK+ A32 D34 PCIE_GTX_C_MRX_P0
(15) TXCLK+ LA_CLK EXP_RXP0
TXCLK- A33 F38 PCIE_GTX_C_MRX_P1 T47 PAD
(15) TXCLK- LA_CLK# EXP_RXP1
TZCLK+ E26 G34 PCIE_GTX_C_MRX_P2
(15) TZCLK+ LB_CLK EXP_RXP2
TZCLK- E27 H38 PCIE_GTX_C_MRX_P3 T48 PAD
(15) TZCLK- LB_CLK# EXP_RXP3
J34 PCIE_GTX_C_MRX_P4 T49 PAD

PCI-EXPRESS GRAPHICS
R108 0_0402_5% EXP_RXP4 PCIE_GTX_C_MRX_P5 T50 PAD
D32 LBKLT_CTL EXP_RXP5 L38
C C
(32) ENBKL 1 2 LBKLT_EN LBKLT_EN J30 LBKLT_EN EXP_RXP6 M34 PCIE_GTX_C_MRX_P6 T51 PAD
LCTLA_CLK H30 N38 PCIE_GTX_C_MRX_P7 T52 PAD
LCTLB_DATA LCTLA_CLK EXP_RXP7 PCIE_GTX_C_MRX_P8 T53 PAD
H29 LCTLB_DATA EXP_RXP8 P34
(15) I2CC_SCL I2CC_SCL G26 R38 PCIE_GTX_C_MRX_P9 T54 PAD
I2CC_SDA LDDC_CLK EXP_RXP9 PCIE_GTX_C_MRX_P10 T55 PAD
(15) I2CC_SDA G25 LDDC_DATA EXP_RXP10 T34
GMCH_ENVDD F32 V38 PCIE_GTX_C_MRX_P11 T56 PAD
(15) GMCH_ENVDD LVDD_EN EXP_RXP11
LIBG B38 W34 PCIE_GTX_C_MRX_P12 T57 PAD
LIBG EXP_RXP12 PCIE_GTX_C_MRX_P13 T58 PAD
C35 LVBG EXP_RXP13 Y38
C33 AA34 PCIE_GTX_C_MRX_P14 T59 PAD
LVREFH EXP_RXP14 PCIE_GTX_C_MRX_P15 T60 PAD
C32 LVREFL EXP_RXP15 AB38
T61 PAD
F36 PCIE_MTX_GRX_N0
GMCH_TV_COMPS EXP_TXN0 PCIE_MTX_GRX_N1
(16) GMCH_TV_COMPS A16 TVDAC_A EXP_TXN1 G40
GMCH_TV_LUMA C18 H36 PCIE_MTX_GRX_N2
(16) GMCH_TV_LUMA TVDAC_B EXP_TXN2
GMCH_TV_CRMA A19 J40 PCIE_MTX_GRX_N3
(16) GMCH_TV_CRMA TVDAC_C EXP_TXN3

TV
L36 PCIE_MTX_GRX_N4
EXP_TXN4
1 2 TV_IREF J20 TV_IREF EXP_TXN5 M40 PCIE_MTX_GRX_N5 T62 PAD
R82 4.99K_0402_1% N36 PCIE_MTX_GRX_N6 T63 PAD
TVOUT@ EXP_TXN6 PCIE_MTX_GRX_N7 T64 PAD
B16 TV_IRTNA EXP_TXN7 P40
B18 R36 PCIE_MTX_GRX_N8 T65 PAD
TV_IRTNB EXP_TXN8 PCIE_MTX_GRX_N9 T66 PAD
B19 TV_IRTNC EXP_TXN9 T40
V36 PCIE_MTX_GRX_N10 T67 PAD
EXP_TXN10 PCIE_MTX_GRX_N11 T68 PAD
J29 TV_DCONSEL1 EXP_TXN11 W40
K30 Y36 PCIE_MTX_GRX_N12 T69 PAD
TV_DCONSEL0 EXP_TXN12 PCIE_MTX_GRX_N13 T70 PAD
EXP_TXN13 AA40
AB36 PCIE_MTX_GRX_N14 T71 PAD
EXP_TXN14 PCIE_MTX_GRX_N15 T72 PAD
EXP_TXN15 AC40
GMCH_CRT_CLK C26 T73 PAD
(16) GMCH_CRT_CLK DDCCLK
CRT

GMCH_CRT_DATA C25 D36 PCIE_MTX_GRX_P0

(16) GMCH_CRT_DATA DDCDATA EXP_TXP0
F40 PCIE_MTX_GRX_P1
EXP_TXP1 PCIE_MTX_GRX_P2
(16) GMCH_CRT_VSYNC H23 VSYNC EXP_TXP2 G36
G23 H40 PCIE_MTX_GRX_P3
B (16) GMCH_CRT_HSYNC HSYNC EXP_TXP3 B
E23 J36 PCIE_MTX_GRX_P4
(16) GMCH_CRT_B BLUE EXP_TXP4
2 1 D23 L40 PCIE_MTX_GRX_P5 T74 PAD
R567 150_0402_1% BLUE# EXP_TXP5 PCIE_MTX_GRX_P6 T75 PAD
(16) GMCH_CRT_G C22 GREEN EXP_TXP6 M36
2 1 B22 N40 PCIE_MTX_GRX_P7 T76 PAD
R565 150_0402_1% GREEN# EXP_TXP7 PCIE_MTX_GRX_P8 T77 PAD
(16) GMCH_CRT_R A21 RED EXP_TXP8 P36
2 1 B21 R40 PCIE_MTX_GRX_P9 T78 PAD
R564 150_0402_1% RED# EXP_TXP9 PCIE_MTX_GRX_P10 T79 PAD
EXP_TXP10 T36
V40 PCIE_MTX_GRX_P11 T80 PAD
EXP_TXP11
1 2 CRT_IREF J22 CRT_IREF EXP_TXP12 W36 PCIE_MTX_GRX_P12 T81 PAD
R91 255_0402_1% Y40 PCIE_MTX_GRX_P13 T82 PAD
EXP_TXP13 PCIE_MTX_GRX_P14 T83 PAD
10mils EXP_TXP14 AA36
PCIE_MTX_GRX_P15 T84 PAD
EXP_TXP15 AB40
+3VS T85 PAD

CALISTOGA_FCBGA1466~D
R122 1 2 10K_0402_5% I2CC_SCL

R104 1 2 10K_0402_5% I2CC_SDA

PCIE_GTX_C_MRX_N1 7307@ C696 1 2 0.1U_0402_16V4Z
SDVO_INT# (17)
R125 1 2 10K_0402_5% LCTLB_DATA PCIE_GTX_C_MRX_P1 C695 1 2 0.1U_0402_16V4Z
SDVO_INT (17)
7307@
R117 1 2 10K_0402_5% LCTLA_CLK
PCIE_MTX_GRX_N0 7307@ C216 1 2 0.1U_0402_16V4Z
SDVOB_R# (17)
R107 1 2 4.7K_0402_5% GMCH_CRT_CLK PCIE_MTX_GRX_P0 C209 1 2 7307@ 0.1U_0402_16V4Z SDVOB_R (17)
R94 1 2 4.7K_0402_5% GMCH_CRT_DATA PCIE_MTX_GRX_N1 C240 1 2 7307@ 0.1U_0402_16V4Z SDVOB_G# (17)
PCIE_MTX_GRX_P1 C239 1 2 7307@ 0.1U_0402_16V4Z SDVOB_G (17)
PCIE_MTX_GRX_N2 C242 1 2 7307@ 0.1U_0402_16V4Z SDVOB_B# (17)
R109 1 2 100K_0402_5% LBKLT_EN PCIE_MTX_GRX_P2 C241 1 2 7307@ 0.1U_0402_16V4Z SDVOB_B (17)
R576 1 2 1.5K_0402_1% LIBG PCIE_MTX_GRX_N3 C235 1 2 7307@ 0.1U_0402_16V4Z
A SDVOB_CLK# (17) A
PCIE_MTX_GRX_P3 C234 1 2 0.1U_0402_16V4Z
SDVOB_CLK (17)
R541 1 2 150_0402_1% GMCH_TV_COMPS 7307@
TVOUT@
R544 1 2 150_0402_1% GMCH_TV_LUMA
TVOUT@
R563 1 2 150_0402_1% GMCH_TV_CRMA
TVOUT@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (3/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 8 of 47
5 4 3 2 1
 5 4 3 2 1

D7 R101
@ RB751V_SOD323 @ 10_0402_5%
+1.05VS 2 1 1 2 +2.5VS

D6 R93
@ RB751V_SOD323 @ 10_0402_5%
+1.5VS 2 1 1 2 +3VS

D +2.5VS D

U40H +1.5VS_DPLLA L46 +1.5VS_DPLLB L45

+1.05VS H22 1 2 MBK1608301YZF_0603 MBK1608301YZF_0603
VCC_SYNC C117 2 1 +1.5VS 2 1 +1.5VS
AC14 (60mA) 0.1U_0402_16V4Z +2.5VS
VTT0

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
(800mA) AB14 B30 +2.5VS
VTT1 VCCTX_LVDS0
W14 VTT2 VCCTX_LVDS1 C30 1 1 1
V14 A30 +1.5VS_PCIE R580
VTT3 VCCTX_LVDS2 1 1

C194

C683

C196
T14 0_0805_5% + C687 + C690
R14
VTT4
VTT5 VCC3G0 AB41 W=60 mils 2 1 +1.5VS 2
P14 AJ41 330U_D2E_2.5VM 330U_D2E_2.5VM
VTT6 VCC3G1 2 2 2 2

10U_0805_10V4Z

10U_0805_10V4Z
N14 L41 (1500mA) 1
VTT7 VCC3G2
M14 VTT8 VCC3G3 N41 1 1
L14 R41 C739 +
VTT9 VCC3G4

C712

C722
AD13 VTT10 VCC3G5 V41 close pin G41
AC13 Y41 220U_D2_2VMR15
VTT11 VCC3G6 2 2 2
AB13 VTT12
1 AA13 VTT13 VCCA_3GPLL AC33 +1.5VS_3GPLL
Y13 VTT14 VCCA_3GBG G41 +2.5VS
C629 + W13 H41 (2mA) +3VS_TVDACB L7 +3VS +3VS_TVDACA L5 +3VS
VTT15 VSSA_3GBG L8 MBK1608301YZF_0603 MBK1608301YZF_0603
V13 VTT16
220U_D2_2VMR15 U13 MBK1608301YZF_0603 2 1 2 1
2 VTT17

0.022U_0402_16V7K

0.022U_0402_16V7K
T13 VTT18 VCCA_CRTDAC0 E21 (70mA) +2.5VS_CRTDAC 2 1 +2.5VS

0.022U_0402_16V7K

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R13 VTT19 VCCA_CRTDAC1 F21 1

0.1U_0402_16V4Z
N13 VTT20 VSSA_CRTDAC2 G21 1 2005/09/21 1 1 1 1
M13 + C49
VTT21 1 1

C105

C92

C84

C85
L13 + C927
VTT22

C118

C106
AB12 VTT23 VCCA_DPLLA B26 (50mA) +1.5VS_DPLLA 220U_D2_4VM
2 2 2 2 2
AA12 VTT24 VCCA_DPLLB C39 (50mA) +1.5VS_DPLLB 220U_D2_4VM
2 2 2
Y12 VTT25 VCCA_HPLL AF1 (45mA) +1.5VS_HPLL
W12 VTT26
C C
V12 VTT27
U12 VTT28 VCCA_LVDS A38 (10mA) +2.5VS
T12 VTT29 VSSA_LVDS B39
R12 VTT30
P12 VTT31
N12 AF2 (45mA)
M12
VTT32
VTT33
P O W E R VCCA_MPLL +1.5VS_MPLL +3VS_TVDACC L4 +3VS
+2.5VS
2.2U_0805_10V6K
4.7U_0805_10V4Z

L12 H20 +3VS_TVBG MBK1608301YZF_0603

VTT34 VCCA_TVBG
R11 VTT35 VSSA_TVBG G20 2 1

0.022U_0402_16V7K
1 1 P11 (120mA)
VTT36

0.01U_0402_16V7K
C627

C67

0.1U_0402_16V4Z

0.1U_0402_16V4Z
N11 VTT37
M11 VTT38 VCCA_TVDACA0 E19 +3VS_TVDACA 1 1
R10 VTT39 VCCA_TVDACA1 F19
2 2

C93

C107
P10 VTT40 VCCA_TVDACB0 C20 +3VS_TVDACB 1 1 CRTDAC: Route caps within

C195

C180
N10 VTT41 VCCA_TVDACB1 D20
M10 E20 +3VS_TVDACC
250mil of Alviso. Route FB 2 2
VTT42 VCCA_TVDACC0
P9 VTT43 VCCA_TVDACC1 F20 within 3" of Calistoga
2 2
N9 VTT44
M9 VTT45
R8 VTT46 VCCD_HMPLL0 AH1 (150mA) +1.5VS
P8 VTT47 VCCD_HMPLL1 AH2
N8 VTT48 close pin A38
M8 VTT49
P7 VTT50 VCCD_LVDS0 A28
N7 B28 (20mA)
VTT51 VCCD_LVDS1
M7 C28
R6
P6
VTT52
VTT53
VCCD_LVDS2
D21 (24mA) +1.5VS_TVDAC
+3VS_TVBG R90
0_0603_5%
+3VS
PCI-E/MEM/PSB PLL decoupling
VTT54 VCCD_TVDAC
M6 VTT55 VCCDQ_TVDAC H19 2 1

0.022U_0402_16V7K
MCH_A6 A6 VTT56 +1.5VS_3GPLL +1.5VS +1.5VS_TVDAC +1.5VS
0.47U_0603_16V4Z

0.1U_0402_16V4Z
R5 A23 +3VS R112 R568
VTT57 VCCHV0 (40mA) 0_0603_5% 0_0603_5%
P5 VTT58 VCCHV1 B23 1 1
0.1U_0402_16V4Z

10U_0805_10V4Z

B B
1 N5 VTT59 VCCHV2 B25 2 1 2 1

0.022U_0402_16V7K
C643

C108

C109

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M5 VTT60 1 1
C111

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
P4 VTT61 VCCAUX0 AK31
2 2
C127

N4 VTT62 VCCAUX1 AF31 1 1 1 1 1 1

2

C141

C140

C119

C672
M4 VTT63 VCCAUX2 AE31
2 2

C94
C139
R3 VTT64 VCCAUX3 AC31
P3 AL30 @ @
VTT65 VCCAUX4 2 2 2 2 2 2
N3 VTT66 VCCAUX5 AK30
M3 VTT67 VCCAUX6 AJ30
+1.5VS
0.22U_0603_16V7K

R2 VTT68 VCCAUX7 AH30

P2 VTT69 VCCAUX8 AG30
1 M2 VTT70 VCCAUX9 AF30
C630

0.1U_0402_16V4Z

MCH_D2 D2 AE30
VTT71 VCCAUX10
0.22U_0603_16V7K

AB1 VTT72 VCCAUX11 AD30 1

R1 AC30
MCH_AB1

2 VTT73 VCCAUX12
C68

1 P1 VTT74 VCCAUX13 AG29

+1.5VS_MPLL +1.5VS_HPLL
C633

N1 AF29 R517 R516

VTT75 VCCAUX14 2 0_0603_5% 0_0603_5%
M1 VTT76 VCCAUX15 AE29
0.47U_0603_16V4Z

2 VCCAUX16 AD29 45mA Max. 2 1 +1.5VS 45mA Max. 2 1 +1.5VS

1 VCCAUX17 AC29

0.1U_0402_16V4Z

0.1U_0402_16V4Z
VCCAUX18 AG28
C632

10U_0805_10V4Z

10U_0805_10V4Z
VCCAUX19 AF28
VCCAUX20 AE28 1 1 1 1
2

C637

C638
VCCAUX21 AH22

C636

C631
VCCAUX22 AJ21
AG14 VCCAUX32 VCCAUX23 AH21
2 2 2 2
AF14 VCCAUX33 VCCAUX24 AJ20
AE14 VCCAUX34 VCCAUX25 AH20
Y14 VCCAUX35 VCCAUX26 AH19
AF13 VCCAUX36 VCCAUX27 P19
AE13 VCCAUX37 VCCAUX28 P16
+1.5VS AF12 AH15
A VCCAUX38 VCCAUX29 A
AE12 VCCAUX39 VCCAUX30 P15
AD12 VCCAUX40 VCCAUX31 AH14

CALISTOGA_FCBGA1466~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (4/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 9 of 47
5 4 3 2 1
 5 4 3 2 1

Strap Pin Table

CFG[3:17] have internal pull up
CFG[19:18] have internal pull down
+1.05VS U40F +1.5VS +1.05VS U40G +1.8V

AD27 VCC_NCTF0 VCCAUX_NCTF0 AG27 AA33 VCC0 VCC_SM0 AU41 011 = 667MT/s FSB
(3500mA) AC27 AF27 W33 AT41 MCH_AT41 CFG[2:0] 001 = 533MT/s FSB
VCC_NCTF1 VCCAUX_NCTF1 VCC1 VCC_SM1 MCH_AM41
AB27 VCC_NCTF2 VCCAUX_NCTF2 AG26 P33 VCC2 VCC_SM2 AM41
AA27 VCC_NCTF3 VCCAUX_NCTF3 AF26 N33 VCC3 VCC_SM3 AU40 0 = DMI x 2

0.47U_0603_16V4Z

0.47U_0603_16V4Z
Y27 VCC_NCTF4 VCCAUX_NCTF4 AG25 L33 VCC4 VCC_SM4 BA34 CFG5 1 = DMI x 4 *(Default)
W27 VCC_NCTF5 VCCAUX_NCTF5 AF25 J33 VCC5 VCC_SM5 AY34
V27 VCC_NCTF6 VCCAUX_NCTF6 AG24 AA32 VCC6 VCC_SM6 AW34 1 1 0 = Reserved

C718

C717
D D
U27 VCC_NCTF7 VCCAUX_NCTF7 AF24 Y32 VCC7 VCC_SM7 AV34 CFG7 1 = Mobile Yonah CPU*(Default)
T27 VCC_NCTF8 VCCAUX_NCTF8 AG23 W32 VCC8 VCC_SM8 AU34
0.22U_0603_16V7K

0.22U_0603_16V7K

0.22U_0603_16V7K

R27 VCC_NCTF9 VCCAUX_NCTF9 AF23 V32 VCC9 VCC_SM9 AT34

2 2 0 = Lane Reversal Enable
AD26 VCC_NCTF10 VCCAUX_NCTF10 AG22 P32 VCC10 VCC_SM10 AR34 CFG9 1 = Normal Operation*(Default)
1 1 1 AC26 VCC_NCTF11 VCCAUX_NCTF11 AF22 N32 VCC11 VCC_SM11 BA30
C639

C42

C640

AB26 VCC_NCTF12 VCCAUX_NCTF12 AG21 M32 VCC12 VCC_SM12 AY30

AA26 VCC_NCTF13 VCCAUX_NCTF13 AF21 L32 VCC13 VCC_SM13 AW30 CFG11 0 = Reserved
Y26 VCC_NCTF14 VCCAUX_NCTF14 AG20 J32 VCC14 VCC_SM14 AV30
2 2 2
W26 VCC_NCTF15 VCCAUX_NCTF15 AF20 AA31 VCC15 VCC_SM15 AU30 PSB 4X CLK Enable 1 = Calistoga *
V26 VCC_NCTF16 VCCAUX_NCTF16 AG19 W31 VCC16 VCC_SM16 AT30
U26 VCC_NCTF17 VCCAUX_NCTF17 AF19 V31 VCC17 VCC_SM17 AR30 Place near pin AT41 & AM41
T26 VCC_NCTF18 VCCAUX_NCTF18 R19 T31 VCC18 VCC_SM18 AP30 00 = Reserved
R26 VCC_NCTF19 VCCAUX_NCTF19 AG18 R31 VCC19 VCC_SM19 AN30 CFG[13:12] 01 = XOR Mode Enabled
AD25 VCC_NCTF20 VCCAUX_NCTF20 AF18 P31 VCC20 VCC_SM20 AM30 10 = All Z Mode Enabled
AC25 VCC_NCTF21 VCCAUX_NCTF21 R18 N31 VCC21 VCC_SM21 AM29 11 = Normal Operation *(Default)
AB25 VCC_NCTF22 VCCAUX_NCTF22 AG17 M31 VCC22 VCC_SM22 AL29
AA25 VCC_NCTF23 VCCAUX_NCTF23 AF17 AA30 VCC23 VCC_SM23 AK29 0 = Dynamic ODT Disabled
Y25 VCC_NCTF24 VCCAUX_NCTF24 AE17 Y30 VCC24 VCC_SM24 AJ29 CFG16 1 = Dynamic ODT Enabled *(Default)
W25 VCC_NCTF25 VCCAUX_NCTF25 AD17 W30 VCC25 VCC_SM25 AH29
V25 VCC_NCTF26 VCCAUX_NCTF26 AB17 V30 VCC26 VCC_SM26 AJ28 0 = 1.05V *(Default)

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
U25 VCC_NCTF27 VCCAUX_NCTF27 AA17 U30 VCC27 VCC_SM27 AH28 CFG18 1 = 1.5V
1U_0603_10V4Z

T25 W17 T30 AJ27

P O W E R
VCC_NCTF28 VCCAUX_NCTF28 VCC28 VCC_SM28 1 1 1 1
10U_0805_10V4Z

10U_0805_10V4Z

R25 VCC_NCTF29 VCCAUX_NCTF29 V17 R30 VCC29 VCC_SM29 AH27 0 = Normal Operation * (Default)

C75

C86
C121

C129
1 1 1 AD24 VCC_NCTF30 VCCAUX_NCTF30 T17 P30 VCC30 VCC_SM30 BA26 CFG19 1 = DMI Lane Reversal Enable
AC24 VCC_NCTF31 VCCAUX_NCTF31 R17 N30 VCC31 VCC_SM31 AY26
2 2 2 2
C45

C44

C43

AB24 VCC_NCTF32 VCCAUX_NCTF32 AG16 M30 VCC32 P O W E R VCC_SM32 AW26 0 = No SDVO Device Present *
2 2 2
AA24 VCC_NCTF33 VCCAUX_NCTF33 AF16 L30 VCC33 VCC_SM33 AV26 (Default)
Y24 VCC_NCTF34 VCCAUX_NCTF34 AE16 AA29 VCC34 VCC_SM34 AU26 SDVO_CTRLDATA
W24 VCC_NCTF35 VCCAUX_NCTF35 AD16 Y29 VCC35 VCC_SM35 AT26 1 = SDVO Device Present
V24 VCC_NCTF36 VCCAUX_NCTF36 AC16 W29 VCC36 VCC_SM36 AR26
U24 VCC_NCTF37 VCCAUX_NCTF37 AB16 V29 VCC37 VCC_SM37 AJ26
C
T24 VCC_NCTF38 VCCAUX_NCTF38 AA16 U29 VCC38 VCC_SM38 AH26 0 = Only PCIE or SDVO is C
R24 VCC_NCTF39 VCCAUX_NCTF39 Y16 R29 VCC39 VCC_SM39 AJ25 CFG20 operational. *(Default)
AD23 VCC_NCTF40 VCCAUX_NCTF40 W16 P29 VCC40 VCC_SM40 AH25
V23 VCC_NCTF41 VCCAUX_NCTF41 V16 M29 VCC41 VCC_SM41 AJ24 (PCIE/SDVO select) 1 = PCIE/SDVO are operating
U23 U16 L29 AH24
T23
VCC_NCTF42 VCCAUX_NCTF42
T16 AB28
VCC42 VCC_SM42
BA23 simu.
VCC_NCTF43 VCCAUX_NCTF43 VCC43 VCC_SM43
R23 VCC_NCTF44 VCCAUX_NCTF44 R16 AA28 VCC44 VCC_SM44 AJ23

0.47U_0603_16V4Z
1 AD22 VCC_NCTF45 VCCAUX_NCTF45 AG15 Y28 VCC45 VCC_SM45 BA22
V22 VCC_NCTF46 VCCAUX_NCTF46 AF15 V28 VCC46 VCC_SM46 AY22
C41 + U22 AE15 U28 AW22
VCC_NCTF47 VCCAUX_NCTF47 VCC47 VCC_SM47 1

C679
T22 VCC_NCTF48 VCCAUX_NCTF48 AD15 T28 VCC48 VCC_SM48 AV22
220U_D2_2VMR15 R22 AC15 R28 AU22
2 VCC_NCTF49 VCCAUX_NCTF49 VCC49 VCC_SM49
AD21 VCC_NCTF50 VCCAUX_NCTF50 AB15 P28 VCC50 VCC_SM50 AT22
2 R58
V21 VCC_NCTF51 VCCAUX_NCTF51 AA15 N28 VCC51 VCC_SM51 AR22 (6) CFG5 1 2 @ 2.2K_0402_5%
U21 VCC_NCTF52 VCCAUX_NCTF52 Y15 M28 VCC52 VCC_SM52 AP22
T21 W15 L28 AK22 R81 1 2 @ 2.2K_0402_5%
VCC_NCTF53 VCCAUX_NCTF53 VCC53 VCC_SM53 (6) CFG7
R21 VCC_NCTF54 VCCAUX_NCTF54 V15 P27 VCC54 VCC_SM54 AJ22
AD20 U15 N27 AK21 R67 1 2 @ 2.2K_0402_5%
VCC_NCTF55 VCCAUX_NCTF55 VCC55 VCC_SM55 (6) CFG9
V20 VCC_NCTF56 VCCAUX_NCTF56 T15 M27 VCC56 VCC_SM56 AK20 Place near pin BA23
U20 R15 L27 BA19 R57 1 2 @ 2.2K_0402_5%
VCC_NCTF57 VCCAUX_NCTF57 VCC57 VCC_SM57 (6) CFG11
T20 VCC_NCTF58 P26 VCC58 VCC_SM58 AY19
R20 N26 AW19 R59 1 2 @ 2.2K_0402_5%
VCC_NCTF59 VCC59 VCC_SM59 (6) CFG12

10U_0805_10V4Z

10U_0805_10V4Z
AD19 VCC_NCTF60 VSS_NCTF0 AE27 L26 VCC60 VCC_SM60 AV19 1
1 V19 AE26 N25 AU19 1 1 R69 1 2 @ 2.2K_0402_5%
VCC_NCTF61 VSS_NCTF1 VCC61 VCC_SM61 + C735 (6) CFG13
U19 VCC_NCTF62 VSS_NCTF2 AE25 M25 VCC62 VCC_SM62 AT19

C720

C719
C40 + T19 AE24 L25 AR19 R68 1 2 @ 2.2K_0402_5%
VCC_NCTF63 VSS_NCTF3 VCC63 VCC_SM63 (6) CFG16
@ AD18 AE23 P24 AP19 220U_D2_4VM
220U_D2_2VMR15 VCC_NCTF64 VSS_NCTF4 VCC64 VCC_SM64 2 2 2
AC18 VCC_NCTF65 VSS_NCTF5 AE22 N24 VCC65 VCC_SM65 AK19
2
AB18 VCC_NCTF66 VSS_NCTF6 AE21 M24 VCC66 VCC_SM66 AJ19
AA18 VCC_NCTF67 VSS_NCTF7 AE20 AB23 VCC67 VCC_SM67 AJ18
Y18 VCC_NCTF68 VSS_NCTF8 AE19 AA23 VCC68 VCC_SM68 AJ17
W18 VCC_NCTF69 VSS_NCTF9 AE18 Y23 VCC69 VCC_SM69 AH17
V18 VCC_NCTF70 VSS_NCTF10 AC17 P23 VCC70 VCC_SM70 AJ16
B
U18 Y17 N23 AH16 +3VS B
VCC_NCTF71 VSS_NCTF11 VCC71 VCC_SM71
T18 VCC_NCTF72 VSS_NCTF12 U17 M23 VCC72 VCC_SM72 BA15
+1.05VS L23 AY15 R92 1 2 @ 1K_0402_5%
VCC73 VCC_SM73 (6) CFG18

0.47U_0603_16V4Z
AC22 VCC74 VCC_SM74 AW15
+1.8V R95
M19 VCC100 AB22 VCC75 VCC_SM75 AV15 (6) CFG19 1 2 @ 1K_0402_5%
L19 VCC101 VCC_SM100 AR6 Y22 VCC76 VCC_SM76 AU15 1

C650
N18 AP6 W22 AT15 R118 1 2 @ 1K_0402_5%
VCC102 VCC_SM101 VCC77 VCC_SM77 (6) CFG20
M18 VCC103 VCC_SM102 AN6 P22 VCC78 VCC_SM78 AR15
L18 VCC104 VCC_SM103 AL6 N22 VCC79 VCC_SM79 AJ15
2
P17 VCC105 VCC_SM104 AK6 M22 VCC80 VCC_SM80 AJ14
N17 VCC106 VCC_SM105 AJ6 L22 VCC81 VCC_SM81 AJ13
M17 VCC107 VCC_SM106 AV1 MCH_AV1 AC21 VCC82 VCC_SM82 AH13
N16 VCC108 VCC_SM107 AJ1 MCH_AJ1 AA21 VCC83 VCC_SM83 AK12
M16 VCC109 W21 VCC84 VCC_SM84 AJ12
0.47U_0603_16V4Z

0.47U_0603_16V4Z

L16 VCC110 N21 VCC85 VCC_SM85 AH12

M21 VCC86 VCC_SM86 AG12 Place near pin BA15
1 1 L21 VCC87 VCC_SM87 AK11
C635

C634

CALISTOGA_FCBGA1466~D AC20 BA8

VCC88 VCC_SM88
AB20 VCC89 VCC_SM89 AY8
Y20 VCC90 VCC_SM90 AW8
2 2
W20 VCC91 VCC_SM91 AV8
P20 VCC92 VCC_SM92 AT8
N20 VCC93 VCC_SM93 AR8
M20 VCC94 VCC_SM94 AP8
L20 VCC95 VCC_SM95 BA6
AB19 VCC96 VCC_SM96 AY6
Place near pin AV1 & AJ1 AA19 VCC97 VCC_SM97 AW6
Y19 VCC98 VCC_SM98 AV6
N19 VCC99 VCC_SM99 AT6

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (5/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

U40I U40J
AC41 VSS0 VSS100 AE34 AN21 VSS200 VSS280 AG10
AA41 VSS1 VSS101 AC34 AL21 VSS201 VSS281 AC10
W41 VSS2 VSS102 C34 AB21 VSS202 VSS282 W10
T41 VSS3 VSS103 AW33 Y21 VSS203 VSS283 U10
P41 VSS4 VSS104 AV33 P21 VSS204 VSS284 BA9
M41 VSS5 VSS105 AR33 K21 VSS205 VSS285 AW9
D D
J41 VSS6 VSS106 AE33 J21 VSS206 VSS286 AR9
F41 VSS7 VSS107 AB33 H21 VSS207 VSS287 AH9
AV40 VSS8 VSS108 Y33 C21 VSS208 VSS288 AB9
AP40 VSS9 VSS109 V33 AW20 VSS209 VSS289 Y9
AN40 VSS10 VSS110 T33 AR20 VSS210 VSS290 R9
AK40 VSS11 VSS111 R33 AM20 VSS211 VSS292 G9
AJ40 VSS12 VSS112 M33 AA20 VSS212 VSS291 E9
AH40 VSS13 VSS113 H33 K20 VSS213 VSS293 A9
AG40 VSS14 VSS114 G33 B20 VSS214 VSS294 AG8
AF40 VSS15 VSS115 F33 A20 VSS215 VSS295 AD8
AE40 VSS16 VSS116 D33 AN19 VSS216 VSS296 AA8
B40 VSS17 VSS117 B33 AC19 VSS217 VSS297 U8
AY39 VSS18 VSS118 AH32 W19 VSS218 VSS298 K8
AW39 VSS19 VSS119 AG32 K19 VSS219 VSS299 C8
AV39 VSS20 VSS120 AF32 G19 VSS220 VSS300 BA7
AR39 VSS21 VSS121 AE32 C19 VSS221 VSS301 AV7
AN39 VSS22 VSS122 AC32 AH18 VSS222 VSS302 AP7
AJ39 VSS23 VSS123 AB32 P18 VSS223 VSS303 AL7
AC39 VSS24 VSS124 G32 H18 VSS224 VSS304 AJ7
AB39 VSS25 VSS125 B32 D18 VSS225 VSS305 AH7
AA39 VSS26 VSS126 AY31 A18 VSS226 VSS306 AF7
Y39 VSS27 VSS127 AV31 AY17 VSS227 VSS307 AC7
W39 VSS28 VSS128 AN31 AR17 VSS228 VSS308 R7
V39 AJ31 AP17 G7
T39
VSS29
VSS30
VSS129
VSS130 AG31 AM17
VSS229
VSS230
P O W E R VSS309
VSS310 D7
R39 VSS31 VSS131 AB31 AK17 VSS231 VSS311 AG6
P39 VSS32 VSS132 Y31 AV16 VSS232 VSS312 AD6
N39 VSS33 VSS133 AB30 AN16 VSS233 VSS313 AB6
M39 E30 AL16 Y6
L39
VSS34
VSS35
P O W E R VSS134
VSS135 AT29 J16
VSS234
VSS235
VSS314
VSS315 U6
J39 VSS36 VSS136 AN29 F16 VSS236 VSS316 N6
H39 VSS37 VSS137 AB29 C16 VSS237 VSS317 K6
C C
G39 VSS38 VSS138 T29 AN15 VSS238 VSS318 H6
F39 VSS39 VSS139 N29 AM15 VSS239 VSS319 B6
D39 VSS40 VSS140 K29 AK15 VSS240 VSS320 AV5
AT38 VSS41 VSS141 G29 N15 VSS241 VSS321 AF5
AM38 VSS42 VSS142 E29 M15 VSS242 VSS322 AD5
AH38 VSS43 VSS143 C29 L15 VSS243 VSS323 AY4
AG38 VSS44 VSS144 B29 B15 VSS244 VSS324 AR4
AF38 VSS45 VSS145 A29 A15 VSS245 VSS325 AP4
AE38 VSS46 VSS146 BA28 BA14 VSS246 VSS326 AL4
C38 VSS47 VSS147 AW28 AT14 VSS247 VSS327 AJ4
AK37 VSS48 VSS148 AU28 AK14 VSS248 VSS328 Y4
AH37 VSS49 VSS149 AP28 AD14 VSS249 VSS329 U4
AB37 VSS50 VSS150 AM28 AA14 VSS250 VSS330 R4
AA37 VSS51 VSS151 AD28 U14 VSS251 VSS331 J4
Y37 VSS52 VSS152 AC28 K14 VSS252 VSS332 F4
W37 VSS53 VSS153 W28 H14 VSS253 VSS333 C4
V37 VSS54 VSS154 J28 E14 VSS254 VSS334 AY3
T37 VSS55 VSS155 E28 AV13 VSS255 VSS335 AW3
R37 VSS56 VSS156 AP27 AR13 VSS256 VSS336 AV3
P37 VSS57 VSS157 AM27 AN13 VSS257 VSS337 AL3
N37 VSS58 VSS158 AK27 AM13 VSS258 VSS338 AH3
M37 VSS59 VSS159 J27 AL13 VSS259 VSS339 AG3
L37 VSS60 VSS160 G27 AG13 VSS260 VSS340 AF3
J37 VSS61 VSS161 F27 P13 VSS261 VSS341 AD3
H37 VSS62 VSS162 C27 F13 VSS262 VSS342 AC3
G37 VSS63 VSS163 B27 D13 VSS265 VSS343 AA3
F37 VSS64 VSS164 AN26 B13 VSS264 VSS344 G3
D37 VSS65 VSS165 M26 AY12 VSS263 VSS345 AT2
AY36 VSS66 VSS166 K26 AC12 VSS266 VSS346 AR2
AW36 VSS67 VSS167 F26 K12 VSS267 VSS347 AP2
AN36 VSS68 VSS168 D26 H12 VSS268 VSS348 AK2
AH36 VSS69 VSS169 AK25 E12 VSS269 VSS349 AJ2
B B
AG36 VSS70 VSS170 P25 AD11 VSS270 VSS350 AD2
AF36 VSS71 VSS171 K25 AA11 VSS271 VSS351 AB2
AE36 VSS72 VSS172 H25 Y11 VSS272 VSS352 Y2
AC36 VSS73 VSS173 E25 J11 VSS273 VSS353 U2
C36 VSS74 VSS174 D25 D11 VSS274 VSS354 T2
B36 VSS75 VSS175 A25 B11 VSS275 VSS355 N2
BA35 VSS76 VSS176 BA24 AV10 VSS276 VSS356 J2
AV35 VSS77 VSS177 AU24 AP10 VSS277 VSS357 H2
AR35 VSS78 VSS178 AL24 AL10 VSS278 VSS358 F2
AH35 VSS79 VSS179 AW23 AJ10 VSS279 VSS359 C2
AB35 VSS80 VSS180 AT23 VSS360 AL1
AA35 VSS81 VSS181 AN23
Y35 AM23 CALISTOGA_FCBGA1466~D
VSS82 VSS182
W35 VSS83 VSS183 AH23
V35 VSS84 VSS184 AC23
T35 VSS85 VSS185 W23
R35 VSS86 VSS186 K23
P35 VSS87 VSS187 J23
N35 VSS88 VSS188 F23
M35 VSS89 VSS189 C23
L35 VSS90 VSS190 AA22
J35 VSS91 VSS191 K22
H35 VSS92 VSS192 G22
G35 VSS93 VSS193 F22
F35 VSS94 VSS194 E22
D35 VSS95 VSS195 D22
AN34 VSS96 VSS196 A22
AK34 VSS97 VSS197 BA21
AG34 VSS98 VSS198 AV21
AF34 VSS99 VSS199 AR21

CALISTOGA_FCBGA1466~D
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Calistoga (6/6)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

+1.8V +1.8V

JP22 *** +1.8V

+DIMM_VREF 1 VREF VSS 2
3 4 DDRA_SDQ6
VSS DQ4

1
DDRA_SDQ4 5 6 DDRA_SDQ0
DDRA_SDQ1 DQ0 DQ5 R153
7 DQ1 VSS 8
9 10 DDRA_SDM0
DDRA_SDQS0# VSS DM0 1K_0402_1%
(7) DDRA_SDQS0# 11 DQS0# VSS 12
DDRA_SDQS0 13 14 DDRA_SDQ5 20mils

2
(7) DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7
15 VSS DQ7 16 +DIMM_VREF
DDRA_SDQ2 17 18
DQ2 VSS

1
DDRA_SDQ3 19 20 DDRA_SDQ13 1 1
DQ3 DQ12 DDRA_SDQ12 C281 C294 R156
21 VSS DQ13 22
DDRA_SDQ8 23 24
D DDRA_SDQ14 DQ8 VSS DDRA_SDM1 0.1U_0402_16V4Z 2.2U_0805_10V6K 1K_0402_1% D
25 DQ9 DM1 26
2 2
27 28

2
DDRA_SDQS1# VSS VSS
(7) DDRA_SDQS1# 29 DQS1# CK0 30 DDRA_CLK0 (6)
DDRA_SDQS1 31 32
(7) DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# (6)
33 VSS VSS 34
DDRA_SDQ9 35 36 DDRA_SDQ11
DDRA_SDQ15 DQ10 DQ14 DDRA_SDQ10
37 DQ11 DQ15 38
39 VSS VSS 40
DDRA_SMA[0..13]
(7) DDRA_SMA[0..13]
41 VSS VSS 42
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SDQ[0..63]
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 (7) DDRA_SDQ[0..63]
45 DQ17 DQ21 46
47 48 0_0402_5% DDRA_SDM[0..7]
VSS VSS (7) DDRA_SDM[0..7]
DDRA_SDQS2# 49 50 R119 1 2
(7) DDRA_SDQS2# DQS2# NC PM_EXTTS#0 (6,13) +1.8V
DDRA_SDQS2 51 52 DDRA_SDM2
(7) DDRA_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRA_SDQ18 55 56 DDRA_SDQ23
DDRA_SDQ19 DQ18 DQ22 DDRA_SDQ22
57 DQ19 DQ23 58
59 VSS VSS 60 1 1 1 1 1
DDRA_SDQ29 61 62 DDRA_SDQ28 C71 C53 C123 C125 C54
DDRA_SDQ24 DQ24 DQ28 DDRA_SDQ25
63 DQ25 DQ29 64
65 66 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
DDRA_SDM3 VSS VSS DDRA_SDQS3# 2 2 2 2 2
67 DM3 DQS3# 68 DDRA_SDQS3# (7)
69 70 DDRA_SDQS3
NC DQS3 DDRA_SDQS3 (7)
71 VSS VSS 72
DDRA_SDQ26 73 74 DDRA_SDQ31
DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ30
75 DQ27 DQ31 76
77 78 +1.8V
DDRA_CKE0 VSS VSS DDRA_CKE1 +0.9VS
(6) DDRA_CKE0 79 CKE0 NC/CKE1 80 DDRA_CKE1 (6)
81 VDD VDD 82
83 84 DDRA_CKE0 1 4
C DDRA_SBS2# NC NC/A15 DDRA_SBS2# C
(7) DDRA_SBS2# 85 BA2 NC/A14 86 2 3 1 1 1 1
87 88 RP41 56_0404_4P2R_5% C115 C113 C62 C63
DDRA_SMA12 VDD VDD DDRA_SMA11
89 A12 A11 90
DDRA_SMA9 91 92 DDRA_SMA7 DDRA_SMA12 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SMA8 A9 A7 DDRA_SMA6 DDRA_SMA9 2 2 2 2
93 A8 A6 94 2 3
95 96 RP39 56_0404_4P2R_5%
DDRA_SMA5 VDD VDD DDRA_SMA4
97 A5 A4 98
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_SMA8 1 4
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SMA5
101 A1 A0 102 2 3
103 104 RP37 56_0404_4P2R_5%
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 A10/AP BA1 106 DDRA_SBS1# (7)
DDRA_SBS0# 107 108 DDRA_SRAS# DDRA_SMA3 1 4
(7) DDRA_SBS0# BA0 RAS# DDRA_SRAS# (7) +0.9VS
DDRA_SWE# 109 110 DDRA_SCS#0 DDRA_SMA1 2 3
(7) DDRA_SWE# WE# S0# DDRA_SCS#0 (6)
111 112 RP35 56_0404_4P2R_5%
DDRA_SCAS# VDD VDD DDRA_ODT0
(7) DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 (6)
DDRA_SCS#1 115 116 DDRA_SMA13 DDRA_SMA10 1 4
(6) DDRA_SCS#1 NC/S1# NC/A13
117 118 DDRA_SBS0# 2 3 1 1 1 1 1
DDRA_ODT1 VDD VDD RP33 56_0404_4P2R_5% C645 C648 C653 C660 C667
(6) DDRA_ODT1 119 NC/ODT1 NC 120
121 VSS VSS 122
DDRA_SDQ37 123 124 DDRA_SDQ39 DDRA_SWE# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRA_SDQ36 DQ32 DQ36 DDRA_SDQ38 DDRA_SCAS# 2 2 2 2 2
125 DQ33 DQ37 126 2 3
127 128 RP31 56_0404_4P2R_5%
DDRA_SDQS4# VSS VSS DDRA_SDM4
(7) DDRA_SDQS4# 129 DQS4# DM4 130
DDRA_SDQS4 131 132 DDRA_SCS#1 1 4
(7) DDRA_SDQS4 DQS4 VSS DDRA_SDQ34 DDRA_ODT1
133 VSS DQ38 134 2 3
DDRA_SDQ35 135 136 DDRA_SDQ33 RP29 56_0404_4P2R_5% +0.9VS
DDRA_SDQ32 DQ34 DQ39
137 DQ35 VSS 138
139 140 DDRA_SDQ45
DDRA_SDQ40 VSS DQ44 DDRA_SDQ43
141 DQ40 DQ45 142
DDRA_SDQ44 143 144 DDRA_CKE1 1 4 1 1 1 1 1
DQ41 VSS DDRA_SDQS5# DDRA_SMA11 C671 C678 C104 C69 C76
145 VSS DQS5# 146 DDRA_SDQS5# (7) 2 3
DDRA_SDM5 147 148 DDRA_SDQS5 RP12 56_0404_4P2R_5%
B DM5 DQS5 DDRA_SDQS5 (7) 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
149 VSS VSS 150
DDRA_SDQ41 DDRA_SDQ47 DDRA_SMA7 2 2 2 2 2
151 DQ42 DQ46 152 1 4
DDRA_SDQ46 153 154 DDRA_SDQ42 DDRA_SMA6 2 3
DQ43 DQ47 RP10 56_0404_4P2R_5%
155 VSS VSS 156
DDRA_SDQ49 157 158 DDRA_SDQ52
DDRA_SDQ48 DQ48 DQ52 DDRA_SDQ53 DDRA_SMA4
159 DQ49 DQ53 160 1 4
161 162 DDRA_SMA2 2 3 +0.9VS
VSS VSS RP8 56_0404_4P2R_5%
163 NC,TEST CK1 164 DDRA_CLK1 (6)
165 VSS CK1# 166 DDRA_CLK1# (6)
DDRA_SDQS6# 167 168 DDRA_SMA0 1 4
(7) DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6 DDRA_SBS1#
(7) DDRA_SDQS6 169 DQS6 DM6 170 2 3 1 1 1
171 172 RP6 56_0404_4P2R_5% C80 C88 C95
DDRA_SDQ54 VSS VSS DDRA_SDQ51
173 DQ50 DQ54 174
DDRA_SDQ50 175 176 DDRA_SDQ55 DDRA_SRAS# 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DQ51 DQ55 DDRA_SCS#0 2 2 2
177 VSS VSS 178 2 3
DDRA_SDQ60 179 180 DDRA_SDQ57 RP4 56_0404_4P2R_5%
DDRA_SDQ61 DQ56 DQ60 DDRA_SDQ56
181 DQ57 DQ61 182
183 184 DDRA_ODT0 1 4
DDRA_SDM7 VSS VSS DDRA_SDQS7# DDRA_SMA13
185 DM7 DQS7# 186 DDRA_SDQS7# (7) 2 3
187 188 DDRA_SDQS7 RP2 56_0404_4P2R_5%
DDRA_SDQ59 VSS DQS7 DDRA_SDQS7 (7)
189 DQ58 VSS 190
DDRA_SDQ58 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
D_CK_SDATA 195 196
(13,14) D_CK_SDATA SDA VSS
D_CK_SCLK 197 198 R23 1 2 10K_0402_5%
(13,14) D_CK_SCLK SCL SAO
+3VS 199 200 R21 1 2 10K_0402_5%
VDDSPD SA1
203 GND1 GND2 204

P-TWO_A5692A-A0G16-N

A
DIMM0 STD H:9.2mm (BOT) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 12 of 47
5 4 3 2 1
 A B C D E

+1.8V +1.8V

JP21 ***
1 2 +DIMM_VREF +1.8V
+DIMM_VREF VREF VSS
3 4 DDRB_SDQ5
DDRB_SDQ0 VSS DQ4 DDRB_SDQ4
5 DQ0 DQ5 6
DDRB_SDQ1 7 8 1 1
DQ1 VSS DDRB_SDM0
9 VSS DM0 10 1 1 1 1 1 1
DDRB_SDQS0# 11 12 C263 C276 C39 + C290 + C78 C89 C79 C90
(7) DDRB_SDQS0# DDRB_SDQS0 DQS0# VSS DDRB_SDQ6
(7) DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7 2.2U_0805_10V6K @ 150U_D2_6.3VM 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SDQ2 VSS DQ7 2 2
0.1U_0402_16V4Z 2 2
150U_D2_6.3VM 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
1 DDRB_SDQ9 DQ8 VSS DDRB_SDM1 1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
(7) DDRB_SDQS1# DQS1# CK0 DDRB_CLK1 (6)
DDRB_SDQS1 31 32
(7) DDRB_SDQS1 DQS1 CK0# DDRB_CLK1# (6)
33 VSS VSS 34
DDRB_SDQ10 35 36 DDRB_SDQ14
DDRB_SDQ11 DQ10 DQ14 DDRB_SDQ15
37 DQ11 DQ15 38
39 VSS VSS 40

41 VSS VSS 42
DDRB_SDQ17 43 44 DDRB_SDQ21 DDRB_SMA[0..13]
DQ16 DQ20 (7) DDRB_SMA[0..13]
DDRB_SDQ20 45 46 DDRB_SDQ16
DQ17 DQ21 0_0402_5% DDRB_SDQ[0..63]
47 VSS VSS 48 (7) DDRB_SDQ[0..63]
DDRB_SDQS2# 49 50 R120 1 2
(7) DDRB_SDQS2# DQS2# NC PM_EXTTS#0 (6,12) DDRB_SDM[0..7]
DDRB_SDQS2 51 52 DDRB_SDM2 (7) DDRB_SDM[0..7]
(7) DDRB_SDQS2 DQS2 DM2
53 VSS VSS 54
DDRB_SDQ18 55 56 DDRB_SDQ22 +1.8V
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 VSS VSS 60
DDRB_SDQ28 61 62 DDRB_SDQ26
DDRB_SDQ25 DQ24 DQ28 DDRB_SDQ24
63 DQ25 DQ29 64 1 1 1 1 1
65 66 C50 C55 C124 C126 C70
DDRB_SDM3 VSS VSS DDRB_SDQS3#
67 DM3 DQS3# 68 DDRB_SDQS3# (7)
69 70 DDRB_SDQS3 2.2U_0805_10V6K 2.2U_0805_10V6K 2.2U_0805_10V6K
NC DQS3 DDRB_SDQS3 (7) 2 2
2.2U_0805_10V6K 2 2
2.2U_0805_10V6K 2
71 VSS VSS 72
DDRB_SDQ30 73 74 DDRB_SDQ29
DDRB_SDQ31 DQ26 DQ30 DDRB_SDQ27
75 DQ27 DQ31 76
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1
(6) DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 (6) +0.9VS +1.8V
81 VDD VDD 82
83 NC NC/A15 84
2 DDRB_SBS2# 2
(7) DDRB_SBS2# 85 BA2 NC/A14 86
87 88 DDRB_SBS2# 1 4
DDRB_SMA12 VDD VDD DDRB_SMA11 DDRB_CKE0
89 A12 A11 90 2 3 1 1 1 1
DDRB_SMA9 91 92 DDRB_SMA7 RP13 56_0404_4P2R_5% C64 C61 C114 C116
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 DDRB_SMA9 1 4 0.1U_0402_16V4Z 0.1U_0402_16V4Z
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SMA12 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
97 A5 A4 98 2 3
DDRB_SMA3 99 100 DDRB_SMA2 RP11 56_0404_4P2R_5%
DDRB_SMA1 A3 A2 DDRB_SMA0
101 A1 A0 102
103 104 DDRB_SMA5 1 4
DDRB_SMA10 VDD VDD DDRB_SBS1# DDRB_SMA8
105 A10/AP BA1 106 DDRB_SBS1# (7) 2 3
DDRB_SBS0# 107 108 DDRB_SRAS# RP9 56_0404_4P2R_5%
(7) DDRB_SBS0# BA0 RAS# DDRB_SRAS# (7)
DDRB_SWE# 109 110 DDRB_SCS#0
(7) DDRB_SWE# WE# S0# DDRB_SCS#0 (6)
111 112 DDRB_SMA1 1 4
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_SMA3 +0.9VS
(7) DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 (6) 2 3
DDRB_SCS#1 115 116 DDRB_SMA13 RP7 56_0404_4P2R_5%
(6) DDRB_SCS#1 NC/S1# NC/A13
117 VDD VDD 118
DDRB_ODT1 119 120 DDRB_SBS0# 1 4
(6) DDRB_ODT1 NC/ODT1 NC
121 122 DDRB_SMA10 2 3 1 1 1 1 1
DDRB_SDQ32 VSS VSS DDRB_SDQ36 RP5 56_0404_4P2R_5% C669 C677 C647 C652 C659
123 DQ32 DQ36 124
DDRB_SDQ33 125 126 DDRB_SDQ37
DQ33 DQ37 DDRB_SCAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
127 VSS VSS 128 1 4
DDRB_SDQS4# DDRB_SDM4 DDRB_SWE# 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z
(7) DDRB_SDQS4# 129 DQS4# DM4 130 2 3
DDRB_SDQS4 131 132 RP3 56_0404_4P2R_5%
(7) DDRB_SDQS4 DQS4 VSS DDRB_SDQ39
133 VSS DQ38 134
DDRB_SDQ34 135 136 DDRB_SDQ38 DDRB_ODT1 1 4
DDRB_SDQ35 DQ34 DQ39 DDRB_SCS#1
137 DQ35 VSS 138 2 3
139 140 DDRB_SDQ44 RP1 56_0404_4P2R_5% +0.9VS
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
DQ41 VSS DDRB_SDQS5# DDRB_CKE1
145 VSS DQS5# 146 DDRB_SDQS5# (7) 1 4
DDRB_SDM5 147 148 DDRB_SDQS5 DDRB_SMA11 2 3 1 1 1 1 1
3 DM5 DQS5 DDRB_SDQS5 (7) RP40 56_0404_4P2R_5% C662 C87 C91 C97 C110 3
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47 DDRB_SMA7 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
153 DQ43 DQ47 154 1 4
DDRB_SMA6 2 2
0.1U_0402_16V4Z 2 2
0.1U_0402_16V4Z 2
155 VSS VSS 156 2 3
DDRB_SDQ48 157 158 DDRB_SDQ52 RP38 56_0404_4P2R_5%
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 DQ49 DQ53 160
161 162 DDRB_SMA4 1 4
VSS VSS DDRB_SMA2 +0.9VS
163 NC,TEST CK1 164 DDRB_CLK0 (6) 2 3
165 166 RP36 56_0404_4P2R_5%
VSS CK1# DDRB_CLK0# (6)
DDRB_SDQS6# 167 168
(7) DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6 DDRB_SMA0
(7) DDRB_SDQS6 169 DQS6 DM6 170 1 4
171 172 DDRB_SBS1# 2 3 1 1 1
DDRB_SDQ51 VSS VSS DDRB_SDQ54 RP34 56_0404_4P2R_5% C65 C73 C77
173 DQ50 DQ54 174
DDRB_SDQ50 175 176 DDRB_SDQ55
DQ51 DQ55 DDRB_SRAS# 0.1U_0402_16V4Z 0.1U_0402_16V4Z
177 VSS VSS 178 1 4
DDRB_SDQ56 DDRB_SDQ60 DDRB_SCS#0 2 2
0.1U_0402_16V4Z 2
179 DQ56 DQ60 180 2 3
DDRB_SDQ61 181 182 DDRB_SDQ57 RP32 56_0404_4P2R_5%
DQ57 DQ61
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7# DDRB_ODT0 1 4
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# (7) DDRB_SMA13
187 VSS DQS7 188 DDRB_SDQS7 (7) 2 3
DDRB_SDQ59 189 190 RP30 56_0404_4P2R_5%
DDRB_SDQ58 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
D_CK_SDATA VSS DQ63
(12,14) D_CK_SDATA 195 SDA VSS 196
D_CK_SCLK 197 198 1 2
(12,14) D_CK_SCLK SCL SAO
+3VS 199 200 R24 1 2 10K_0402_5% +3VS
VDDSPD SA1 R22 10K_0402_5%
203 GND1 GND2 204

P-TWO_A5652C-A0G16

4
DIMM1 STD H:5.2mm (BOT) 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRII-SODIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 13 of 47
A B C D E
 A B C D E F G H

+CLK_VDDREF
L58
40mil
+CLK_VDD1
Clock Generator
FSLC FSLB FSLA CPU SRC PCI +CLK_VDD48 1 +3VS 1 2
CLKSEL2 CLKSEL1 CLKSEL0 C474
MHz MHz MHz 1
C432
1
C444
1 1 1 1 1
0.047U_0402_16V7K KC FBM-L11-201209-221LMAT_0805 C452 C477 C443 C469 C475
10U_0805_10V4Z 0.047U_0402_16V7K 2 10U_0805_10V4Z 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K 0.047U_0402_16V7K
0 0 1 133 100 33.3 2 2 2 2 2 2 2

0 1 1 166 100 33.3

L59 +CLK_VDD2
Table : ICS9LPR325 20mil L60
U19 +CLK_VCCA 1 2 +CLK_VDD1 40mil
1 +CLK_VDD1 1
0 1 1 1 1 2 +3VS
KC FBM-L11-201209-221LMAT_0805
**SEL_PCI5/REF1 CLKREQ3# 33.3MHz PCICLK5 1 7 C483 C476 1 1 1 KC FBM-L11-201209-221LMAT_0805
VDDSRC VDDA 10U_0805_10V4Z 0.047U_0402_16V7K C457 C460 C440
49 VDDSRC 2 2
**SEL_PCI6/PCICLK1 CLKREQ5# 33.3MHz PCICLK6 54 VDDSRC GNDA 8
65 0.047U_0402_16V7K 0.047U_0402_16V7K 10U_0805_10V4Z
+CLK_VDD2 VDDSRC 2 2 2
**SEL_24M/PCICLK2 TESTMODE 24MHz Output
25 PM_STP_PCI#
PCI_SRC_STOP# PM_STP_PCI# (20)
**SEL_48M/PCICLK3 CLKREQ7# 48MHz_1 Output 30 VDDPCI
36 24 PM_STP_CPU#
VDDPCI CPU_STOP# PM_STP_CPU# (20)
ITP_EN/PCICLK_F0 SRC pair CPU_ITP pair
+CLK_VDD1 12 VDDCPU
11 CLK_CPU1 R373 1 2 0_0402_5% CLK_MCH_BCLK
CPUCLKT1LP CLK_MCH_BCLK (6)
**SEL_24M/PCICLK2=0=TESTMODE C466 1 2 +CLK_VDDREF 18
33P_0402_50V8J R376 1_0603_5% VDDREF CLK_CPU1# R372 1
**SEL_PCI6/PCICLK1=0=CLKREQ5# 15mil CPUCLKC1LP 10 2 0_0402_5% CLK_MCH_BCLK#
CLK_MCH_BCLK# (6)
1 2 1 2 +CLK_VDD48 40 VDD48
R316 2.2_0603_5% 15mil

1
14 CLK_CPU0 R375 1 2 0_0402_5% CLK_CPU_BCLK
+3VS CPUCLKT0LP CLK_CPU_BCLK (4)
Y3 CLK_XTALIN 20
C468 X1 CLK_CPU0# R374 1
**SEL_PCI5=1=PCICLK5 CPUCLKC0LP 13 2 0_0402_5% CLK_CPU_BCLK#
CLK_CPU_BCLK# (4)
33P_0402_50V8J 14.31818MHz_20P_1BX14318BE1A

2
1 2 CLK_REF 1 2 CLK_XTALOUT 19
R712 10K_0402_5% X2
CPUCLKT2_ITP/SRCCLKT10LP 6
CLK_ICH_48M R288 1 2 12_0402_5%
(20) CLK_ICH_48M
CLK_SD_48M R307 1 2 12_0402_5% CLKSEL0 41 5 CLK_MCH_BCLK 1 2
(24) CLK_SD_48M USB_48MHz/FSLA CPUCLKC2_ITP/SRCCLKC10LP
1 2 CLK_PCI0 R383 @ 49.9_0402_1%
R619 10K_0402_5% CLKSEL1 45 CLK_MCH_BCLK# 1 2
FSLB/TEST_MODE/24Mhz CLK_SRC9 R371 1 EXPCARD@ CLK_PCIE_CARD
ITP_EN/PCICLK_F0=0=SRC pair SRCCLKT9LP 3 2 0_0402_5% CLK_PCIE_CARD (29)
R382 @ 49.9_0402_1%
CLK_14M_SIO R349 2 1 33_0402_5% CLKSEL2 23 CLK_CPU_BCLK 1 2
(31) CLK_14M_SIO REF0/FSLC/TEST_SEL
2 CLK_SRC9# R370 1 EXPCARD@
2 0_0402_5% CLK_PCIE_CARD# R385 @ 49.9_0402_1%
SRCCLKC9LP CLK_PCIE_CARD# (29)
2005/10/31 CLK_CPU_BCLK# 1 2
CLK_PCI_SIO R326 1 2 33_0402_5% CLK_PCI4 34 72 R384 @ 49.9_0402_1%
2 (31) CLK_PCI_SIO PCICLK4/FCTSEL1 CLKREQ9# EXP_CLKREQ# (29) 2
CLK_PCI_MINI R327 1 2 12_0402_5% R658 1 2 10K_0402_5% +3VS
(28) CLK_PCI_MINI
CLK_PCI_LAN R333 1 4401@ 2 33_0402_5% CLK_PCI3 33 70 CLK_SRC8 R367 1 MINI2@ 2 0_0402_5% CLK_PCIE_MINI2
(26) CLK_PCI_LAN SEL_48M/PCICLK3 SRCCLKT8LP CLK_PCIE_MINI2 (28)
CLK_PCI_PCM R338 1 2 33_0402_5% CLK_PCI2 32 69 CLK_SRC8# R365 1 MINI2@ 2 0_0402_5% CLK_PCIE_MINI2#
(24) CLK_PCI_PCM SEL_24M/PCICLK2 SRCCLKC8LP CLK_PCIE_MINI2# (28)
1 2 CLK_PCI4
R713 CLK_PCI_LPC R345 1 2 33_0402_5% CLK_PCI1 27 71
(32) CLK_PCI_LPC SEL_PCI6/PCICLK1 CLKREQ8# MINI2_CLKREQ# (28)
10K_0402_5% CLK_PCI_TPM R344 1 @ 2 12_0402_5% R659 1 2 10K_0402_5% +3VS
(31) CLK_PCI_TPM
SRCCLKT7LP 66
CLK_ICH_14M R353 1 2 33_0402_5% CLK_REF CLK_PCIE_MINI2
08/29 add (20) CLK_ICH_14M 22 SEL_PCI5/REF1
67
1
R366
2
@ 49.9_0402_1%
SRCCLKC7LP CLK_PCIE_MINI2# 1 2
CLK_DREF_96M R306 1 2 0_0402_5% CLK_DOT 43 38 R364 @ 49.9_0402_1%
(6) CLK_DREF_96M DOTT_96MHz/27MHz_Nonspread
CLKREQ7#/48Mhz_1 CLK_PCIE_ICH 1 2
CLK_DREF_96M# R305 1 2 0_0402_5% CLK_DOT# 44 63 CLK_SRC6 R355 1 2 0_0402_5% CLK_PCIE_SATA R346 @ 49.9_0402_1%
(6) CLK_DREF_96M# DOTC_96MHz/27MHz_spread SRCCLKT6LP CLK_PCIE_SATA (19)
CLK_PCIE_ICH# 1 2
64 CLK_SRC6# R361 1 2 0_0402_5% CLK_PCIE_SATA# R350 @ 49.9_0402_1%
SRCCLKC6LP CLK_PCIE_SATA# (19)
CLK_PCI_ICH R308 1 2 33_0402_5% CLK_PCI0 37 CLK_PCIE_MINI1 1 2
(18) CLK_PCI_ICH ITP_EN/PCICLK_F0
62 R283 @ 49.9_0402_1%
CLKREQ6# SATA_CLKREQ# (20)
R647 1 2 10K_0402_5% +3VS CLK_PCIE_MINI1# 1 2
CLK_ENABLE# 39 60 CLK_SRC5 R347 1 2 0_0402_5% CLK_PCIE_ICH R282 @ 49.9_0402_1%
(47) CLK_ENABLE# VTT_PWRGD#/PD SRCCLKT5LP CLK_PCIE_ICH (20)
CLK_PCIE_SATA 1 2
61 CLK_SRC5# R351 1 2 0_0402_5% CLK_PCIE_ICH# R354 @ 49.9_0402_1%
+3VS SRCCLKC5LP CLK_PCIE_ICH# (20)
R657 1 2 0_0402_5% CLKIREF 9 CLK_PCIE_SATA# 1 2
GND R637 1
15mil CLKREQ5#/PCICLK6 29 2 10K_0402_5% +3VS R360 @ 49.9_0402_1%
CLK_DREF_SSC 1 2
1 2 CLK_ENABLE# 58 CLK_SRC4 R336 1 8789@ 2 0_0402_5% CLK_PCIE_LAN R285 @ 49.9_0402_1%
SRCCLKT4LP CLK_PCIE_LAN (26)
R620 D_CK_SCLK 16 CLK_DREF_SSC# 1 2
(12,13) D_CK_SCLK SMBCLK
10K_0402_5% 59 CLK_SRC4# R340 1 8789@ 2 0_0402_5% CLK_PCIE_LAN# R284 @ 49.9_0402_1%
SRCCLKC4LP CLK_PCIE_LAN# (26)
CLK_DREF_96M 1 2
2005/10/17 57 R640 1 2 @ 10K_0402_5% +3VS R287 @ 49.9_0402_1%
D_CK_SDATA CLKREQ4# CLK_DREF_96M# 1
(12,13) D_CK_SDATA 17 SMBDAT 2
55 CLK_SRC3 R286 @ 49.9_0402_1%
3 SRCCLKT3LP CLK_PCIE_CARD 1 3
2
4 56 CLK_SRC3# R381 @ 49.9_0402_1%
+3VS GNDSRC SRCCLKC3LP CLK_PCIE_CARD# 1 2
R387 15 28 CLK_PCI5 R636 1 2 @ 10K_0402_5% +3VS R380 @ 49.9_0402_1%
4.7K_0402_5% GNDCPU CLKREQ3#/PCICLK5 R334 2 33_0402_5% CLK_PCI_1394 CLK_MCH_3GPLL 1
1 CLK_PCI_1394 (30) 2
2

CLK_SRC2 R300 1 2 0_0402_5% CLK_MCH_3GPLL R281 @ 49.9_0402_1%

G

1 2 +3VS 21 GNDREF SRCCLKT2LP 52 CLK_MCH_3GPLL (6)

CLK_MCH_3GPLL# 1 2
VGATE (6,20,47)
1 3 D_CK_SDATA 31 53 CLK_SRC2# R299 1 2 0_0402_5% CLK_MCH_3GPLL# R280 @ 49.9_0402_1%
(20,26,28,29) ICH_SMBDATA GNDPCI SRCCLKC2LP CLK_MCH_3GPLL# (6)
CLK_PCIE_LAN 1 2
D

Q15 R335 @ 49.9_0402_1%

G

35 GNDPCI CLKREQ2# 26 MCH_CLKREQ# (6)

2N7002_SOT23 R639 1 2 10K_0402_5% +3VS CLK_PCIE_LAN# 1 2
CLK_ENABLE# 1 3 42 50 CLK_SRC1 R302 1 MINI1@ 2 0_0402_5% CLK_PCIE_MINI1 R339 @ 49.9_0402_1%
+3VS GND48 SRCCLKT1LP CLK_PCIE_MINI1 (28)
D

R386 Q38 68 51 CLK_SRC1# R301 1 MINI1@ 2 0_0402_5% CLK_PCIE_MINI1#

GNDSRC SRCCLKC1LP CLK_PCIE_MINI1# (28)
4.7K_0402_5% 2N7002_SOT23
2
G

1 2 +3VS CLKREQ1# 46 MINI1_CLKREQ# (28)

2005/10/17 73 R626 1 2 10K_0402_5% +3VS
D_CK_SCLK THRM_PAD CLK_SRC0 R304 1
(20,26,28,29) ICH_SMBCLK 1 3 74 THRM_PAD LCD100/96/SRC0_TLP 47 2 0_0402_5% CLK_DREF_SSC
CLK_DREF_SSC (6)
75
D

Q14 THRM_PAD CLK_SRC0# R303 1

76 THRM_PAD LCD100/96/SRC0_CLP 48 2 0_0402_5% CLK_DREF_SSC#
CLK_DREF_SSC# (6)
2N7002_SOT23

ICS9LPR325AKLFT_MLF72
+1.05VS +1.05VS +1.05VS
ICS9LPR325AKLFT_MLF72: SA00000RE00
2

R623 R624 SLG8LP465VTR: SA00000TS00 R638

@ 56_0402_5% @ 1K_0402_5% @ 1K_0402_5%

R621 R622 R625 R643 R645

8.2K_0402_5% 1K_0402_5% 1K_0402_5% 8.2K_0402_5% 1K_0402_5%
1

4 CLKSEL0 1 CLKSEL1 CLKSEL2 1 4

2 1 2 MCH_CLKSEL0 (6) 1 2 MCH_CLKSEL1 (6) 2 1 2 MCH_CLKSEL2 (6)
1 2 1 2 CPU_BSEL1 (5) 1 2 1 2 CPU_BSEL2 (5)
1 2 1 2 CPU_BSEL0 (5) R617 R618 R646 R642
R616 R615 @ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5%
@ 1K_0402_5% 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Thursday, November 10, 2005 Sheet 14 of 47
A B C D E F G H
 5 4 3 2 1

LCD POWER CIRCUIT

+3VALW +3VS
+LCDVDD
W=60mils

1
1
R493 C12
R485 100K_0402_5%
D 300_0402_5% 4.7U_0805_10V4Z D
2

1 2

3
D S
G
Q25 2 2 1 2 Q28 AOS 3413
2N7002_SOT23 G R496 1K_0402_5%
S 1 SI2301BDS_SOT23

3
C600 +LCDVDD
D
W=60mils

1
1
D 0.047U_0402_16V7K
Q1 2
(8) GMCH_ENVDD 2
G 2N7002_SOT23 1 1
S C593 C597

3
1
4.7U_0805_10V4Z 0.1U_0402_16V4Z
R490 2 2
10K_0402_5%
2

+3VS

1
R492

4.7K_0402_5%
D27

2
BKOFF# 1 2 RB751V_SOD323 DISPOFF#
(32) BKOFF#

C C

LCD/PANEL BD. Conn.

JP1 I2CC_SCL I2CC_SCL (8)
+INVPWR_B+ DAC_BRIG I2CC_SDA I2CC_SDA (8)
40 20 DAC_BRIG (32)
INVT_PWM
39 19 INVT_PWM (32)
DISPOFF# TXOUT0-
38 18 TXOUT0- (8)
+3VS +LCDVDD TXOUT0+
37 17 TXOUT0+ (8)
I2CC_SCL (60 MIL)
I2CC_SDA 36 16 TXOUT1-
35 15 TXOUT1- (8)
TXOUT1+
34 14 TXOUT1+ (8)
TZOUT0- TXOUT0-
TZOUT0+ 33 13 TXOUT0+ TXOUT2+
32 12 TXOUT2+ (8)
TXOUT2-
31 11 TXOUT2- (8)
TZOUT1+ TXOUT1-
TZOUT1- 30 10 TXOUT1+ TXCLK-
29 9 TXCLK- (8)
TXCLK+
28 8 TXCLK+ (8)
TZOUT2+ TXOUT2+
TZOUT2- 27 7 TXOUT2- TZOUT0-
26 6 TZOUT0- (8)
TZOUT0+
25 5 TZOUT0+ (8)
TZCLK- TXCLK-
TZCLK+ 24 4 TXCLK+ TZOUT1+
23 3 TZOUT1+ (8)
TZOUT1-
B 22 2 TZOUT1- (8) B
21 1 TZOUT2+
TZOUT2+ (8)
ACES_88107-4000G TZOUT2-
TZOUT2- (8)
TZCLK-
TZCLK- (8)
(SAME AS ACES_87216-4016) TZCLK+
TZCLK+ (8)

+LCDVDD
+INVPWR_B+ +3VS
08/30 modified
L1 2 1 B+
KC FBM-L11-201209-221LMAT_0805 1 1 1
C11 C586 C591
L2 2 1
KC FBM-L11-201209-221LMAT_0805 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2
1 1
C930 C10

68P_0402_50V8K
680P_0603_50V7K 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 15 of 47
5 4 3 2 1
 A B C D E

CRT Connector D20

@
D21
@
D26
@ +5VS
W=40mils
+R_CRT_VCC +CRT_VCC
DAN217_SC59 DAN217_SC59 DAN217_SC59
D22 F1 W=40mils

1
2 1 1 2

RB411D_SOT23 1.1A_6VDC_FUSE
1
C575

3
0.1U_0402_16V4Z
2
+2.5VS 2 1 R474 +CRT_PULLUP
1 0_0603_5% 1

VGA:8P_0402_50V8K
UMA:10P_0402_50V8J
JP15
6
FCM2012C-800_0805 11
(8) GMCH_CRT_R 1 2 CRT_R_L 1
L36 7
12
(8) GMCH_CRT_G 1 2 CRT_G_L 2
L37 8
FCM2012C-800_0805 13
(8) GMCH_CRT_B 1 2 CRT_B_L 3
L42 DDC_MD2 9
FCM2012C-800_0805 1 1 1 14

1
10P_0402_50V8J1 1 1 4
R477 R483 R487 C96 C98 C99 10
C81 C82 C83 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 15
10P_0402_50V8J 2 2 2
1 5
150_0402_1% 150_0402_1% 150_0402_1% 2 2
10P_0402_50V8J2 C573

2
SUYIN_070549FR015S208CR
+CRT_VCC CRT_HSYNC_L
1 2
L38 FCM1608C-121T_0603 2
1 2 2 1 100P_0402_50V8J DSUB_12
C584 0.1U_0402_16V4Z R489 10K_0402_5% 1 2 CRT_VSYNC_L
L40 FCM1608C-121T_0603 1

1
U35
1 1
(HDQ70)

OE#
1 2 CRT_HSYNC 2 4 CRT_HSYNC_B C574
(8) GMCH_CRT_HSYNC A Y
R106 C577 C579 2

G
39_0402_5% 10P_0402_50V8K 10P_0402_50V8K 68P_0402_50V8K DSUB_15
2 SN74AHCT1G125DCKR_SC70-5 2 2 2

3
+CRT_VCC 1

Place closed to chipset C572

1 2 68P_0402_50V8K
C590 0.1U_0402_16V4Z 2

1
U36

OE#
1 2 CRT_VSYNC 2 4 CRT_VSYNC_B
(8) GMCH_CRT_VSYNC A Y
R116

G
39_0402_5% +CRT_VCC
SN74AHCT1G125DCKR_SC70-5

3
+3VS

1
R479
TV-OUT Conn. 4.7K_0402_5% R478

2
D1 D23 D24

G
@ @ @ 4.7K_0402_5%
DAN217_SC59 DAN217_SC59 DAN217_SC59 DSUB_12 1 3
GMCH_CRT_DATA (8)

S
1

1
Q27

2
2N7002_SOT23

G
DSUB_15 1 3 GMCH_CRT_CLK (8)

S
Q26
2

3
2N7002_SOT23
3 3
+3VS

TVOUT@ JP14
(8) GMCH_TV_LUMA 1 2 3
L39 FCM1608C-121T_0603 TV_CRMA_L 6
TVOUT@ TV_COMPS_L 7
(8) GMCH_TV_CRMA 1 2 5
L43 FCM1608C-121T_0603 2
TV_LUMA_L 4
(8) GMCH_TV_COMPS 1 2 1
L41 FCM1608C-121T_0603 8
TVOUT@ 9
1 1 1 TVOUT@ 1 1 C60 1
1

R486 R488 R484 C74 TVOUT@

C52 C72 C57 C56 TVOUT@ SUYIN_030107FR007SX08FU
TVOUT@ TVOUT@ 6P_0402_50V8K TVOUT@ TVOUT@ TVOUT@
2 2 2 6P_0402_50V8K 2 2 2 6P_0402_50V8K
150_0402_5% 150_0402_5% 6P_0402_50V8K 6P_0402_50V8K (ECQ60)
2

TVOUT@ 6P_0402_50V8K
150_0402_5%
TVOUT@

4
VGA:82P_0402_50V8J 4
UMA:6P_0402_50V8J

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT & TV-OUT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Monday, November 14, 2005 Sheet 16 of 47
A B C D E
 5 4 3 2 1

+2.5VS +3VS

0.1U_0402_16V4Z 0.1U_0402_16V4Z
+3VS
+2.5VS
1 1 1 1 1 1
C5 C3 C9 C4 C8 C6
7307@ 7307@ 7307@ 7307@ 7307@ 7307@
10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
BOM structure DVI from SDVO
D D
7307@ Stuff

12
28

15
21
36
42
48
1
U1 @ No _Stuff

DVDD
DVDD

TVDD
TVDD
AVDD
AVDD
AVDD
AVDD_PLL
32 13 DVI_TXC- +DVI_VCC
(8) SDVO_INT SDVOB_INT+ TLC#
33 14 DVI_TXC+
(8) SDVO_INT# SDVOB_INT- TLC
16 DVI_TXD0-
TDC0# DVI_TXD0+
(8) SDVOB_R 37 SDVOB_R+ TDC0 17

1
38 19 DVI_TXD1-
(8) SDVOB_R# SDVOB_R- TDC1#
20 DVI_TXD1+ R481 R482
TDC1 DVI_TXD2- 4.7K_0402_5% 4.7K_0402_5%
(8) SDVOB_G 40 SDVOB_G+ TDC2# 22
+2.5VS DVI_TXD2+ 7307@ 7307@
(8) SDVOB_G# 41 SDVOB_G- TDC2 23

2
(8) SDVOB_B 43 SDVOB_B+
1

R10 44 29 DVI_DET
(8) SDVOB_B# SDVOB_B- HPDET
10K_0402_5%
7307@ 46 11 DVI_SCLK
(8) SDVOB_CLK SDVOB_CLK+ SC_DDC
47 10 DVI_SDATA
(8) SDVOB_CLK# SDVOB_CLK- SD_DDC
2

AS AS 3 9
AS SC_PROM
(18,28,31) PLT_RST_BUF# 2 RESET# SD_PROM 8
1

25 VSWING

AGND_PLL
R9 5 SDVO_SDAT
SPD SDVO_SDAT (8)
10K_0402_5% 27 4 SDVO_SCLK
ATPG SPC SDVO_SCLK (8)

DGND
DGND
AGND
AGND
AGND
TGND
TGND
@ 26 SCEN

NC
NC
Keep 30mil spacing to other signals
2

1
+2.5VS
R6 R1 R5 7307@ CH7307_LQFP48

7
30
31
39
45
18
24
6

34
35
1.2K_0402_5% 10K_0402_5% 10K_0402_5% SDVO_SDAT 1 2
7307@ 7307@ 7307@ R12 7307@ 5.6K_0402_5%
C C

2
SDVO_SCLK 1 2
R11 7307@ 5.6K_0402_5%

DVI-D Connector D25

+DVI_VCC 7307@ RB411D_SOT23
JP16
DVI_TXD0- 17 14 1 2 +5VS
DVI_TXD0+ TMDS_DATA0- +5V
18 TMDS_DATA0+ W=40mils 1
DVI_TXD1- 9 C1
DVI_TXD1+ TMDS_DATA1- 7307@ 0.1U_0402_16V4Z
10 TMDS_DATA1+ 2
DVI_TXD2- 1
DVI_TXD2+ TMDS_DATA2- DVI_SCLK
2 TMDS_DATA2+ DDC_CLOCK 6

12 TMDS_DATA3-
B DVI_SDATA B
13 TMDS_DATA3+ DDC_DATA 7

4 TMDS_DATA4-
5 TMDS_DATA4+
20 TMDS_DATA5-
21 TMDS_DATA5+ Hot Plug Detect 16

DVI_TXC+ 23
DVI_TXC- TMDS_Clock+
24 TMDS_Clock-

TMDS_DATA2/4 shield 3
TMDS_DATA1/3 shield 11
TMDS_DATA0/5 shield 19
TMDS_Clock shield 22

8 Analog VSYNC GND 15

SUYIN_070939FR024S531PL

R2
DVI_DET 1 2
7307@ 20K_0402_5%
1

1
R7
D2 7307@
A @ SKS10-04AT_TSMA 100K_0402_5% A
2

(HDQ70)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CH7307 & DVI-D Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 17 of 47
5 4 3 2 1
 5 4 3 2 1

ICH7M(B-0)(QK17)[ES3]:SA00000JK30
D D

+3VS

R665 1 2 8.2K_0402_5% PCI_DEVSEL#

R629 1 2 8.2K_0402_5% PCI_STOP#

R630 1 2 8.2K_0402_5% PCI_TRDY#

R631 1 2 8.2K_0402_5% PCI_FRAME# (24,26,28,30) PCI_AD[0..31] U48B

PCI_AD0 E18 D7 PCI_REQ#0
AD0 REQ0# PCI_REQ#0 (30)
R648 1 2 8.2K_0402_5% PCI_PLOCK# PCI_AD1 C18 E7 PCI_GNT#0
AD1 GNT0# PCI_GNT#0 (30)
PCI_AD2 A16 C16 PCI_REQ#1
R668 1 2 8.2K_0402_5% PCI _IRDY# PCI_AD3 F18
AD2 PCI REQ1#
D16 PCI_GNT#1
PCI_REQ#1 (28)
AD3 GNT1# PCI_GNT#1 (28)
PCI_AD4 E16 C17 PCI_REQ#2
AD4 REQ2# PCI_REQ#2 (24)
R666 1 2 8.2K_0402_5% PCI_SERR# PCI_AD5 A18 D17 PCI_GNT#2
AD5 GNT2# PCI_GNT#2 (24) +3VS
PCI_AD6 E17 E13 PCI_REQ#3
AD6 REQ3# PCI_REQ#3 (26)
R628 1 2 8.2K_0402_5% PCI_PERR# PCI_AD7 A17 F13 PCI_GNT#3
AD7 GNT3# PCI_GNT#3 (26)
PCI_AD8 A15 A13 PCI_REQ#4
AD8 REQ4# / GPIO22

5
R664 1 2 8.2K_0402_5% PCI_REQ#4 PCI_AD9 C14 A14 U17
PCI_AD10 AD9 GNT4# / GPIO48 PCI_REQ#5 PLT_RST#
E14 C8 2

P
R649 1 AD10 GPIO1 / REQ5# B
2 8.2K_0402_5% PCI_REQ#3 PCI_AD11 D14 AD11 GPIO17 / GNT5# D8 Y 4 PLT_RST_BUF# (17,28,31)
PCI_AD12 B12 1
AD12 A

G
PCI_AD13 C13 B15 PCI_CBE#0
AD13 C/BE0# PCI_CBE#0 (24,26,28,30)
PCI_AD14 G15 C12 PCI_CBE#1 NC7SZ08P5X_NL_SC70-5
PCI_CBE#1 (24,26,28,30)

3
PCI_AD15 AD14 C/BE1# PCI_CBE#2
G13 AD15 C/BE2# D12 PCI_CBE#2 (24,26,28,30)
PCI_AD16 E12 C15 PCI_CBE#3
AD16 C/BE3# PCI_CBE#3 (24,26,28,30)
PCI_AD17 C11
PCI_AD18 AD17 PCI _IRDY#
D11 AD18 IRDY# A7 PCI_IRDY# (24,26,28,30) 2 1
C PCI_AD19 PCI_PAR R331 @ 0_0402_5% C
A11 AD19 PAR E10 PCI_PAR (24,26,28,30)
PCI_AD20 A10 B18 PCI_RST#
AD20 PCIRST# PCI_RST# (24,26,28,29,30)
PCI_AD21 F11 A12 PCI_DEVSEL#
+3VS AD21 DEVSEL# PCI_DEVSEL# (24,26,28,30)
PCI_AD22 F10 C9 PCI_PERR#
AD22 PERR# PCI_PERR# (24,26,28,30)
PCI_AD23 E9 E11 PCI_PLOCK#
PCI_AD24 AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10 PCI_SERR# (24,26,28)
R670 1 2 8.2K_0402_5% PCI_PIRQA# PCI_AD25 B9 F15 PCI_STOP#
AD25 STOP# PCI_STOP# (24,26,28,30)
PCI_AD26 A8 F14 PCI_TRDY#
AD26 TRDY# PCI_TRDY# (24,26,28,30)
R669 1 2 8.2K_0402_5% PCI_PIRQB# PCI_AD27 A6 F16 PCI_FRAME#
AD27 FRAME# PCI_FRAME# (24,26,28,30)
PCI_AD28 C7
R655 1 PCI_PIRQC# PCI_AD29 AD28 PLT_RST#
2 8.2K_0402_5% B6 AD29 PLTRST# C26 PLT_RST# (6,20,23,26,31,32)
PCI_AD30 E6 A9 CLK_PCI_ICH
AD30 PCICLK CLK_PCI_ICH (14)
R660 1 2 8.2K_0402_5% PCI_PIRQD# PCI_AD31 D6 B19 PCI_PME#
AD31 PME# PCI_PME# (26,28,32)
R632 1 2 8.2K_0402_5% PCI_PIRQE#

R644 1 2 8.2K_0402_5% PCI_PIRQF# PCI_PIRQA# A3

Interrupt I/F G8 PCI_PIRQE#
(24) PCI_PIRQA# PIRQA# GPIO2 / PIRQE# PCI_PIRQE# (30)
PCI_PIRQB# B4 F7 PCI_PIRQF#
(24) PCI_PIRQB# PIRQB# GPIO3 / PIRQF# PCI_PIRQF# (26)
R324 1 2 8.2K_0402_5% PCI_PIRQG# PCI_PIRQC# C5 F8 PCI_PIRQG#
PIRQC# GPIO4 / PIRQG# PCI_PIRQG# (28)
PCI_PIRQD# B5 G7 PCI_PIRQH#
PIRQD# GPIO5 / PIRQH# PCI_PIRQH# (28)
R650 1 2 8.2K_0402_5% PCI_PIRQH#

R633 1 2 8.2K_0402_5% PCI_REQ#0 AE5

MISC AE9
RSVD[1] RSVD[6]
AD5 RSVD[2] RSVD[7] AG8
R652 1 2 8.2K_0402_5% PCI_REQ#1 AG4 AH8
RSVD[3] RSVD[8]
AH4 RSVD[4] RSVD[9] F21
R651 1 2 8.2K_0402_5% PCI_REQ#2 AD9 AH20
RSVD[5] MCH_SYNC# MCH_ICH_SYNC# (6)
R654 1 2 8.2K_0402_5% PCI_REQ#5 Place closely pin A9
ICH7_BGA652~D

CLK_PCI_ICH
B B

2
R667
10_0402_5%
@

1
1
C851
10P_0402_50V8K
@
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(1/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 18 of 47
5 4 3 2 1
 5 4 3 2 1

C826
+RTCVCC 18P_0402_50V8J
2 1 ICH_RTCX1

10M_0402_5%
1 2005/11/02 X3

1
3 NC OUT 4

R614
R274
32.768KHZ_12.5P_1TJS125DJ2A073 2 1
1M_0402_5% NC IN U48A
C827
2

RTC
SM_INTRUDER# 18P_0402_50V8J AB1 AA6 LPC_AD0
RTXC1 LAD0 LPC_AD0 (31,32)
2 1 ICH_RTCX2 AB2 AB5 LPC_AD1
D RTCX2 LAD1 LPC_AD1 (31,32) D
AC4 LPC_AD2
LAD2 LPC_AD2 (31,32)
+RTCVCC 1 2 ICH_RTCRST# AA3 Y6 LPC_AD3
RTCRST# LAD3 LPC_AD3 (31,32)

LPC
+RTCVCC ENABLE INTERNAL R263
1.05V 20K_0402_5% ICH_INTVRMEN W4 AC3 LPC_DRQ0#
INTVRMEN LDRQ0# LPC_DRQ#0 (31)
SUSPEND SM_INTRUDER# Y5 AA5
INTRUDER# LDRQ1# / GPIO23
REGULARTOR
1

2 1 AB3 LPC_FRAME#
LFRAME# LPC_FRAME# (31,32)
R278 close to RAM door J3 @ JOPEN W1
332K_0402_1% EE_CS
Y1 EE_SHCLK 2 1 R249 10K_0402_5% +3VS
Y2 AE22 EC_GA20
EE_DOUT A20GATE EC_GA20 (32)

LAN
C427 W3 AH28 H_A20M#
H_A20M# (4)
2

EE_DIN A20M#

CPU
1U_0603_10V4Z
ICH_INTVRMEN 1 2 V3 AG27 H_CPUSLP_R# PAD
LAN_CLK CPUSLP# T25
U3 AF24 DPRSTP# R240 1 2 0_0402_5%
LAN_RSTSYNC TP1 / DPRSTP# H_DPRSTP# (4,47)
AH25 H_DPSLP#
+3VS TP2 / DPSLP# H_DPSLP# (4)
U5 R604 2 1 56_0402_5% +1.05VS
LAN_RXD0 H_FERR#
V4 LAN_RXD1 FERR# AG26 H_FERR# (4)
T5 LAN_RXD2
1

AG24 H_PW RGOOD

GPIO49 / CPUPWRGD H_PWRGOOD (4)
R610 U7 LAN_TXD0 H_IGNNE#
V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# (4)
10K_0402_5% V7 AG21
LAN_TXD2 INIT3_3V# H_INIT#
AF22 H_INIT# (4)
2

INIT# H_INTR
INTR AF25 H_INTR (4)
1 2 ICH_AC_BITCLK
(34) ICH_BITCLK_MDC +1.05VS

AC-97/AZALIA
SATA_LED# R627 39_0402_5% U1 R239 2 1 10K_0402_5%
ACZ_BCLK +3VS
(34) ICH_SYNC_MDC 1 2 ICH_AC_SYNC_R R6 AG23 EC_KBRST#
ACZ_SYNC RCIN# EC_KBRST# (32)
R298 39_0402_5%

1
1 2 ICH_AC_RST_R# R5 AF23 H_SMI#
(34) ICH_RST_MDC# ACZ_RST# SMI# H_SMI# (4)
R313 39_0402_5% AH24 H_NMI R605
NMI H_NMI (4)
1 2 ICH_AC_BITCLK (36) ICH_AC_SDIN0 T2
C (36) ICH_BITCLK_AUDIO ACZ_SDIN0 C
R634 39_0402_5% (34) ICH_AC_SDIN1 T3 AH22 H_STPCLK# 56_0402_5%
ACZ_SDIN1 STPCLK# H_STPCLK# (4)
T1

2
ICH_AC_SYNC_R ACZ_SDIN2 THRMTRIP_ICH# R606 1
(36) ICH_SYNC_AUDIO 1 2 THERMTRIP# AF26 2 24.9_0402_1% H_THERMTRIP#
H_THERMTRIP# (4,6)
R297 39_0402_5% 1 2 ICH_AC_SDOUT_R T4
(34) ICH_SDOUT_MDC ACZ_SDOUT
R292 39_0402_5% IDE_DA[0..2] (22,23)
1 2 ICH_AC_RST_R# AH17 IDE_DA0
(36) ICH_RST_AUDIO# DA0
R320 39_0402_5% (32) SATA_LED# SATA_LED# AF18 AE17 IDE_DA1
SATALED# DA1 IDE_DA2
DA2 AF17
(36) ICH_SDOUT_AUDIO 1 2 ICH_AC_SDOUT_R
MAINPWON (41,42,44)
R291 39_0402_5% (22) SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AF3 AE16 IDE_DCS1# IDE_DCS1# (22,23)
SATA_DTX_C_IRX_P0 SATA0RXN DCS1# IDE_DCS3#
(22) SATA_DTX_C_IRX_P0 AE3 SATA0RXP DCS3# AD16 IDE_DCS3# (22,23)
SATA_ITX_DRX_N0 AG2 R222
SATA0TXN

1
SATA
SATA_ITX_DRX_P0 AH2 @ 330_0402_5% C
SATA0TXP IDE_DD[0..15] (22,23)
AB15 IDE_DD0 +1.05VS 1 2 2 Q6
SATA_DTX_C_IRX_N2 DD0 IDE_DD1 B
AF7 SATA2RXN DD1 AE14
SATA_DTX_C_IRX_P2 AE7 AG13 IDE_DD2 E 2SC2411K_SC59

3
SATA2RXP DD2 IDE_DD3 @
AG6 SATA2TXN DD3 AF13
AH6 AD14 IDE_DD4
SATA2TXP DD4 IDE_DD5 H_THERMTRIP#
DD5 AC13
CLK_PCIE_SATA# AF1 AD12 IDE_DD6
(14) CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12 IDE_DD7
(14) CLK_PCIE_SATA SATA_CLKP DD7
AE12 IDE_DD8
DD8 IDE_DD9
AH10 SATARBIASN DD9 AF12
R613 1 2 24.9_0402_1% SATARBIAS AG10 AB13 IDE_DD10
SATARBIASP DD10 IDE_DD11
10mils DD11 AC14
IDE_DD12
DD12 AF14
AH13 IDE_DD13
DD13 IDE_DD14
R612 1 2 4.7K_0402_5% IDE_ DIORDY IDE_ DIORDY AG16
IDE DD14 AH14
AC15 IDE_DD15
+3VS (22,23) IDE_DIORDY IORDY DD15
IDE_IRQ AH16
(22,23) IDE_IRQ IDEIRQ
IDE_DDACK# AF16
(22,23) IDE_DDACK# DDACK#
R611 1 2 8.2K_0402_5% IDE_IRQ IDE_DIOW# AH15 AE15 IDE_DDREQ
B (22,23) IDE_DIOW# DIOW# DDREQ IDE_DDREQ (22,23) B
IDE_DIOR# AF15
(22,23) IDE_DIOR# DIOR#

ICH7_BGA652~D

SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0
C824 3900P_0402_50V7K SATA_ITX_C_DRX_N0 (22)

SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
C823 3900P_0402_50V7K SATA_ITX_C_DRX_P0 (22)

close ICH7 1 2 SATA_DTX_C_IRX_N0

R247 @ 1K_0402_5%
1 2 SATA_DTX_C_IRX_P0
R252 @ 1K_0402_5%

1 2 SATA_DTX_C_IRX_N2
R248 1K_0402_5%
1 2 SATA_DTX_C_IRX_P2
R254 1K_0402_5%

SATA_RXn/p need tie to ground when SATA port no used

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(2/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 19 of 47
5 4 3 2 1
 5 4 3 2 1

Place closely pin B2 Place closely pin AC1

+3VS CLK_ICH_48M CLK_ICH_14M
10K_0402_5% +3VALW
R607 1 2 SERIRQ

1
8.2K_0402_5% R656 R258

1
R609 1 2 PM_CLKRUN# 10_0402_5% 10_0402_5%
R325 R332 @ @
10K_0402_5% 2.2K_0402_5% 2.2K_0402_5%

2
R256 1 2 ICH_VGATE U48C
1 1

2
(14,26,28,29) ICH_SMBCLK ICH_SMBCLK C22 AF19 C844 C406
D +3VALW ICH_SMBDATA SMBCLK GPIO21 / SATA0GP 10P_0402_50V8K 10P_0402_50V8K D
(14,26,28,29) ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18

SMB
SATA
GPIO
10K_0402_5% LINKALERT# A26 AH19 @ @
R671 1 EC_SWI# ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
2 B25 SMLINK0 GPIO37 / SATA3GP AE19 1 R608 2
ICH_SMLINK1 A25 100_0402_5%
10K_0402_5% SMLINK1
R352 1 2 ICH_SMLINK0
AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M (14)

Clocks
10K_0402_5% EC_SWI# A28 B2 CLK_ICH_48M
(32) EC_SWI# RI# CLK48 CLK_ICH_48M (14)
R359 1 2 ICH_SMLINK1
SB_SPKR A19
(36) SB_SPKR SPKR
10K_0402_5% (31,33) SUS_STAT# SUS_STAT# A27 C20 SUS_CLK
R672 1 LINKALERT# ITP_DBRESET# SUS_STAT# SUSCLK
2 (4) ITP_DBRESET# A22 SYS_RST#

SYS
B24 PM_SLP_S3#
SLP_S3# PM_SLP_S3# (32)
150_0402_5% PM_BMBUSY# AB18 D23 SLP_S4#
R342 1 ITP_DBRESET# (6) PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4# SLP_S5#
2 SLP_S5# F22
SMBALERT# B23
1K_0402_5% GPIO11 / SMBALERT# SYS_PWROK R264
PWROK AA4 SYS_PWROK (6,35)

POWER MGT
R314 1 2 ICH_PCIE_WAKE# (14) PM_STP_PCI#
PM_STP_PCI# AC20 GPIO18 / STPPCI# 1 2 10K_0402_5%

GPIO
PM_STP_CPU# AF21 AC22 PM_DPRSLPVR
(14) PM_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR (6,47)
8.2K_0402_5% PM_DPRSLPVR : Need to series
R321 2 1 PM_BATLOW# A21 C21 PM_BATLOW#
(29) CP_PE# GPIO26 TP0 / BATLOW# a 500Ohm resistor to IMVP6
10K_0402_5% PROJECT_ID0 B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# (32)
R310 1 2 SPI_MOSI PROJECT_ID1 E23 GPIO28
LAN_RST# C19 PLT_RST# (6,18,23,26,31,32)
10K_0402_5% PM_CLKRUN# AG18
R635 1 SPI_MISO (26,28,31) PM_CLKRUN# GPIO32 / CLKRUN# EC_RSMRST#
2 RSMRST# Y4 EC_RSMRST# (32)
SB_INT_FLASH_SEL# AC19 R277 10K_0402_5%
(33) SB_INT_FLASH_SEL# GPIO33 / AZ_DOCK_EN#
10K_0402_5% IDE_HRESET# U2 1 2
(23) IDE_HRESET# GPIO34 / AZ_DOCK_RST#
R311 1 2 SPI_CS#
ICH_PCIE_WAKE# F20 E20 EC_SCI#
(26,28,29) ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# (32) +3VALW
10K_0402_5% SERIRQ AH21 A20
C (24,31,32) SERIRQ SERIRQ GPIO10 ACIN (32,45) C
R348 1 2 SMBALERT# EC_THERM# AF20 F19 C451
(32) EC_THERM# THRM# GPIO12
E19 EC_LID_OUT# 0.1U_0402_16V4Z 2 1
GPIO13 EC_LID_OUT# (32)
1 ICH_VGATE AD22
R780 10K_0402_5% 2005/10/27 (6,14,47) VGATE 2
R255 0_0402_5% VRMPWRGD GPIO14 R4
E22
GPIO15

5
1 2 R3 U18
GPIO24 EC_FLASH# SLP_S4#
AC21 GPIO D20 2

P
GPIO6 GPIO25 EC_FLASH# (33) B
AC18 GPIO7 GPIO35 / SATAREQ# AD21 SATA_CLKREQ# (14) Y 4 PM_SLP_S5# (32)
GEN@ 10K_0402_5% EC_SMI# E21 AD20 SLP_S5# 1
(32) EC_SMI# GPIO8 GPIO38 A

G
R676 1 2 AE20
GPIO39 NC7SZ08P5X_NL_SC70-5
2005/11/02

3
GRA@ 10K_0402_5% ICH7_BGA652~D Need update symbol
R675 1 2 PROJECT_ID0

@ 10K_0402_5%
R674 1 2 PROJECT_ID1
U48D
100K_0402_5% PCIE_PTX_C_IRX_N1 F26 V26 DMI_MTX_IRX_N0
(29) PCIE_PTX_C_IRX_N1 PERn1 DMI0RXN DMI_MTX_IRX_N0 (6)
R262 1 2 PM_DPRSLPVR PCIE_PTX_C_IRX_P1 F25 V25 DMI_MTX_IRX_P0
(29) PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_MTX_IRX_P0 (6)

DIRECT MEDIA INTERFACE

(29) PCIE_ITX_C_PRX_N1 C839 2 1 EXPCARD@
0.1U_0402_16V4Z PCIE_ITX_PRX_N1 E28 U28 DMI_ITX_MRX_N0
PETn1 DMI0TXN DMI_ITX_MRX_N0 (6)
@ 10K_0402_5% (29) PCIE_ITX_C_PRX_P1 C837 2 1 EXPCARD@
0.1U_0402_16V4Z PCIE_ITX_PRX_P1 E27 U27 DMI_ITX_MRX_P0
PETp1 DMI0TXP DMI_ITX_MRX_P0 (6)
R677 1 2 SUS_CLK
PCIE_PTX_C_IRX_N2 H26 Y26 DMI_MTX_IRX_N1
(28) PCIE_PTX_C_IRX_N2 PERn2 DMI1RXN DMI_MTX_IRX_N1 (6)
PCIE_PTX_C_IRX_P2 H25 Y25 DMI_MTX_IRX_P1
(28) PCIE_PTX_C_IRX_P2 PERp2 DMI1RXP DMI_MTX_IRX_P1 (6)
(28) PCIE_ITX_C_PRX_N2 C835 2 1 MINI2@ 0.1U_0402_16V4Z PCIE_ITX_PRX_N2 G28 W28 DMI_ITX_MRX_N1
PETn2 DMI1TXN DMI_ITX_MRX_N1 (6)
(28) PCIE_ITX_C_PRX_P2 C832 2 1 MINI2@ 0.1U_0402_16V4Z PCIE_ITX_PRX_P2 G27 W27 DMI_ITX_MRX_P1
PETp2 DMI1TXP DMI_ITX_MRX_P1 (6)

PCI-EXPRESS
PCIE_PTX_C_IRX_N3 K26 AB26 DMI_MTX_IRX_N2
(26) PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN DMI_MTX_IRX_N2 (6)
PCIE_PTX_C_IRX_P3 K25 AB25 DMI_MTX_IRX_P2
(26) PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP DMI_MTX_IRX_P2 (6)
(26) PCIE_ITX_C_PRX_N3 C831 2 1 8789@ 0.1U_0402_16V4Z PCIE_ITX_PRX_N3 J28 AA28 DMI_ITX_MRX_N2
PETn3 DMI2TXN DMI_ITX_MRX_N2 (6)
PROJECT_ID[1:0] (26) PCIE_ITX_C_PRX_P3 C830 2 1 8789@ 0.1U_0402_16V4Z PCIE_ITX_PRX_P3 J27 AA27 DMI_ITX_MRX_P2
PETp3 DMI2TXP DMI_ITX_MRX_P2 (6)
00 = Grapevine PCIE_PTX_C_IRX_N4 M26 AD25 DMI_MTX_IRX_N3
B (28) PCIE_PTX_C_IRX_N4 PERn4 DMI3RXN DMI_MTX_IRX_N3 (6) B
PCIE_PTX_C_IRX_P4 M25 AD24 DMI_MTX_IRX_P3
(28) PCIE_PTX_C_IRX_P4 PERp4 DMI3RXP DMI_MTX_IRX_P3 (6)
01 = Geneva (28) PCIE_ITX_C_PRX_N4 C829 2 1 MINI1@0.1U_0402_16V4Z PCIE_ITX_PRX_N4 L28 AC28 DMI_ITX_MRX_N3
PETn4 DMI3TXN DMI_ITX_MRX_N3 (6)
(28) PCIE_ITX_C_PRX_P4 C828 2 1 MINI1@0.1U_0402_16V4Z PCIE_ITX_PRX_P4 L27 AC27 DMI_ITX_MRX_P3
PETp4 DMI3TXP DMI_ITX_MRX_P3 (6)
10 = HBL51_PATA
P26 AE28 CLK_PCIE_ICH#
PERn5 DMI_CLKN CLK_PCIE_ICH# (14)
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH (14)
N28 PETn5
N27 C25 R673 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25 PERn6
T24 F1 USB20_N0
PERp6 USBP0N USB20_N0 (29)
R28 F2 USB20_P0
PETn6 USBP0P USB20_P0 (29)
R27 G4 USB20_N1
PETp6 USBP1N USB20_N1 (29)
RP44 G3 USB20_P1
USBP1P USB20_P1 (29)
5 4 USB_OC#1 R2 H1 USB20_N2
+3VALW SPI_CLK USBP2N USB20_N2 (29)
6 3 USB_OC#2 SPI_CS# P6 H2 USB20_P2
SPI_CS# SPI USBP2P USB20_P2 (29)
7 2 USB_OC#3 P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 (28)
8 1 USB_OC#4 J3 USB20_P3
USBP3P USB20_P3 (28)
SPI_MOSI P5 K1 USB20_N4
SPI_MOSI USBP4N USB20_N4 (34)
10K_1206_8P4R_5% SPI_MISO P2 K2 USB20_P4
SPI_MISO USBP4P USB20_P4 (34)
L4 USB20_N5
USBP5N USB20_N5 (34)
L5 USB20_P5
USBP5P USB20_P5 (34)
RP43 USB_OC#0 D3 M1 USB20_N6
(29) USB_OC#0 OC0# USBP6N USB20_N6 (34)
5 4 USB_OC#6 USB_OC#1 C4 OC1# USB USBP6P M2 USB20_P6
USB20_P6 (34)
6 3 USB_OC#7 USB_OC#2 D5 OC2# USBP7N N4 USB20_N7
USB20_N7 (28)
7 2 USB_OC#5 USB_OC#3 D4 OC3# USBP7P N3 USB20_P7
USB20_P7 (28)
8 1 USB_OC#4 E5
USB_OC#5 OC4# R653 22.6_0402_1%
C3 OC5# / GPIO29
10K_1206_8P4R_5% USB_OC#6 A2 D2 USBRBIAS 1 2
USB_OC#7 OC6# / GPIO30 USBRBIAS#
B3 OC7# / GPIO31 USBRBIAS D1
Within 500 mils
A ICH7_BGA652~D A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(3/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom HBL51 LA-3081P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, November 10, 2005 Sheet 20 of 47
5 4 3 2 1
 5 4 3 2 1

+1.05VS
U48F U48E
A4 VSS[0] VSS[98] P28
ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
Vcc1_05[4] L16 1 1 B11 VSS[4] VSS[102] R13
+1.5VS ICH_V5REF_SUS F6 L17 C426 C439 + C390 B14 R14
+5VS +3VS V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
D 0.1U_0402_16V4Z 220U_D2_2VMR15 D
AA22 Vcc1_5_B[1] Vcc1_05[7] M11 B20 VSS[7] VSS[105] R16
2 2 2
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
2

2
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 VSS[9] VSS[107] R18
R259 D11 C433 + C408 C449 C853 AB23 P18 C2 T6
Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108]
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
100_0402_5% RB751V_SOD323 220U_D2_2VMR15 AC24 T18 C27 T13
2 2 2 2 Vcc1_5_B[6] Vcc1_05[12] VSS[12] VSS[110]
AC25 U11 D10 T14
1

Vcc1_5_B[7] Vcc1_05[13] VSS[13] VSS[111]

AC26 Vcc1_5_B[8] Vcc1_05[14] U18 D13 VSS[14] VSS[112] T15
ICH_V5REF_RUN 15mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z AD26 V11 D18 T16
Vcc1_5_B[9] Vcc1_05[15] VSS[15] VSS[113]
2 2 2 AD27 Vcc1_5_B[10] Vcc1_05[16] V12 D21 VSS[16] VSS[114] T17
AD28 Vcc1_5_B[11] Vcc1_05[17] V14 D24 VSS[17] VSS[115] U4
C424 C425 Place closely pin D26 V16 E1 U12
1U_0603_10V4Z C410 0.1U_0402_16V4Z Vcc1_5_B[12] Vcc1_05[18] VSS[18] VSS[116]
D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
1 1 1 D28,T28,AD28. D28 V18 E4 U14
0.1U_0402_16V4Z Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
E25 Vcc1_5_B[16] Vcc3_3 / VccHDA U6 +3VS E15 VSS[23] VSS[120] U16
(1uF x1, 0.1uF x1) E26 Vcc1_5_B[17] +1.05VS
1 F3 VSS[24] VSS[121] U17
F23 R7 +3VALW C442 F4 U24
Vcc1_5_B[18] VccSus3_3/VccSusHDA VSS[25] VSS[122]
F24 Vcc1_5_B[19] F5 VSS[26] VSS[123] U25
G22 AE23 C435 0.1U_0402_16V4Z F12 U26
Vcc1_5_B[20] V_CPU_IO[1] 2 VSS[27] VSS[124]
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 1 2 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 F28 VSS[29] VSS[126] V13
+5VALW +3VALW 0.1U_0402_16V4Z
H23 Vcc1_5_B[23] G1 VSS[30] VSS[127] V15
J22 Vcc1_5_B[24] Vcc3_3[3] AA7 +3VS 1 2 G2 VSS[31] VSS[128] V24
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 G5 VSS[32] VSS[129] V27
2

K22 AB20 1 C446 G6 V28

R641 D31 Vcc1_5_B[26] Vcc3_3[5] C412 0.1U_0402_16V4Z VSS[33] VSS[130]
K23 Vcc1_5_B[27] Vcc3_3[6] AC16 G9 VSS[34] VSS[131] W6
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 1 2 G14 VSS[35] VSS[132] W24
10_0402_5% RB751V_SOD323 L23 AD18 0.1U_0402_16V4Z G18 W25
Vcc1_5_B[29] Vcc3_3[8] 2 C428 VSS[36] VSS[133]
M22 AG12 G21 W26
1

ICH_V5REF_SUS Vcc1_5_B[30] Vcc3_3[9] 4.7U_0805_10V4Z VSS[37] VSS[134]

15mils M23 Vcc1_5_B[31] Vcc3_3[10] AG15 G24 VSS[38] VSS[135] Y3
2 2 N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
C C838 C840 C
N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
P22 Vcc1_5_B[34] Vcc3_3[12] A5 +3VS H3 VSS[41] VSS[138] Y28

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
1U_0603_10V4Z 0.1U_0402_16V4Z P23 B13 H4 AA1
1 1 Vcc1_5_B[35] Vcc3_3[13] VSS[42] VSS[139]
R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H5 VSS[43] VSS[140] AA24
R23 Vcc1_5_B[37] Vcc3_3[15] B7 H24 VSS[44] VSS[141] AA25

C409

C413

C415
(1uF x1, 0.1uF x1) R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C855 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]

0.1U_0402_16V4Z

1U_0402_6.3V4Z
U23 Vcc1_5_B[47] VccSus3_3[1] P7 +3VALW K27 VSS[54] VSS[151] AB27
0.1U_0402_16V4Z V22 1 1 1 1 K28 AB28
2 Vcc1_5_B[48] VSS[55] VSS[152]

C431

C437
V23 A24 C856 C854 L13 AC2
Vcc1_5_B[49] VccSus3_3[2] VSS[56] VSS[153]
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS R226 +1.5VS_DMIPLLR +1.5VS_DMIPLL
B27 K3 M4 AD4
0.5_0603_1% R225 Vcc3_3[1] VccSus3_3[7] +3VALW VSS[62] VSS[159]
VccSus3_3[8] K4 1 1 M5 VSS[63] VSS[160] AD7
0.01U_0402_16V7K

1 2 1 2 +1.5VS_DMIPLL AG28 K5 C441 C834 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
10U_0805_10V4Z

VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11

0_0603_5% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C819

AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C820

AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C404 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z B
AF6 Vcc1_5_A[7] VccSus3_3[17] M7 M28 VSS[72] VSS[169] AE11
2
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
+1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
0.1U_0402_16V4Z

N11 VSS[77] VSS[174] AE25

+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z

1 Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

C405

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8

C825

AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11

1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27
2 C397 AD10 Vcc1_5_A[13] Vcc1_5_A[25] AC8 N17 VSS[83] VSS[180] AF28
2 C411 0.1U_0402_16V4Z
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] T28 VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD N26 AG11
Vcc1_5_A[17] VccSus1_05[2] T30 VSS[87] VSS[184]
AH9 G20 ICH_G20 PAD P3 AG14
Vcc1_5_A[18] VccSus1_05[3] T29 VSS[88] VSS[185]
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C841 C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C852 P15 AH3
0.1U_0402_16V4Z C842 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T26 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_ Y7 0.1U_0402_16V4Z
T27 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652~D
VccSus3_3/VccLAN3_3[3]
+3VALW W7 VccSus3_3/VccLAN3_3[4]
1 ICH7_BGA652~D
C430
A A
0.1U_0402_16V4Z
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ICH7-M(4/4)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B HBL51 LA-3081P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, November 09, 2005 Sheet 21 of 47
5 4 3 2 1
 A B C D E

+3VS

2005/10/20

1
U26 R395
100K_0402_5%
PIDE_DD0 62 32 SATA_DTX_IRX_P0 @ R394
PIDE_DD1 HDD0 TXP SATA_DTX_IRX_N0 8040@ 0_0402_5%
64 31

2
PIDE_DD2 HDD1 TXM SATA_ITX_C_DRX_P0 SATA_RESET# IDE_RST#
PIDE_DD3
2
5
HDD2 SATA RXP 27
28 SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_P0 (19)
1
1 2

PIDE_DD4 HDD3 RXM SATA_ITX_C_DRX_N0 (19) C486

7 HDD4
PIDE_DD5 11 17 SATA_RESET# @
PIDE_DD6 HDD5 RST# +3VS 1U_0603_10V4Z
13 HDD6 T0 33
PIDE_DD7 2
15 HDD7 T1 34

Config & Debug

PIDE_DD8 14 35 T2 R804 1 2 @ 10K_0402_5%
1 PIDE_DD9 HDD8 T2 T3 R797 1 1
12 HDD9 T3 36 2 8040@ 10K_0402_5%
PIDE_DD10 10 37
PIDE_DD11 HDD10 T4 T5 R421 1
6 HDD11 T5 38 2 8040@ 4.7K_0402_5%

Parallel ATA
PIDE_DD12 3 39 R805 1 2 @ 10K_0402_5%
PIDE_DD13 HDD12 T6
1 HDD13 T7 40
PIDE_DD14 63 20
PIDE_DD15 HDD14 CNFG2 CNFG1 R406 1
61 HDD15 CNFG1 19 2 @ 10K_0402_5%
18 CNFG0 R397 1 2 @ 10K_0402_5%
CNFG0 ATAIOSEL R407 1
21 2 8040@ 10K_0402_5% PATA
PIDE_DA0 50
ATAIOSEL
IDE (JP24)
PIDE_DA1 HDA0 SATA_XTALI
PIDE_DA2
51 HDA1 XTLIN/OSC 22
SATA_XTALO
Connector
49 HDA2 XTLOUT 23
PIDE_CS0# 48 +3VS Y4
PIDE_CS1# HCS0# SATA_XTALI 1 SATA_XTALO
47 HCS1# 2
26 R415 1 2 12.1K_0603_1%
PIDE_HIOCS16# ISET 8040@ 25MHZ_12PF_1BG25000CK1B
52 HIOCS16# VDDIO_0 44 R

1
PIDE_INTRQ 53 4 +3VS 8040@
HINTRQ VDDIO_1
2

PIDE_DMACK# 54 9 +1.8VS MBK1608121YZF_0603 L31 R800 PATA

R798 PIDE_DIORDY HDMACK# VDD_0 8040@
55 HIORDY VDD_1 41 0_0402_5%
10K_0402_5% PIDE_DIOR# 58 56 8040@ ICH7M SATA IDE Connector
PIDE_DIOW# HDIOR# VDD_2
@ 59 24 SPIF3811A

2
PIDE_DREQ HDIOW# VAA1 +1.8VS_VDDA
60 29
1

1
PIDE_RESET# HDMARQ VAA2 R411 1M_0402_5%
16 HRESET# Power
46 25 GNDA_3811 8040@
HPDIAG# VSS1
30
1
C866
1
C504
1
C517 1 1
(JP33)
VSS2
1

T86 8 R424 8040@ 8040@ 8040@ C498 C500

UAO GND_0 0_0603_5% 0.1U_0402_16V4Z 4.7U_0805_10V4Z 12P_0402_50V8J 12P_0402_50V8J
PAD
T87 PAD UAI
45 UAO UART GND_1 42
2 2 2 8040@ 8040@
43 UAI GND_2 57 1
@
2
0.1U_0402_16V4Z 2 2 R SATA
8040@
SATA CONN (JP32)
2

R799 88SA8040_QFN64
10K_0402_5% 8040@
2 2

+1.8VS +3VS
8040@
0.1U_0402_16V4Z 0.1U_0402_16V4Z SATA_ITX_C_R_DRX_P0 2 3 SATA_ITX_C_DRX_P0
SATA_ITX_C_R_DRX_N0 1 4 SATA_ITX_C_DRX_N0
1 1 1 1 1 1 1 RP45 0_0404_4P2R_5%
C501 C515 C488 C505 C516 C489 C519 +3VS
8040@ 8040@ 8040@ 8040@ 8040@ 8040@ 8040@ 8040@
4.7U_0805_10V4Z 4.7U_0805_10V4Z SATA_DTX_R_IRX_N0 2 3 SATA_DTX_IRX_N0 1
2 2 2 2 2 2 2 SATA_DTX_R_IRX_P0 SATA_DTX_IRX_P0 C865
1 4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z RP46 0_0404_4P2R_5%
0.1U_0402_16V4Z
2 @
(19) SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 1 2 SATA_DTX_IRX_N0
C507 3900P_0402_50V7K
+3VS SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0
Place closed to Connector (19) SATA_DTX_C_IRX_P0 1
C510
2
3900P_0402_50V7K
PIDE_DIORDY 1 2
R419 8040@ 4.7K_0402_5%
Place closed to U21
SATA HDD Conn.
PIDE_DREQ 1 2 JP32
R408 8040@ 5.6K_0402_5% IDE_DD[0..15]
PIDE_INTRQ 1 2 09/06 :changed the size of RP from 1206 to 0404 IDE_DA[0..2]
IDE_DD[0..15] (19,23)
1 GND
R426 8040@ 10K_0402_5% IDE_DA[0..2] (19,23) SATA_ITX_C_R_DRX_P0 2
PIDE_DD7 SATA_ITX_C_R_DRX_N0 HTX+
1 2 3 HTX-
R356 @ 10K_0402_5% 4
3 SATA_DTX_R_IRX_N0 GND 3
5 HRX-
SATA_DTX_R_IRX_P0 6
RP49 PATA@ RP50 PATA@ HRX+
7 GND
+5VS PIDE_DD2 2 3 IDE_DD2 PIDE_DIOR# 2 3 IDE_DIOR#
PIDE_DD12 IDE_DD12 PIDE_DIOW# IDE_DIOW# IDE_DIOR# (19,23)
1 4 1 4 IDE_DIOW# (19,23)
0.1U_0402_16V4Z 10U_0805_10V4Z 0_0404_4P2R_5% 0_0404_4P2R_5%
PIDE_DD3 2 3 IDE_DD3 PIDE_DREQ 2 3 IDE_DDREQ 8
IDE_DDREQ (19,23) +3VS VCC3.3
1 1 1 1 1 PIDE_DD11 1 4 IDE_DD11 PIDE_DD15 1 4 IDE_DD15 9
C868 C869 C530 C531 C867 0_0404_4P2R_5% 0_0404_4P2R_5% VCC3.3
10 VCC3.3
RP51 PATA@ RP52 PATA@ 11 GND
12 GND
2 2 2 2 2 RP53 PATA@ RP54 PATA@ 13 GND
PIDE_DD4 2 3 IDE_DD4 PIDE_DA1 2 3 IDE_DA1 14
+5VS VCC5
1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z PIDE_DD10 1 4 IDE_DD10 PIDE_INTRQ 1 4 IDE_IRQ 15
0_0404_4P2R_5% 0_0404_4P2R_5% IDE_IRQ (19,23) VCC5
16 VCC5
PIDE_DD5 2 3 IDE_DD5 PIDE_DMACK# 2 3 IDE_DDACK# 17
PATA HDD Conn. PIDE_DD9 1 4 IDE_DD9
0_0404_4P2R_5%
PIDE_DIORDY 1 4 IDE_ DIORDY
0_0404_4P2R_5%
IDE_DDACK# (19,23)
IDE_DIORDY (19,23) 18
GND
RESERVED
19 GND
JP33 RP55 PATA@ RP56 PATA@ 20 23
PIDE_RESET# VCC12 GND1
1 1 2 2 21 VCC12 GND2 24
PIDE_DD7 3 3 PIDE_DD8 RP57 PATA@ RP58 PATA@
PIDE_DD6 4 4 PIDE_DD9 PIDE_DD6 IDE_DD6 PIDE_CS1# IDE_DCS3#
22 VCC12
5 5 6 6 2 3 2 3 IDE_DCS3# (19,23)
PIDE_DD5 7 7 PIDE_DD10 PIDE_DD8 IDE_DD8 PIDE_CS0# IDE_DCS1#
PIDE_DD4 8 8 PIDE_DD11
1 4
0_0404_4P2R_5%
1 4
0_0404_4P2R_5% IDE_DCS1# (19,23) OCTEK_SAT-22SG1G_NR
9 9 10 10
PIDE_DD3 11 11 PIDE_DD12 PIDE_DD7 IDE_DD7 PIDE_DA2 IDE_DA2
PIDE_DD2 12 12 PIDE_DD13 PIDE_RESET#
2 3
IDE_RST# PIDE_DA0
2 3
IDE_DA0
PIDE_DD1
13 13
15 15
14 14 PIDE_DD14
1 4
0_0404_4P2R_5% IDE_RST# (23) 1 4
0_0404_4P2R_5% (NEW)
PIDE_DD0 16 16 PIDE_DD15 RP59 PATA@ RP60 PATA@
17 17 18 18 Change Library
19 19 20 20
PIDE_DREQ 21 21 RP61 PATA@
PIDE_DIOW# 22 22 PIDE_DD0 IDE_DD0
23 23 24 24 2 3
PIDE_DIOR# 25 25 PIDE_DD14 IDE_DD14 PIDE_LED# IDE_LED#
4 PIDE_DIORDY 26 26 PCSEL 1
1 4
0_0404_4P2R_5%
1
R435
2
PATA@ 0_0402_5% IDE_LED# (23,32) 4
27 27 28 28 2
PIDE_DMACK# 29 29 R417 475_0402_1% PIDE_DD1 IDE_DD1 PIDE_PDIAG# IDE_PDIAG#
PIDE_INTRQ 30 30 PIDE_DD13
2 3
IDE_DD13
1
R428
2
PATA@ 0_0402_5% IDE_PDIAG# (23)
31 31 32 32 1 4
PIDE_DA1 33 33 PIDE_PDIAG# 0_0404_4P2R_5%
PIDE_DA0 34 34 PIDE_DA2 RP62 PATA@
35 35 36 36
PIDE_CS0# 37 37 PIDE_CS1# For PATA HDD+ODD only
PIDE_LED# 38 38
39 39 40 40
+5VS 41 41
43 43
42 42 +5VS Security Classification Compal Secret Data Compal Electronics, Inc.
44 44 2005/06/20 2006/06/20 Title
47 47 48 48 Issued Date Deciphered Date
OCTEK_HDD-22SG1G_NR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ULI M5285
Size Document Number Rev
(NEW) AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 22 of 47
A B C D E
 A B C D E F G H

+5VS Placea caps. near ODD CONN.

0.1U_0402_16V4Z 10U_0805_10V4Z

1 1 1 1 1
C207 C231
+3VS
C206 C205 C232
2 2 2 2 2 IDE_DD[0..15] C293
1 (19,22) IDE_DD[0..15] 1
1 2 0.1U_0402_16V4Z
1000P_0402_50V7K 1U_0603_10V4Z 10U_0805_10V4Z IDE_DA[0..2]
(19,22) IDE_DA[0..2]

5
U6
IDE_HRESET# 2

P
(20) IDE_HRESET# B
4 IDE_RST#
Y IDE_RST# (22)
PLT_RST# 1
(6,18,20,26,31,32) PLT_RST# A

G
NC7SZ08P5X_NL_SC70-5

3
JP24 2005/11/01
1 1 2 2
3 3 4 4
IDE_RST# 5 6 IDE_DD8
IDE_DD7 5 6 IDE_DD9
7 7 8 8
IDE_DD6 9 10 IDE_DD10
IDE_DD5 9 10 IDE_DD11
11 11 12 12
IDE_DD4 13 14 IDE_DD12
IDE_DD3 13 14 IDE_DD13
15 15 16 16
IDE_DD2 17 18 IDE_DD14
IDE_DD1 17 18 IDE_DD15
19 19 20 20
IDE_DD0 21 22 IDE_DDREQ
21 22 IDE_DDREQ (19,22)
23 24 IDE_DIOR#
23 24 IDE_DIOR# (19,22)
IDE_DIOW# 25 26
(19,22) IDE_DIOW# 25 26
IDE_ DIORDY 27 28 IDE_DDACK#
(19,22) IDE_DIORDY 27 28 IDE_DDACK# (19,22)
IDE_IRQ 29 30
(19,22) IDE_IRQ 29 30
IDE_DA1 31 32 IDE_PDIAG# 1 2 R149 +5VS
IDE_DA0 31 32 IDE_DA2 100K_0402_5%
33 33 34 34
(19,22) IDE_DCS1# IDE_DCS1# 35 36 IDE_DCS3# IDE_DCS3# (19,22)
IDE_LED# 35 36
(22,32) IDE_LED# 37 37 38 38
+5VS 39 39 40 40 +5VS
2 2
41 41 42 42
43 43 44 44
45 45 46 46
+5VS 1 2 IDE_CSEL 47 48
R133 @ 475_0402_1% 47 48 IDE_PDIAG#
49 49 50 50 IDE_PDIAG# (22)
1 2 51 51 52 52
R134 475_0402_1%
8040@ 2005/11/04 OCTEK_CDR-50JL1G

IDE_CSEL
(NEW)
2005/10/27
Grounding for Master (When use SATA HDD)
Open or High for Slaver (Normal) IDE_LED#
+5VS 2 1
R146 100K_0402_5%

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ODD & SATA HDD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 23 of 47
A B C D E F G H
 A B C D E

+S1_VCC +3VS
VPPD0
(25) VPPD0
VPPD1
(25) VPPD1
VCCD0#
+3VS (25) VCCD0#
40mil VCCD1#
(25) VCCD1#

M13

M12

G13
N13

N12

D12
H11
S1_A[0..25]

G1
C8

N4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A7

B4

K2

F3
L9
L6
S1_A[0..25] (25)
U22
1 1 1 1 1 1 1 S1_D[0..15]

VCCD1#
VCCD0#

VPPD1
VPPD0

VCCA2
VCCA1

VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
S1_D[0..15] (25)
C857 C863 C848 C861 C862 C850 C849

0.1U_0402_16V4Z
2 2 2 2 2 2 2
PCI_AD31 C2 B2 S1_D10
1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z PCI_AD30 AD31 CAD31/D10 S1_D9 1
C1 AD30 CAD30/D9 C3
PCI_AD29 D4 B3 S1_D1
PCI_AD28 AD29 CAD29/D1 S1_D8
D2 AD28 CAD28/D8 A3
PCI_AD27 D1 C4 S1_D0 +3VS
PCI_AD26 AD27 CAD27/D0 S1_A0
E4 AD26 CAD26/A0 A6
PCI_AD25 E3 D7 S1_A1
PCI_AD24 AD25 CAD25/A1 S1_A2
E2 AD24 CAD24/A2 C7 1 1
PCI_AD23 F2 A8 S1_A3 C472 C859
PCI_AD[0..31] PCI_AD22 AD23 CAD23/A3 S1_A4
(18,26,28,30) PCI_AD[0..31] F1 AD22 CAD22/A4 D8
PCI_AD21 G2 A9 S1_A5 4.7U_0805_10V4Z 0.1U_0402_16V4Z
PCI_CBE#[0..3] PCI_AD20 AD21 CAD21/A5 S1_A6 2 2
(18,26,28,30) PCI_CBE#[0..3] G3 AD20 CAD20/A6 C9
PCI_AD19 H3 A10 S1_A25
PCI_AD18 AD19 CAD19/A25 S1_A7
H4 AD18 CAD18/A7 B10
PCI_AD17 J1 D10 S1_A24
PCI_AD16 AD17 CAD17/A24 S1_A17
J2 AD16 CAD16/A17 E12
PCI_AD15 N2 F10 S1_IOWR#
AD15 CAD15/IOWR# S1_IOWR# (25)
CLK_PCI_PCM CLK_SD_48M PCI_AD14 M3 E13 S1_A9
PCI_AD13 AD14 CAD14/A9 S1_IORD# +S1_VCC
N3 AD13 CAD13/IORD# F13 S1_IORD# (25)

1
PCI_AD12 K4 F11 S1_A11
R393 R678 PCI_AD11 AD12 CAD12/A11 S1_OE#
M4 AD11 CAD11/OE# G10 S1_OE# (25)
@ 10_0402_5% @ 10_0402_5% PCI_AD10 K5 G11 S1_CE2# 1 1
+3VS AD10 CAD10/CE2# S1_CE2# (25)
PCI_AD9 L5 G12 S1_A10 C864 C860
PCI_AD8 AD9 CAD9/A10 S1_D15
M5 H12

2
SM_CD# PCI_AD7 AD8 CAD8/D15 S1_D7 0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 2 1 1 K6 AD7 CAD7/D7 H10
R662 43K_0402_5% C485 C858 PCI_AD6 S1_D13 2 2
M6 AD6 CAD6/D13 J11
PCI_AD5 N6 J12 S1_D6
@ 15P_0402_50V8J @ 15P_0402_50V8J PCI_AD4 AD5 CAD5/D6 S1_D12
M7 AD4 CAD4/D12 K13
2 2 PCI_AD3 S1_D5
N7 J10

PCI Interface
PCI_AD2 AD3 CAD3/D5 S1_D11
L7 AD2 CAD2/D11 K10

CARDBUS
PCI_AD1 K7 K12 S1_D4
PCI_AD0 AD1 CAD1/D4 S1_D3
N8 AD0 CAD0/D3 L13
2 PCI_CBE#3 S1_REG# 2
E1 CBE3# CCBE3#/REG# B7 S1_REG# (25)
PCI_CBE#2 J3 A11 S1_A12
PCI_CBE#1 CBE2# CCBE2#/A12 S1_A8
N1 CBE1# CCBE1#/A8 E11
PCI_CBE#0 N5 H13 S1_CE1#
CBE0# CCBE0#/CE1# S1_CE1# (25)
PCI_RST# G4 B9 S1_RST
(18,26,28,29,30) PCI_RST# PCIRST# CRST#/RESET S1_RST (25)
(18,26,28,30) PCI_FRAME# J4 B11 S1_A23
FRAME# CFRAME#/A23 S1_A15
(18,26,28,30) PCI_IRDY# K1 IRDY# CIRDY#/A15 A12
(18,26,28,30) PCI_TRDY# K3 A13 S1_A22
TRDY# CTRDY#/A22 S1_A21
(18,26,28,30) PCI_DEVSEL# L1 DEVSEL# CDEVSEL#/A21 B13
L2 C12 S1_A20
(18,26,28,30) PCI_STOP# STOP# CSTOP#/A20
L3 C13 S1_A14
(18,26,28,30) PCI_PERR# PERR# CPERR#/A14
M1 A5 S1_WAIT#
(18,26,28) PCI_SERR# SERR# CSERR#/WAIT# S1_WAIT# (25)
(18,26,28,30) PCI_PAR M2 D13 S1_A13
PCI_REQ#2 PAR CPAR/A13 S1_INPACK#
(18) PCI_REQ#2 A1 PCIREQ# CREQ#/INPACK# B8 S1_INPACK# (25)
B1 C11 S1_WE#
(18) PCI_GNT#2 PCIGNT# CGNT#/WE# S1_WE# (25)
CLK_PCI_PCM H1 B12 1 2 S1_A16
(14) CLK_PCI_PCM PCICLK CCLK/A16 R416 33_0402_5%
L8 C5 S1_BVD1
RIOUT#_PME# CSTSCHG/BVD1_STSCHG# S1_BVD1 (25)
+3VS 1 2 L11 D5 S1_WP
SUSPEND# CCLKRUN#/WP_IOIS16# S1_WP (25)
R663 10K_0402_5%
PCI_AD20 1 2 F4 D11 S1_A19
R680 100_0402_5% IDSEL CBLOCK#/A19
K8 D6 S1_RDY# S1_CD2# S1_CD1#
(18) PCI_PIRQA# MFUNC0 CINT#/READY_IREQ# S1_RDY# (25)
R368 1 2 SD_PULLHIGH N9 2 2
(25) MS_PWREN# MFUNC1
0_0402_5% K9 M9 PCM_SPK# C506 C487
(18) PCI_PIRQB# MFUNC2 SPKROUT PCM_SPK# (36)
@ N10 B5 S1_BVD2
(20,31,32) SERIRQ MFUNC3 CAUDIO/BVD2_SPKR# S1_BVD2 (25)
SM_CD# L10 10P_0402_50V8K 10P_0402_50V8K
5IN1_LED# MFUNC4 S1_CD2# 1 1
(32) 5IN1_LED# N11 MFUNC5 CCD2#/CD2# A4 S1_CD2# (25)
M11 L12 S1_CD1#
MFUNC6 CCD1#/CD1# S1_CD1# (25)
SDOC# J9 D9 S1_VS2
(25) SDOC# MFUNC7 CVS2/VS2# S1_VS2 (25)
C6 S1_VS1
3 CVS1/VS1 S1_VS1 (25) 3
A2 S1_D2
PCI_RST# CRSV3/D2 S1_A18
M10 GRST# CRSV2/A18 E10
MFUNC5[3:0] = (0 1 0 1) J13 S1_D14
CRSV1/D14
MFUNC5[4] = 1
E7
SD/MMC/MS/SM H7
+VCC_SD VCC_SD MSINS# MS_INS# (25)
J8 XD_PWREN#
MSPWREN#/SMPWREN# XD_PWREN# (25)
SD_CD# E8 H8 MSBS_XDD1
(25) SD_CD# SDCD# MSBS/SMDATA1 MSBS_XDD1 (25)
SD_WP# F8 E9 MS_CLK R683 1 2 33_0402_5%
(25) SD_WP# SDWP/SMWPD# MSCLK/SMRE# MSCLK_XDRE# (25)
SD_PWREN# G7 G9 MSD0_XDD2 4IN1@
(25) SD_PWREN# SDPWREN33# MSDATA0/SMDATA2 MSD0_XDD2 (25)
H9 MSD1_XDD6
MSDATA1/SMDATA6 MSD1_XDD6 (25)
CLK_SD_48M H5 G8 MSD2_XDD5
(14) CLK_SD_48M SDCLKI MSDATA2/SMDATA5 MSD2_XDD5 (25)
33_0402_5% F9 MSD3_XDD3
MSDATA3/SMDATA3 MSD3_XDD3 (25)
R681 1 2 4IN1@ SD_CLK F6
(25) SDCK_XDWE# SDCLK/SMWE#
SDCM_XDALE E5
(25) SDCM_XDALE SDCMD/SMALE
SDDA0_XDD7 E6 H6
(25) SDDA0_XDD7 SDDAT0/SMDATA7 SMBSY# XD_BSY# (25)
SDDA1_XDD0 F7 J7 XD_CD#
(25) SDDA1_XDD0 SDDAT1/SMDATA0 SMCD# XD_CD# (25)
SDDA2_XDCL F5 J6 XD_WP#
(25) SDDA2_XDCL SDDAT2/SMCLE SMWP# XD_WP# (25)
SDDA3_XDD4 G6 J5
(25) SDDA3_XDD4 SDDAT3/SMDATA4 SMCE# XD_CE# (25)

2
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
G5 GND_SD R661
4IN1@ 2.2K_0402_5%
CB714_LFBGA169
D3
H2
L4
M8
K11
F12
C10
B6

1
**CB714 use B0 version

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cardbus Controller CB714
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 24 of 47
A B C D E
 A B C D E

PCMCIA Socket 1
JP9
GND
35 GND
S1_D3 2
S1_CD1# DATA3
(24) S1_CD1# 36 CD1#
S1_D4 3
+S1_VCC S1_D11 DATA4
37
PCMCIA Power Control S1_D5
S1_D12
4
38
DATA11
DATA5
S1_D6 DATA12
1 1 5 DATA6
+S1_VCC C502 C494 S1_D13 39
S1_D7 DATA13
6 DATA7
10U_0805_10V4Z 0.1U_0402_16V4Z S1_D14 40
2 2 S1_CE1# DATA14
1 U23
40mil (24) S1_CE1# S1_D15
7 CE1# 1
41 DATA15
13 S1_A10 8
VCC S1_CE2# ADD10
VCC 12 (24) S1_CE2# 42 CE2#
9 11 S1_OE# 9
12V VCC +S1_VPP (24) S1_OE# S1_VS1 OE#
(24) S1_VS1 43 VS1#
40mil S1_A11 10
+5VS +S1_VPP S1_IORD# ADD11
(24) S1_IORD# 44 IORD#
W=40mil 1 S1_A9 11
S1_IOWR# ADD9
VPP 10 (24) S1_IOWR# 45 IOWR#
1 1 C522 1 1 S1_A8 12
C479 0.1U_0402_16V4Z C493 C520 S1_A17 ADD8
5 5V 46 ADD17
C480 2 S1_A13
6 5V 13 ADD13
10U_0805_10V4Z 0.1U_0402_16V4Z S1_A[0..25] S1_A18 47
2 2 2 2 (24) S1_A[0..25] ADD18
0.1U_0402_16V4Z 1 VCCD0# 10U_0805_10V4Z S1_A14 14
VCCD0 VCCD0# (24) S1_D[0..15] ADD14
2 VCCD1# (24) S1_D[0..15] S1_A19 48
+3VS VCCD1 VCCD1# (24) ADD19
15 VPPD0 S1_WE# 15
VPPD0 VPPD0 (24) (24) S1_WE# WE#
14 VPPD1 S1_A20 49
VPPD1 VPPD1 (24) ADD20
W=40mil S1_RDY# 16
(24) S1_RDY# S1_A21 READY
3 3.3V 50 ADD21
1 1 4 3.3V OC 8 +S1_VCC 17 VCC
SHDN
C482 C481 51
GND

+S1_VCC VCC
+S1_VPP 18 VPP
10U_0805_10V4Z +S1_VPP 52 VPP
1

2 2
0.1U_0402_16V4Z CP2211FD3_SSOP16 S1_OE# S1_A16
1 2 +S1_VCC 19
7

16

R396 R684 43K_0402_5% S1_A22 ADD16

53 ADD22
10K_0402_5% S1_WP 2 1 S1_A15 20
+S1_VCC ADD15
R410 43K_0402_5% S1_A23 54
S1_RST S1_A12 ADD23
1 2 +S1_VCC 21
2

R429 43K_0402_5% S1_A24 ADD12

55 ADD24
S1_CE1# 1 2 +S1_VCC S1_A7 22
R679 43K_0402_5% S1_A25 ADD7
56 ADD25
S1_CE2# 1 2 +S1_VCC S1_A6 23
2 R682 43K_0402_5% S1_VS2 ADD6 2
(24) S1_VS2 57 VS2#
VCCD0# 1 2 S1_A5 24
R392 10K_0402_5% S1_RST ADD5
(24) S1_RST 58 RESET
VCCD1# 1 2 S1_A4 25
R389 10K_0402_5% S1_WAIT# ADD4
(24) S1_WAIT# 59 WAIT#
S1_A3 26
S1_INPACK# ADD3
(24) S1_INPACK# 60 INPACK#
S1_A2 27
+VCC_SD S1_REG# ADD2
(24) S1_REG# 61 REG#
S1_A1 28
4IN1@ S1_BVD2 ADD1
(24) S1_BVD2 62 BVD2
1 1 1 S1_A0 29
SD/MS Power Control C793 C804 C803 4IN1@
(24) S1_BVD1
S1_BVD1
S1_D0
63
30
ADD0
BVD1 (NEW)
XD Power Control 4IN1@ 10U_0805_10V4Z
2
0.1U_0402_16V4Z
2 0.1U_0402_16V4Z
2
S1_D8
S1_D1
64
31
DATA0
DATA8
S1_D9 DATA1
65 DATA9 GND 69
+3VS S1_D2 32 70
+3VS S1_D10 DATA2 GND
40mil S1_WP
66 DATA10
xD PU and PD. Close to Socket (24) S1_WP 33 WP
2

+3VS +VCC_XD S1_CD2# 67

(24) S1_CD2# CD2#
2

R192 +3VS +VCC_XD 34

R191 U9 GND
68 GND
4IN1@ 10K_0402_5% 1 8 4IN1@ 10K_0402_5% 2 1 XD_CD#
GND OUT R208 @ 43K_0402_5% SANTA_130601-7_LT
2 7 1 1
1

IN OUT C754 C753

3 6
1

XD_PWREN# IN OUT SDOC# +VCC_XD

4 5
(24) XD_PWREN# EN# FLG SDOC# (24)
4IN1@ 0.1U_0402_16V4Z 4 IN 1 Socket
1

G528_SO8 2
4IN1@ 10U_0805_10V4Z 2
(HDQ70)
1

4IN1@ R589 1 2 MSCLK_XDRE# JP27

2005/10/17 R190 4IN1@ 300_0402_5% R203 4IN1@ 2.2K_0402_5%
0_0402_5% 1 2 SDCK_XDWE# +VCC_XD 34 14 +VCC_SD
3 4IN1@ R196 4IN1@ 2.2K_0402_5% XD-VCC SD-VCC 3
4 IN 1 CONN 3
1 2

XD_CE# MS-VCC
1 2
2

D R201 4IN1@2.2K_0402_5% SD / MMC / MS(PRO) / XD

SD_PWREN# XD_PWREN# 2 Q34 2N7002_SOT23 1 2 XD_BSY# SDDA1_XDD0 26 15 SDCK_XDWE#
(24) SD_PWREN# (24) SDDA1_XDD0 XD-D0 SD-CLK
G 4IN1@ R205 4IN1@ 2.2K_0402_5% MSBS_XDD1 27 16 SDDA0_XDD7
(24) MSBS_XDD1 XD-D1 SD-DAT0
S MSD0_XDD2 28 17 SDDA1_XDD0
(24) MS_PWREN# (24) MSD0_XDD2
3

MSD3_XDD3 XD-D2 SD-DAT1 SDDA2_XDCL

(24) MSD3_XDD3 29 XD-D3 SD-DAT2 11
SDDA3_XDD4 30 12 SDDA3_XDD4
(24) SDDA3_XDD4 XD-D4 SD-DAT3
MSD2_XDD5 31 13 SDCM_XDALE
(24) MSD2_XDD5 XD-D5 SD-CMD
MSD1_XDD6 32 2 SD_CD#
(24) MSD1_XDD6 XD-D6 SD-CD-SW SD_CD# (24)
SDDA0_XDD7 33 35 SD_WP#
(24) SDDA0_XDD7 XD-D7 SD-WP-SW SD_WP# (24)
Reserve for SD,MS CLK.
Close to Socket (24) SDCK_XDWE#
SDCK_XDWE# 24 4 MSCLK_XDRE#
XD_WP# XD-WE MS-SCLK MSD0_XDD2
+VCC_XD 1 2 +VCC_SD (24) XD_WP# 25 XD-WP MS-DATA0 8
R209 0_0603_5% SDCK_XDWE# 1 2 4IN1@ SDCM_XDALE 23 9 MSD1_XDD6
(24) SDCM_XDALE XD-ALE MS-DATA1
4IN1@ C783 10P_0402_50V8K XD_CD# 18 7 MSD2_XDD5
(24) XD_CD# XD-CD MS-DATA2
XD_BSY# 19 5 MSD3_XDD3
(24) XD_BSY# XD-R/B MS-DATA3
MSCLK_XDRE#1 2 MSCLK_XDRE# 20 6 MS_INS#
(24) MSCLK_XDRE# XD-RE MS-INS MS_INS# (24)
C788 10P_0402_50V8K XD_CE# 21 10 MSBS_XDD1
(24) XD_CE# XD-CE MS-BS
4IN1@ SDDA2_XDCL 22
(24) SDDA2_XDCL XD-CLE
4IN1-GND 1
4IN1-GND 36

TAITW_R007-520-L3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCMCIA Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 25 of 47
A B C D E
 5 4 3 2 1

+3VALW +2.5V_LAN +3V_LAN +LAN_18_12

0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VALW 1 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R224 4401@ 0_0805_5%
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C379 C359 C355 C350 C317 C311 C384 +3VS 1 2 C363 C319 C333 C328 C341 C318 C312 C347 C346 C345 C303
8789@ 8789@ 8789@ R223 5789@ 0_0805_5%
2 2 2 2 2 2 2
5789 only 2 2 2 2 2 2 2 2 2 2 2

4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

PCI_AD0 R237 1 2 4401@ 0_0402_5% AD0 +REGOUT25 R214 1 2 4401@ 0_0603_5% +3VALW
For BCM5789 +3VALW
D R216 5787@ 0_0402_5% D
1 2
PCI_AD1 R232 1 2 4401@ 0_0402_5% AD1 2 1 R220 1 2 8789@ 0_0603_5% +2.5V_LAN 1K_0402_5% 1 2
R221 5787@ 0_0402_5% C387 100U_B2_4VM 8789@

+
1 2
For BCM4401E

1
PCI_AD2 R231 1 2 4401@ 0_0402_5% AD2 8789@ C315
R230 1 2 5787@ 0_0402_5% Colsed to M14 2005/11/01 +3VALW R187 R188 R189 0.1U_0402_16V4Z
PCI_AD3 R228 1 2 4401@ 0_0402_5% AD3 1 2 U8 1K_0402_5% 1K_0402_5%
R217 1 2 5787@ 0_0402_5% C361 0.1U_0402_16V4Z SPROM_CS 1 8 8789@ 8789@ 8789@
PCI_AD4 R229 4401@ 0_0402_5% AD4 U13A SPROM_CLK CS VCC
1 2 2 7 1

2
R218 5787@ 0_0402_5% SPROM_DOUT SK NC C301 U7
1 2 3 DI NC 6
PCI_AD5 R236 1 2 4401@ 0_0402_5% AD5 AD0 M7 E13 LAN_MIDI3+ SPROM_DIN 4 5 0.1U_0402_16V4Z 8 1
AD0/(NC) DC_E13/(TRD3+) LAN_MIDI3+ (27) DO GND VCC A0
R215 1 2 5787@ 0_0402_5% AD1 N7 E14 LAN_MIDI3- 4401@ SPROM_WP 7 2
AD1/(NC) DC_E14/(TRD3-) LAN_MIDI3- (27) 2 WP A1
AD2 P7 D13 LAN_MIDI2+ AT93C46-10SI-2.7_SO8 SPROM_CLK 6 3
AD2/(NC) DC_D13/(TRD2+) LAN_MIDI2+ (27) SCL NC
AD3 P5 D14 LAN_MIDI2- 4401@ SPROM_CS 5 4
PCI_AD11 R783 1 2 4401@ 0_0402_5% AD11 AD4 N5
AD3/(NC) BCM4401E DC_D14/(TRD2-)
C13 LAN_MIDI1+
LAN_MIDI2- (27) SDA GND
AD4/(NC) TRD1+ LAN_MIDI1+ (27)
PCI_AD14 R784 1 2 4401@ 0_0402_5% AD14 AD5 LAN_MIDI1- AT24C256_SO8
PCI_AD16 R785 1 2 4401@ 0_0402_5% AD16 PCI_AD6
M5
P4
AD5/(NC) /(BCM5789) TRD1- C14
B13 LAN_MIDI0+
LAN_MIDI1- (27)
8789@
AD6/(NC) TRD0+ LAN_MIDI0+ (27)
L23 PCI_AD7 N4 B14 LAN_MIDI0-
AD7/(NC) TRD0- LAN_MIDI0- (27)
BLM18AG601SN1D_0603 2005/11/01 PCI_AD8 P3 U13B
+LAN_XTALVDD PCI_AD9 AD8/(NC) +3VALW R806 5787@
+3VALW 1 2 N3 AD9/(NC) Place closed to L14 & K14
4401@ PCI_AD10 +PLLVDD 2 4.7K_0402_5%
L22
1
C336 AD11
N2
M1
AD10/(NC) PLLVDD/(GPHY_PLLVDD) G14
C360 1 2 0.1U_0402_16V4Z
+LAN_18_12 B8
E5
VDDC_B8 BCM4401E DC_A9/(NC) A9
B9
1

BLM18AG601SN1D_0603 PCI_AD12 AD11/(NC) VDDC_E5 DC_B9/(NC)

+2.5V_LAN 1 2 0.1U_0402_16V4Z PCI_AD13

M2
M3
AD12/(NC)
L14 C354 1 2 4.7U_0805_10V4Z
E6
E7
VDDC_E6 /(BCM5789) DC_C10/(NC) C10
C12 +3VALW
8789@ 2 AD14 AD13/(NC) REGSUP18_1/(REGSUP25) VDDC_E7 DC_C12/(CS#) D9
L1 AD14/(NC) REGSUP18_0/(REGSUP12) K14 E8 VDDC_E8 DC_D9/NC) D9

3
L19 PCI_AD15 L2 Q4 E9 D10 D10 1 2
BLM18AG601SN1D_0603 AD16 AD15/(NC) VDDC_E9 DC_D10/(NC) C388 5787@
K1 AD16/(NC) E10 VDDC_E10 DC_F11/(SO) F11
+3VALW 1 2 +LAN_BIASVDD PCI_AD17 E3 J13 1 MMJT9435T1G_SOT223 F5 K9 0.1U_0402_16V4Z
4401@ PCI_AD18 AD17/(NC) DC_J13/(REGCTL12) 8789@ VDDC_F5 DC_K9 5787@
1 D1 AD18/(NC) F10 VDDC_F10 DC_K10 K10 1 2
L18 C314 PCI_AD19 D2 +LAN_18_12 G4 L5 R250 4.7K_0402_5% C389 5787@
BLM18AG601SN1D_0603 PCI_AD20 AD19/(NC) VDDC_G4 DC_L5 4.7U_0805_10V4Z
D3 J14 J4 L7 1 2

2
4
0.1U_0402_16V4Z PCI_AD21 AD20/(NC) REG18OUT/(REGSEN12) VDDC_J4 DC_L7/(NC)
+2.5V_LAN 1 2 C1 AD21/(NC) J5 VDDC_J5 DC_L8 L8

4
8789@ 2 PCI_AD22 Q5
B1 AD22/(NC) 1 1 J10 VDDC_J10 DC_H11 H11
C PCI_AD23 +REGOUT25 C348 C352 MBT35200MT1G_TSOP6~D C
B2 AD23/(NC) REGSUP18/(REGOUT25) M14 K4 VDDC_K4 DC_L11 L11
PCI_AD[0..31] PCI_AD24 D4 K5 L12 5787@
(18,24,28,30) PCI_AD[0..31] AD24/(NC) VDDC_K5 DC_L12/(NC)
PCI_AD25 A5 0.1U_0402_16V4Z 10U_0805_10V4Z K6 L13 CTL25 3
PCI_AD26 AD25/(NC) SPROM_CS 2 2 VDDC_K6 DC_L13/(NC) R251 5787@ 0_0402_5%
B5 AD26/(NC) SPROM_CS/(EEDATA) L10 K7 VDDC_K7 DC_M9 M9
+3VALW R177 1 2 5787@ 4.7K_0402_5% SERR# PCI_AD27 B6 K11 SPROM_CLK K8 M10 1 2
PCI_AD28 AD27/(NC) SPROM_CLK/(EECLK) SPROM_DOUT VDDC_K8 DC_M10/(NC)
C6 J11 M11

1
2
5
6
R808 1 AD28/(NC) SPROM_DOUT/(NC) DC_M11
+3VS 2 5789@ 4.7K_0402_5% PCI_AD29 C7 AD29/(NC) SPROM_DIN/(NC) N13 SPROM_DIN
DC_M12/(NC) M12
PCI_AD30 C8 2005/11/01 +3V_LAN A7 M13 R234 5787@ 0_0402_5%
R212 1 CBE#1 PCI_AD31 AD30/(NC) VDDIOPCI_A7 DC_M13/(NC)
+3VS 2 @ 1K_0402_5% C9 AD31/(NC) B3 VDDIOPCI_B3 DC_N11/(NC) N11 1 2
J12 R181 1 2 1K_0402_5% +3VALW 2 1 C376 C5 N14 R233 5787@ 0_0402_5%
VAUX_PRSNT R168 1 VDDIOPCI_C5 DC_N14/(NC)
GPIO0/(GPIO0_TST_CLKOUT) G12 2 @ 10K_0402_5% E1 VDDIOPCI_E1 DC_P11/(NC) P11 1 2
M4 H13 SPROM_WP 4.7U_0805_10V4Z E4 P14
(18,24,28,30) PCI_CBE#0 CBE0#/(NC) GPIO1 VDDIOPCI_E4 DC_P14/(NC)
R213 1 2 4401@ 0_0402_5% CBE#1 L3 G13 R197 1 2 10K_0402_5% 2 1 C351 G1
(18,24,28,30) PCI_CBE#1 CBE1#/(NC) DC_G13/(GPIO2) VDDIOPCI_G1
F3 8789@ K3
(18,24,28,30) PCI_CBE#2 CBE2#/(NC) VDDIOPCI_K3
R172 1 2 4401@ 0_0402_5% CBE#3 C4 0.1U_0402_16V4Z L4 B4 +REGOUT25
(18,24,28,30) PCI_CBE#3 CBE3#/(NC) VDDIOPCI_L4 VSS_B4
LINK_LED10/(LINKLED#) A11 LAN_LINK# (27) 2 1 C358 P2 VDDIOPCI_P2 VSS_B7 B7
PCI_AD17 1 2 LAN_IDSEL A4 B11 B12
R179 4401@ 100_0402_5% IDSEL/(NC) LINK_LED100/(SPD100LED#) R180 1 VSS_B12
COL_LED/(SPD1000LED#) A12 2 8789@ 0_0402_5% 0.1U_0402_16V4Z
VSS_E2 E2
(18,24,28,30) PCI_FRAME# F2 FRAME#/(NC) ACT_LED/(TRAFFICLED#) B10 LAN_ACTIVITY# (27) 2 1 C324 P1 VESD1 VSS_F6 F6
(18,24,28,30) PCI_IRDY# F1 IRDY#/(NC) G2 VESD2 VSS_F7 F7
G3 0.1U_0402_16V4Z A1 F8 Change Q5 P/N:SB000004M10
(18,24,28,30) PCI_TRDY# TRDY#/(NC) VESD3 VSS_F8
R206 1 2 4401@ 0_0402_5% DEVSEL# H3 D7 TCK R166 1 2 4401@ 4.7K_0402_5% F9
(18,24,28,30) PCI_DEVSEL# DEVSEL#/(NC) TCK VSS_F9
(18,24,28,30) PCI_STOP# H1 STOP#/(NC) TDI H12 VSS_G5 G5
R211 1 2 4401@ 0_0402_5% PERR# J2 D6 +3VALW D11 G6
(18,24,28,30) PCI_PERR# PERR#/(ATTN_IND#) TDO VDDIO_D11 VSS_G6
R176 1 2 4401@ 0_0402_5% SERR# A2 C11 TMS R184 1 2 5789@ 4.7K_0402_5% G11 G7
(18,24,28) PCI_SERR# SERR#/(ATTN_BTTN#) TMS VDDIO_G11 VSS_G7
J1 D12 TRST# R167 1 2 4.7K_0402_5% K12 G8
(18,24,28,30) PCI_PAR PAR/(NC) TRST# VDDIO_K12 VSS_G8
CLK_PCI_LAN A3 G9
(14) CLK_PCI_LAN PCI_CLK/(NC) VSS_G9
VSS_G10 G10
R204 1 2 4401@ 0_0402_5% H14 +LAN_XTALVDD H5
(18) PCI_PIRQF# R242 1 XTALVDD VSS_H5
(18,24,28,29,30) PCI_RST# 2 4401@ 0_0402_5% LAN_INTA# H2 INTA#/(PWR_IND#) XTALO N12 XTALO R219 1 2 200_0402_5% LAN_XTALO +AVDDL F12 AVDD_F12/(AVDDL) VSS_H6 H6
R243 1 2 8789@ 0_0402_5% LAN_RESET# C2 P12 LAN_XTALI F13 H7
(6,18,20,23,31,32) PLT_RST# PCI_RST#/(PERST#) XTALI AVDD_F13/(AVDDL) VSS_H7
J3 +PCIE_PLLVDD M8 H8
B (18) PCI_GNT#3 GNT#/(NC) DC_M8/(PCIE_PLLVDD) VSS_H8 B
C3 +PCIE_SDSVDD M6 H9
(18) PCI_REQ#3 REQ#/(NC) DC_M6/(PCIE_SDS_VDD) VSS_H9
PM_CLKRUN# H4 E12 H10
(20,28,31) PM_CLKRUN# R175 1 0_0402_5% CLKRUN#/(NC) EEDATA_PXE/(SI) VSS_H10
(18,28,32) LAN_PME# 2 A6 PME#/(WAKE#) EECLK_PXE/(SCLK) E11 VSS_J6 J6
R182 1 2 @ 0_0402_5% +2.5V_LAN A8 J7
(20,28,29) ICH_PCIE_WAKE# DC_A8/(VDDP) VSS_J7
D5 DC_D5/(VDDP) VSS_J8 J8
(20) PCIE_PTX_C_IRX_P3 C381 1 2 8789@ 0.1U_0402_16V4Z PCIE_PTX_IRX_P3 N6 L9 P13 J9
C380 1 PCIE_PTX_IRX_N3 NC_N6/(PCIE_TXDP) EXT_POR/(DC) DC_P13/(VDDP) VSS_J9
(20) PCIE_PTX_C_IRX_N3 2 8789@ 0.1U_0402_16V4Z P6 NC_P6/(PCIE_TXDN) VREF/(NC) K13 VSS_K2 K2
L6 R171 1 2 10K_0402_5% +AVDD_A13 A13 N1
PCIE_ITX_C_PRX_P3 TEST_MODE/(LOW_PWR) DC_A13/(AVDD) VSS_N1
(20) PCIE_ITX_C_PRX_P3 P10 RESERVED_P10/(PCIE_RXDP) VSS_N9 N9
PCIE_ITX_C_PRX_N3 N10 D8 R174 1 2 5789@ 4.7K_0402_5% +AVDD_F14 F14 P9
(20) PCIE_ITX_C_PRX_N3 RESERVED_N10/(PCIE_RXDN) DC_D8/(PCIE_TST) DC_F14/(AVDD) VSS_P9

(14) CLK_PCIE_LAN N8 RESERVED_N8/(REFCLK+)

CLK_PCI_LAN P8 A14 +LAN_BIASVDD BCM4401E_BCM5789
(14) CLK_PCIE_LAN# RESERVED_P8/(REFCLK-) BIASVDD
5789 only 4401@
1

+3VS R193 1 2 5789@ 4.7K_0402_5% F4 A10 R165 1 2 4401@ 1.27K_0402_1%

R178 DC_F4/(REFCLK_SEL) RDAC D9 R244 1 2 5787@ 0_0402_5% ICH_SMBDATA (14,20,28,29)
10_0402_5% R194 1 2 @ 4.7K_0402_5% R173 1 2 8789@ 1.24K_0402_1% D10 R245 1 2 5787@ 0_0402_5% ICH_SMBCLK (14,20,28,29)
@ BCM4401E_BCM5789
4401@
2

1
C302 L26 L17
18P_0402_50V8J L21 BLM18AG601SN1D_0603 BLM18AG601SN1D_0603
@ BLM18AG601SN1D_0603 Y1 +LAN_18_12 1 2 +PCIE_PLLVDD +2.5V_LAN 1 2 +AVDD_A13
2 +AVDDL LAN_XTALI LAN_XTALO 8789@ 8789@
+LAN_18_12 1 2 1 2 1 1 1
1 1 C400 C385 C313
C322 C320 1 25MHZ_20PF_6X25000017 1 8789@ 8789@ 8789@
(SA00000OD10) (SA00000SZ00) 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.47U_0603_16V4Z C382 C383 2 2 2
2 2 27P_0402_50V8J 27P_0402_50V8J
2 2 L25 L20
PIN 4401E(10/100 LAN) 5789(10/100/1000 LAN) 5787(10/100/1000 LAN)
L24 BLM18AG601SN1D_0603 BLM18AG601SN1D_0603
RDAC 1.27K 1.24K 1.24K BLM18AG601SN1D_0603 +LAN_18_12 1 2 +PCIE_SDSVDD +2.5V_LAN 1 2 +AVDD_F14
A +PLLVDD 8789@ 8789@ A
+LAN_18_12 1 2 1 1 1
1 1 C378 C377 C327
C326 C330 8789@ 8789@ 8789@
BOM structure 4401E(10/100 LAN) 5789(10/100/1000 LAN) 5787(10/100/1000 LAN) 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2
2 2
4401@ Stuff No_Stuff No_Stuff
5789@ No_Stuff Stuff No_Stuff Security Classification Compal Secret Data Compal Electronics, Inc.
5787@ No_Stuff No_Stuff Stuff Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

8789@ No_Stuff Stuff Stuff THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN BCM4401E/Jade15
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
@ No_Stuff No_Stuff No_Stuff DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 26 of 47
5 4 3 2 1
 5 4 3 2 1

LAN BCM4401E/ BCM5789

D D

Place these components colsed to LAN chip

unpop when use BCM4401E(10/100)

1 1
GbE Transformer: GST5009 (SP050005610) 09/06 modified (symbol must be updated)
C287 C288
0.1U_0402_16V4Z 0.1U_0402_16V4Z 10/100 Transformer : TST1284-LF (SP050001X10)
5789@ 5789@ JP23
2 2 +2.5V_LAN +3VALW LAN_ACTIVITY#
(26) LAN_ACTIVITY# 12 Amber LED-
R132 2 1 300_0402_5% 11 Amber LED+

1
SHLD4 16

1
L57 L55 RJ45_MIDI3- 8 PR4-
1

49.9_0402_1% 8789@ R151 1 2 15

+3VALW SHLD3
R161 R162 R163 R164 0_0603_5% RJ45_MIDI3+ 7
C 5789@ 5789@ 5789@ 5789@ 4401@ FBM-11-160808-121-T_0603 PR4+ C
1
49.9_0402_1% 49.9_0402_1% 49.9_0402_1% T31 RJ45_MIDI1- 6

2
FBM-11-160808-121-T_0603 C7 PR2-
2

1 24 220P_0402_25V8J RJ45_MIDI2- 5
LAN_MIDI3- TCT1 MCT1 RJ45_MIDI3- 2 PR3-
(26) LAN_MIDI3- 2 TD1+ MX1+ 23
(26) LAN_MIDI3+ LAN_MIDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI2+ 4
TD1- MX1- PR3+
4 21 RJ45_MIDI1+ 3
LAN_MIDI2- TCT2 MCT2 RJ45_MIDI2- PR2+
(26) LAN_MIDI2- 5 TD2+ MX2+ 20
(26) LAN_MIDI2+ LAN_MIDI2+ 6 19 RJ45_MIDI2+ RJ45_MIDI0- 2
TD2- MX2- PR1-
SHLD2 14
7 18 RJ45_MIDI0+ 1
LAN_MIDI1- TCT3 MCT3 RJ45_MIDI1- PR1+
(26) LAN_MIDI1- 8 TD3+ MX3+ 17 SHLD1 13
(26) LAN_MIDI1+ LAN_MIDI1+ 9 16 RJ45_MIDI1+ LAN_LINK# 10
TD3- MX3- (26) LAN_LINK# Green LED-
10 15 R155 2 1 300_0402_5% 9
LAN_MIDI0- TCT4 MCT4 RJ45_MIDI0- Green LED+
(26) LAN_MIDI0- 11 TD4+ MX4+ 14
(26) LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+ SUYIN_100073FR012S100ZL
TD4- MX4- L56
1

+3VALW 1 2
R160 R159 R158 R157 1

1
49.9_0402_1% 49.9_0402_1% 0.1U_0402_16V4Z 0.5u_GST5009 FBM-11-160808-121-T_0603
49.9_0402_1% 49.9_0402_1% 0189@ 4401@ C101
0189@ 0189@ 0189@ R147 R145 220P_0402_25V8J RJ45_GND 1 2 LANGND
2

75_0402_1% 75_0402_1% 2
1 1 1 1 1 1
C258 C245 C188 C215 C284

2
1 1 1000P_1206_2KV7K C296 C298
C286 C285 0.1U_0402_16V4Z 4.7U_0805_10V4Z
0189@ 0189@ 2 2 2 2 2 2
B 0.1U_0402_16V4Z 0.1U_0402_16V4Z B
2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

RJ45_TER2

RJ45_TER3
RJ45_MIDI3+ R141 1 2 4401@ 0_0402_5%
RJ45_MIDI3- R137 1 2 4401@ 0_0402_5%

RJ45_MIDI2+ R144 1 2 4401@ 0_0402_5%

RJ45_MIDI2- R143 1 2 4401@ 0_0402_5%
1

reseved for BCM4401E(10/100)

R142 R135
75_0402_1% 75_0402_1%
2

RJ45_GND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45/RJ11
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P 0.2

Date: Wednesday, November 09, 2005 Sheet 27 of 47

5 4 3 2 1
 A B C D E

+3VS +1.5VS +3VALW

+3VALW
+5VS +3VS
1 1 1 1 1 1
W=40mils C14 C605 C603 C602 C604 C601
0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z MINI1@ MINI1@ MINI1@ MINI1@ MINI1@ MINI1@
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1
C797
C794 C393 C392 C798 C800 C801 C394 C796 C795 C792
10U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2 JP17
ICH_PCIE_WAKE# 1 2 +3VS
1 1000P_0402_50V7K (20,26,29) ICH_PCIE_WAKE# 1 2 1
1000P_0402_50V7K 1000P_0402_50V7K 0.1U_0402_16V4Z WLAN_BT_DATA 3 4
WLAN_BT_CLK 3 4
5 5 6 6 +1.5VS
(14) MINI1_CLKREQ# 7 7 8 8
9 9 10 10
(14) CLK_PCIE_MINI1# 11 11 12 12
(14) CLK_PCIE_MINI1 13 13 14 14
15 15 16 16

17 17 18 18
PCI_AD[0..31] 19 20 MINI1_OFF#
PCI_AD[0..31] (18,24,26,30) 19 20 MINI1_OFF# (32)
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# (17,18,31)
(20) PCIE_PTX_C_IRX_N4 23 23 24 24 +3VALW
JP28 25 26
TIP RING (20) PCIE_PTX_C_IRX_P4 25 26
1 1 2 2 27 27 28 28
29 30 ICH_SMBCLK ICH_SMBCLK (14,20,26,29)
KEY KEY 29 30
3 4 (20) PCIE_ITX_C_PRX_N4 31 32 ICH_SMBDATA ICH_SMBDATA (14,20,26,29)
3 4 31 32
5 5 6 6 (20) PCIE_ITX_C_PRX_P4 33 33 34 34
7 7 8 8 35 35 36 36
9 10 37 38
D10
11
9
11
10
12 12 39
37
39
38
40 40 2005/09/10
WL_OFF# 1 2 13 14 41 42
(32) WL_OFF# 13 14 41 42
RB751V_SOD323 15 16 43 44 (MINI1_LED#)
15 16 43 44
(18) PCI_PIRQH# 17 17 18 18 W=40mils +5VS 45 45 46 46
+3VS W=40mils 19 19 20 20 PCI_PIRQG# (18) 47 47 48 48
S_YIN 21 22 S_CIN 49 50
(34) S_YIN 21 22 S_CIN (34) 49 50
23 23 24 24 W=40mils +3VALW 51 51 52 52
CLK_PCI_MINI 25 26
(14) CLK_PCI_MINI 25 26 PCI_RST# (18,24,26,29,30)
W=40mils

G1
G2
G3
G3
27 27 28 28 +3VS
PCI_REQ#1 29 30 PCI_GNT#1
(18) PCI_REQ#1 29 30 PCI_GNT#1 (18)
31 32 FOX_AS0B226-S99N-7F

53
54
55
56
PCI_AD31 31 32 MINI1@
33 33 34 34 MINI_PME# (18,26,32)
2 PCI_AD29 WLAN_BT_CLK 2
35 35 36 36 WLAN_BT_CLK (34)
37 38 PCI_AD30
PCI_AD27 37 38
39 39 40 40
PCI_AD25 41 42 PCI_AD28 +3VS +1.5VS +3VALW
WLAN_BT_DATA 41 42 PCI_AD26
(34) WLAN_BT_DATA 43 43 44 44
45 46 PCI_AD24
(18,24,26,30) PCI_CBE#3 45 46
CLK_PCI_MINI PCI_AD23 47 48 MINI_IDSEL1 1 2 R598 PCI_AD18 1 1 1 1 1 1
47 48 100_0402_5% C450 C420 C436 C421 C429 C386
49 49 50 50
PCI_AD21 51 52 PCI_AD22 MINI2@ MINI2@ MINI2@ MINI2@ MINI2@ MINI2@
51 52
1

PCI_AD19 53 54 PCI_AD20 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

R241 53 54 2 2 2 2 2 2
55 55 56 56 PCI_PAR (18,24,26,30)
PCI_AD17 57 58 PCI_AD18
@ 10_0402_5% PCI_CBE#2 57 58 PCI_AD16
(18,24,26,30) PCI_CBE#2 59 59 60 60
PCI _IRDY# 61 62 JP30
(18,24,26,30) PCI_IRDY#
2

61 62 PCI_FRAME# ICH_PCIE_WAKE#
1 63 63 64 64 PCI_FRAME# (18,24,26,30) 1 1 2 2 +3VS
C395 65 66 PCI_TRDY# WLAN_BT_DATA 3 4
(20,26,31) PM_CLKRUN# 65 66 PCI_TRDY# (18,24,26,30) 3 4
PCI_SERR# 67 68 PCI_STOP# WLAN_BT_CLK 5 6 +1.5VS
PCI_STOP# (18,24,26,30)
@ 10P_0402_50V8K (18,24,26) PCI_SERR# 69
67 68
70 (14) MINI2_CLKREQ# 7
5 6
8 +UIM_PWR +UIM_PWR
2 PCI_PERR# 69 70 PCI_DEVSEL# 7 8 UIM_DATA
(18,24,26,30) PCI_PERR# 71 71 72 72 PCI_DEVSEL# (18,24,26,30) 9 9 10 10
PCI_CBE#1 73 74 11 12 UIM_CLK
(18,24,26,30) PCI_CBE#1 73 74 (14) CLK_PCIE_MINI2# 11 12
PCI_AD14 75 76 PCI_AD15 13 14 UIM_RESET
75 76 (14) CLK_PCIE_MINI2 13 14
77 78 PCI_AD13 15 16 UIM_VPP
PCI_AD12 77 78 PCI_AD11 15 16
79 79 80 80
PCI_AD10 81 82
81 82 PCI_AD9
83 83 84 84 17 17 18 18
PCI_AD8 85 86 PCI_CBE#0 19 20 MINI2_OFF#
85 86 PCI_CBE#0 (18,24,26,30) 19 20 MINI2_OFF# (32)
PCI_AD7 87 88 21 22 PLT_RST_BUF#
87 88 PCI_AD6 21 22
89 89 90 90 (20) PCIE_PTX_C_IRX_N2 23 23 24 24 +3VALW
PCI_AD5 91 92 PCI_AD4 25 26
91 92 (20) PCIE_PTX_C_IRX_P2 25 26
CVBS_IN 93 94 PCI_AD2 27 28
(34) CVBS_IN 93 94 27 28
PCI_AD3 95 96 PCI_AD0 29 30 ICH_SMBCLK
95 96 29 30 ICH_SMBDATA
+5VS W=40mils 97 97 98 98 TV_THERM# (32,47) (20) PCIE_ITX_C_PRX_N2 31 31 32 32
3 PCI_AD1 3
99 99 100 100 (20) PCIE_ITX_C_PRX_P2 33 33 34 34
101 101 102 102 35 35 36 36 USB20_N7 (20)
103 103 104 104 37 37 38 38 USB20_P7 (20)
105 105 106 106 +3VS 39 39 40 40
107 108 41 42 (WWAN_LED#)
107 108 41 42
109 109 110 110 2005/1101 43 43 44 44
111 112 AUDIO_INR Vcc 3.3V +/- 8% 45 46 JP43
111 112 AUDIO_INR (34) 45 46
113 114 47 48 +UIM_PWR +UIM_PWR
113 114 Peak Icc 2750mA 47 48 UIM_RESET 1
115 115 116 116 49 49 50 50 2
117 118 51 52 UIM_CLK
117 118 with max supply droop 50mA 51 52 3
119 119 120 120 4
AUDIO_INL Average Icc 1000mA UIM_VPP

G1
G2
G3
G3
(34) AUDIO_INL 121 121 122 122 5
123 124 +3VALW UIM_DATA
+5VS 123 124 6
W=30mils 127 128 W=20mils FOX_AS0B226-S99N-7F

53
54
55
56
127 128 MINI2@ ACES_85201-0605
P-TWO_A53921-A0G16-P

(Change to SP070003200) C836 1 2 1U_0603_10V4Z JP31

@
+UIM_PWR +UIM_PWR 1 2
+5VS UIM_RESET GND1 RES0
3 IAC_SDATA_OUT RES1 4
UIM_CLK 5 6
GND2 3.3V
7 IAC_SYNC GND3 8
1 UIM_VPP 9 10
UIM_DATA IAC_SDATA_IN GND4
2005/09/06 11 IAC_RESET# IAC_BITCLK 12
C895

1000P_0402_50V7K
@

@
22P_0402_50V8J

22P_0402_50V8J
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 1 1 1
JP38 2 U49

GND
GND
GND
GND
GND
GND
GEN@
1 1 1 K1 K4 5
2 2 USB20_N3 (20) 2 2 2 2 ACES_88018-124G
3 USB20_P3 (20) 2

13
14
15
16
17
18
3 A
C847

C846

C845

C843
4 4
4 4 Mini Card Power Rating @
5 5 3 K2 K3 4
GND1 6 Power Primary Power (mA) Auxiliary Power (mA) Connector for MDC Rev1.5
7 NNCD6.8RL-A
GND2 @
Peak Normal Normal 2005/11/02
ACES_88266-05001
GEN@ +3VS 1000 750
+3VALW 330 250 250 (wake enable)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
+1.5VS 500 375 5 (Not wake enable)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI-PCI Slot (WLAN)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 28 of 47
A B C D E
 A B C D E

New Card Power Switch

New Card Socket (Left)
U32
+3VALW_CARD1 +3VS_CARD1 +1.5VS_CARD1
60mils JP34
+3VS 5 3.3Vin1 3.3Vout1 7 +3VS_CARD1 Imax = 0.275A Imax = 1.35A Imax = 0.75A
6 3.3Vin2 3.3Vout2 8
1 GND
1 1 1 1 1 1 (20) USB20_N1 2 USB_D-
40mil C540 C871 C525 C872 C534 C870 3
1 (20) USB20_P1 USB_D+ 1
+3VALW 21 20 +3VALW_CARD1 CP_USB# 4
3.3Vaux_in Aux_out 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z CPUSB#
5 RSV
EXPCARD@ 2 2
0.1U_0402_16V4Z 2
EXPCARD@ 2
0.1U_0402_16V4Z EXPCARD@2 2
0.1U_0402_16V4Z
40mil EXPCARD@ EXPCARD@ EXPCARD@
6 RSV
+1.5VS 18 1.5Vin1 1.5Vout1 16 +1.5VS_CARD1 (14,20,26,28) ICH_SMBCLK 7 SMB_CLK
19 1.5Vin2 1.5Vout2 17 (14,20,26,28) ICH_SMBDATA 8 SMB_DATA
EXPCARD@ 9
EXPCARD@ +1.5VS_CARD1 +1.5V
10 +1.5V
+3VALW R431 1 2 100K_0402_5% CP_USB# 14 CPUSB# (20,26,28) ICH_PCIE_WAKE# 11 WAKE#
R436 1 2 100K_0402_5% CP_PE# 15 23 +3VALW_CARD1 12
SUSP# CPPE# OC# PERST1# +3.3VAUX
(32,33,40,45) SUSP# 4 STBY# 13 PERST#
SYSON 3 22 RCLKEN1 +3VS_CARD1 14
(32,40,46) SYSON SHDN# RCLKEN +3.3V
PCI_RST# 2 9 PERST1# +3VS +3VS 15
(18,24,26,28,30) PCI_RST# SYSRST# PERST# +3.3V
CLKREQ1# 16
CP_PE# CLKREQ#
17

GND
(20) CP_PE#

NC1
NC2
NC3
NC4
NC5
CPPE#

1
+3VS 1 18
(14) CLK_PCIE_CARD# REFCLK-
R685 C873 19
(14) CLK_PCIE_CARD REFCLK+
TPS2231PWPR_PWP24 10K_0402_5% 20

11

1
10
12
13
24
GND

1
EXPCARD@ 0.1U_0402_16V4Z 21
2 EXPCARD@ (20) PCIE_PTX_C_IRX_N1 PERn0
R686 EXPCARD@ 22
(20) PCIE_PTX_C_IRX_P1

2
PERp0

5
10K_0402_5% U50 23
CLKREQ1# GND
2 24

G Vcc
B (20) PCIE_ITX_C_PRX_N1 PETn0
EXPCARD@ 4 (20) PCIE_ITX_C_PRX_P1 25
EXP_CLKREQ# (14)

2
Y PETp0
1 A 26 GND

1
D NC7SZ32P5X_NL_SC70-5 EXPCARD@ 27

3
RCLKEN1 2 Q36 GND
28 GND
G 2N7002_SOT23
+3VS +3VALW +1.5VS S EXPCARD@ TYCO_1759056-1

3
EXPCARD@

C524
1
C541
1
C523
1 (NEW)
2 2
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
EXPCARD@ 2 EXPCARD@2 2
EXPCARD@

USB CONN. 1 & 2

+USB_VCCA +USB_VCCA

+USB_VCCA
W=80mils +USB_VCCA
W=80mils
1 1
1 1
+ C651 C644 + C681 C689

150U_D_6.3VM 470P_0402_50V7K 150U_D_6.3VM 470P_0402_50V7K

2 2 2 2
2005/09/06 2005/09/06
JP5 JP4

USB20_N0 1 USB20_N2 1
(20) USB20_N0 2 (20) USB20_N2 2
USB20_P0 USB20_P2
(20) USB20_P0 3 (20) USB20_P2 3
3 4 4 3
SUYIN_020173MR004S312ZL SUYIN_020173MR004S312ZL
+3VALW

+5VALW ECQ60 ECQ60

1

+USB_VCCA
U39
1 8 R533
GND OUT 100K_0402_5%
2 IN OUT 7
3 6
2

IN OUT R534
1 4 EN# FLG 5
C668 10K_0402_5%
G528_SO8 1 2 USB_OC#0 (20)
4.7U_0805_10V4Z 1
2 C642
D29 D28
USB_EN# 0.1U_0402_16V4Z 1 4 +USB_VCCA 1 4 +USB_VCCA
(32,34) USB_EN# 2 GND VCC GND VCC

USB20_P0 2 3 USB20_N0 USB20_P2 2 3 USB20_N2

I/O I/O I/O I/O
@ PRTR5V0U2X_SOT143 @ PRTR5V0U2X_SOT143

SUYIN_020173MR004G533ZR_4P
SUYIN_020173MR004G533ZR_4P

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NEW CARD SOCKET
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. HBL51 LA-3081P
Date: Thursday, November 10, 2005 Sheet 29 of 47
A B C D E
 A B C D E

+3VS +2.5VS_1394 +3VS

2005/10/20
U14
1 1 1 1 1 1 1 1 1 A0 VCC 8
C461 C454 C463 C402 C462 C414 C438 C396 2 7
A1 WP EECK
3 A2 SCL 6

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 4 5 EEDI
2 2 2 2 2 2 2 2 GND SDA R253
6311S@ 6311S@ 6311S@ 6311S@ 6311S@ 6311S@ 6311S@ 6311S@
AT24C02N-10SU-2.7_SO8 510_0402_5%
@ @

2
EECK and EEDI is pull high internal
External pull high circuit is unnecessary
1 +2.5VS_1394 +3VS 1

20mils L27
6311S@ MBK1608301YZF_0603 2005/11/01
+1394_PLLVDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2 +3VS
1 1 1 1
C422 C448 C403 C447 When use external EEPROM
4.7U_0805_10V4Z
6311S@
Populate U14, R246, R253

111

122
110
U15 2 2 2 2 Un-populate R261

46
30
21

99
36
17

87
86
73
72
62
59
6311S@ 6311S@ 6311S@

5
0.1U_0402_16V4Z

VDD4
VDD3
VDD2
VDD1
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1

PVA5
PVA4
PVA3
PVA2
PVA1
PVA0
+3VS

PCI_AD31 94
VT6311S EECS 26
27
EECS R261 1
6311S@
2 4.7K_0402_5%

PCI_AD30 AD31 EEDO EEDI 2005/11/01

PCI_AD29
95
96
AD30
AD29
EEPROM SDA/EEDI
SCL/EECK
28
29 EECK
PCI_AD[0..31] PCI_AD28 97 6311S@
(18,24,26,28) PCI_AD[0..31] PCI_AD27 AD28 C391 1 1U_0603_10V4Z
98 AD27 PHYRST# 55 2
PCI_AD26 101 81 R279 1 2 @ 4.7K_0402_5% +3VS
PCI_AD25 AD26 BJT_CTL I2CEEN R246 1
102 AD25 I2CEN 43 2 @ 4.7K_0402_5% +3VS
PCI_AD24 103 32 R257 1 2 6311S@ 4.7K_0402_5%
PCI_AD23 AD24 PWRDET C407 1 2 0.1U_0402_16V4Z
PCI_AD22
106
107
AD23
AD22
others REG_FB 84 REG_FB 6311S@

3
PCI_AD21 109 2005/11/01 E
PCI_AD20 AD21 REG_OUT REG_OUT Q35
113 AD20 REG_OUT 85 2
PCI_AD19 114 C398 B 2SB1197K_SOT23
PCI_AD18 AD19 R227 1 C
115 60 2 6311S@ 1K_0402_5% 10P_0402_50V8K @

1
PCI_AD17 AD18 XCPS XREXT R235 1
116 AD17 XREXT 63 2 6311S@ 6.19K_0603_1% 1 2 6311S@
2 PCI_AD16 C399 1 2
117 AD16 10mils 2 6311S@ 47P_0402_50V8J

2
PCI_AD15 2 57 1394_XI Y2 REG_FB +2.5VS_1394
PCI_AD14 AD15 XI 6311S@
PCI_AD13
3
4
AD14
AD13
OSCILLATOR XO 58 1394_XO 24.576MHZ_16P_X8A024576FG1H When use external BJT
PCI_AD12 7 Populate Q35, R279

1
PCI_AD11 AD12 TPB0-
8 AD11 XTPB0M 67 1 2 6311S@
PCI_AD10 9 68 TPB0+
PCI_AD9 AD10 XTPB0P TPA0- C401
PCI_AD8
10
11
AD9
AD8
PHY PORT0 XTPA0M
XTPA0P
69
70 TPA0+ 10P_0402_50V8K
IDSEL:PCI_AD16 PCI_AD7 14 71 TPBIAS0
PCI_AD6 15
AD7
AD6
PCI I/F XTPBIAS0
PCI_AD16 1 2 1394_IDSEL PCI_AD5 16 74
R341 6311S@ 100_0402_5% PCI_AD4 AD5 XTPB1M
18 AD4 XTPB1P 75
PCI_AD3
PCI_AD2
19
20
AD3
AD2
PHY PORT1XTPA1M
XTPA1P
76
77
PCI_AD1 24 78
PCI_AD0 AD1 XTPBIAS1
25 AD0
(18,24,26,28) PCI_CBE#3 104 CBE3# NC17 83
(18,24,26,28) PCI_CBE#2 119 CBE2# NC16 82
(18,24,26,28) PCI_CBE#1 1 CBE1# NC15 64
(18,24,26,28) PCI_CBE#0 12 CBE0# NC14 54
PCI_STOP# 125 53
(18,24,26,28) PCI_STOP# STOP# NC13
PCI_PERR# 127 52
(18,24,26,28) PCI_PERR# PERR# NC12
PCI_PAR 128 51
(18,24,26,28) PCI_PAR PAR NC11
PCI_PIRQE# 88 50
(18) PCI_PIRQE# INTA# NC10
(18,24,26,28,29) PCI_RST# 89 PCIRST# NC9 49
CLK_PCI_1394 90 48
(14) CLK_PCI_1394 PCICLK NC8
PCI_GNT#0 92 45
(18) PCI_GNT#0 GNT# NC7
PCI_REQ#0 93 44
(18) PCI_REQ#0 REQ# NC6
1394_IDSEL 105 42
IDSEL NC5
34 PME# NC4 41
PCI _IRDY# 121 40
3 (18,24,26,28) PCI_IRDY# IRDY# NC3 3
PCI_TRDY# 123 39
(18,24,26,28) PCI_TRDY# TRDY# NC2
PCI_DEVSEL# 124 37
(18,24,26,28) PCI_DEVSEL# DEVSEL# NC1
PCI_FRAME# 120 35
(18,24,26,28) PCI_FRAME# FRAME# NC0
GNDARX1

GNDARX2
GNDATX1

GNDATX2

15mils
GND19
GND18
GND17
GND16
GND15
GND10
GND9
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1
GND0

1
54.9_0402_1% C445
VT6311S_LQFP128 R293 R309 0.33U_0603_10V7K
66
65
80
79
118
112
108
100
91
61
56
47
38
33
31
23
22
6
13
126

6311S@ 54.9_0402_1% 6311S@

6311S@ 6311S@ 2

2
TPBIAS0 JP29
TPA0+ 4
CLK_PCI_1394 TPA0- 4
3 3 6 6
TPB0+ 2 5
2 5
1

TPB0- 1
R319 1

1
@ 10_0402_5% FOX_UV31413-4R1-TR
R275 R289 6311S@
54.9_0402_1% 6311S@ 54.9_0402_1%
(ECQ60)
2

1 6311S@
C456

2
@ 10P_0402_50V8K

1
2
1
C434 R276
6311S@ 4.99K_0402_1%
270P_0402_50V7K 6311S@
2

2
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IEEE1394 VIA VT6311S
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 30 of 47
A B C D E
SUPER I/O SMsC LPC47N207
+3VS

0.1U_0402_16V4Z

1 1 1
C786 C817 C818
FIR@ FIR@ FIR@
0.1U_0402_16V4Z
2 2 2

0.1U_0402_16V4Z

+3VALW

+3VS +3VS

+3VS

17
31
42
60

48
5
U47

24
19
10

1
U31

3.3V
3.3V
3.3V
3.3V
3.3V

VTR
Base I/O Address R441

VSB
VDD
VDD
VDD
LPC_AD0 64 0 = 02Eh 4.7K_0402_5%
(19,32) LPC_AD0 LAD0 +3VS
LPC_AD1 @
(19,32) LPC_AD1
LPC_AD2
2 LAD1 GPIO10 27
LPC_AD0
* 1 = 04Eh
(19,32) LPC_AD2 4 28 26 28

2
LPC_AD3 LAD2 GPIO11 LPC_AD1 LAD0 LPCPD# SUS_STAT# (20,33)
(19,32) LPC_AD3 7 LAD3 GPIO12/IO_SMI# 30 1 2 23 LAD1 TESTB1/BADD 9
32 R603 FIR@ 10K_0402_5% LPC_AD2 20 8 R437 1 2 @ 0_0402_5%
GPIO13/IRQIN1 LAD2 TEST1

1
33 1 2 LPC_AD3 17
GPIO14/IRQIN2 R599 FIR@ 10K_0402_5% LAD3 TPM_XTALO R444
10 LPC_CLK_33 GPIO15 34 XTALO 14
12 35 13 TPM_XTALI 4.7K_0402_5%
LPC_DRQ#0 LDRQ1# GPIO16 TPM XTALI @
(19) LPC_DRQ#0 24 LDRQ0# GPIO17 36
LPC_FRAME# CLK_PCI_TPM SLB 9635 TT 1.1

GPIO
(19,32) LPC_FRAME# 14 38 (14) CLK_PCI_TPM 21

2
PM_CLKRUN# LFRAME# GPIO30 LPC_FRAME# LCLK

LPC I/F
(20,26,28) PM_CLKRUN# 16 CLKRUN# GPIO31 39 22 LFRAME# GPIO2 2
SERIRQ 19 40 16 6
(20,24,32) SERIRQ SERIRQ GPIO32 (17,18,28) PLT_RST_BUF# LRESET# GPIO
CLK_PCI_SIO 21 41 SERIRQ 27
(14) CLK_PCI_SIO PCI_CLK GPIO33 SERIRQ
PLT_RST# 22 43 PM_CLKRUN# 15
(6,18,20,23,26,32) PLT_RST# PCIRST# GPIO34 CLKRUN#
CLK_14M_SIO 23 44 +3VS R432 1 2 @ 4.7K_0402_5% 7 1
(14) CLK_14M_SIO SIO_14M GPIO35 PP NC
1 2 SIO_PD# 25 46 3
+3VS R602 1 FIR@ 210K_0402_5% SIO_PME# LPCPD# GPIO36 NC
47 61 12

GND
GND
GND
GND
+3VS R595 FIR@ 10K_0402_5% IO_PME# GPIO37 NC

SLB-9635-TT-1.2_TSSOP28

4
11
18
25
@
C551
63 52 RXD1 CLK_PCI_TPM 18P_0402_50V8J
DLAD0 RXD1 TXD1 TPM_XTALI
SERIAL I/F

1 DLAD1 TXD1 53 1 2

2
3 54 DSR#1 @
DLAD2 DRSR1#

@
10M_0402_5%
6 55 RTS#1 1 2 R439 X2
DLAD3 RTS1#/SYSOPT0

1
CTS#1 R198 FIR@ 10K_0402_5% @ 10_0402_5%
DLPC I/F

CTS1# 56 1 IN NC 2
57 DTR#1 1 2
DTR1#/SYSOPT1 RI#1 R199 FIR@ 10K_0402_5%
9 58 4 3

1
DLPC_CLK_33 RI1# OUT NC

R448
11 59 DCD#1 2
DLDRQ1# DCD1# 32.768KHZ_12.5P_1TJS125DJ2A073
13

2
DLFRAME# IRTXOUT C536 @
15 DCLKRUN# IRTX2 49
18 50 IRRX 1 2 @ 15P_0402_50V8J TPM_XTALO 1 2
DSER_IRQ IRRX2 IRMODE R591 FIR@ 1 @
IR

26 DSIO_14M IRMODE/IRRX3 51
10K_0402_5% C552
18P_0402_50V8J
GND0
GND1
GND2
GND3
GND4
GND5

LPC47N207-JN_STQFP64
8
20
29
37
45
62

FIR@

RTS#1
Base I/O Address
CLK_14M_SIO CLK_PCI_SIO * 0 = 02Eh
1 = 04Eh
2

R601 R600
@ 10_0402_5% @ 33_0402_5%
1

2 2
C822 C821 +IR_ANODE
@ 15P_0402_50V8J @ 22P_0402_50V8J
1 1
+3VS 1 FIR@ 2
R195 0_1206_5%
1 1 FIR@ 2
C323 R202 0_1206_5%
FIR@

FIR Module 2
4.7U_0805_10V4Z
W=60mil
Place on the BOT side(near MINIPCI conn.)
IR1
+5VS 1
JP35 +IR_3VS IRED_A IRTXOUT
2 IRED_C TXD 3 T = 12mil
+3VS IRRX 4 5 T = 12mil IRMODE
1 RP42 RXD SD/MODE
2 +3VS 1 FIR@ 2 +IR_3VS 6 VCC MODE 7
RXD1 DCD#1 1 8 R210 W=40mil 8
TXD1 3 RI#1 47_1206_5% GND
4 2 7 1 1
DSR#1 CTS#1 3 6 C357 C356 TFDU6102-TR3_8P
RTS#1 5 DSR#1 FIR@ FIR@
6 4 5 FIR@
CTS#1 10U_0805_10V4Z 0.1U_0402_16V4Z
DTR#1 7 4.7K_1206_8P4R_5% 2 2
RI#1 8 FIR@
DCD#1 9
10
ACES_85201-10051
@

For SW debug use when no seial port

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SIO1036 & FIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 31 of 47
 5 4 3 2 1

+3VALW
KBA[0..19]
KBA[0..19] (33) L29 +3VALW For EC Tools
ADB[0..7] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2+EC_VCCA
ADB[0..7] (33) +3VALW
1 1 C416 1 1 2 2 FBM-L11-160808-800LMT_0603 20mil
C473 1 JP26
C453 C467 C491 C478 KSI[0..7]
1000P_0402_50V7K 1000P_0402_50V7K C423
20mil KSI[0..7] (33,34) 1 1
E51_RXD
1 1 2 2
L28 2 2 2 2 1 1 C496 C484 KSO[0..15] E51_TXD
KSO[0..15] (33) 3 3

ECAGND
ECAGND 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z
1 2 4 4
FBM-L11-160808-800LMT_0603 20mil 0.1U_0402_16V4Z 1U_0603_10V4Z
2 2 @ ACES_85205-0400

123
136
157
166

161

159
D D

16
34
45

95

96
U20
LPC_AD0 15

VCCA
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AGND

BATGND
VCCBAT
(19,31) LPC_AD0 LAD0
C497 LPC_AD1 14 49 KSO0
(19,31) LPC_AD1 LAD1 GPOK0/KSO0
@ 22P_0402_50V8J LPC_AD2 13 50 KSO1 Analog Board ID definition, SKU ID definition,
(19,31) LPC_AD2 LAD2 GPOK1/KSO1
2 1 R402 2 1 @ 33_0402_5% LPC_AD3 10 51 KSO2
(19,31) LPC_AD3 LAD3 GPOK2/KSO2 Please see page 3. Please see page 3.
KSO3
(19,31) LPC_FRAME# 9 LFRAME# LPC Interface GPOK3/KSO3 52
KSO4
(6,18,20,23,26,31) PLT_RST# 165 LRST#/GPIO2C GPOK4/KSO4 53

ENE-KB910-B4
18 56 KSO5
(14) CLK_PCI_LPC LCLK GPOK5/KSO5
7 57 KSO6 +3VALW +3VALW
(20,24,31) SERIRQ SERIRQ GPOK6/KSO6 KSO7
(38) DSP_WP# 25 CLKRUN#/GPIO0C * GPOK7/KSO7 58
24 59 KSO8
(34) 3G_LED# LPCPD#/GPIO0B * GPOK8/KSO8

2
+3VALW 60 KSO9
FR D# GPOK9/KSO9 KSO10 R273 R312
(33) FRD# 150 RD# GPOK10/KSO10 61
FWR# KSO11 100K_0402_5% 100K_0402_5%

Internal Keyboard
(33) FWR# 151 WR# GPOK11/KSO11 64 Ra Rc
2

FSEL# 173 65 KSO12

(33) FSEL# MEMCS# GPOK12/KSO12
R378 SELIO# 152 66 KSO13

1
10K_0402_5% ADB0 IOCS# GPOK13/KSO13 KSO14 AD_BID0 SKU_ID
138 D0 GPOK14/KSO14 67
ADB1 139 68 KSO15
D1 GPOK15/KSO15

2
ADB2 140 153 KSO16 1 1
KSO16 (34)
1

ADB3 D2 GPOK16/KSO16 KSO17 R272 C417 C458

(18,26,28) MINI_PME# 141 D3 GPOK17/KSO17 154 KSO17 (34)
ADB4 144 Rb Rd
EC_PME# +3VALW ADB5 D4 KSI0 8.2K_0402_5% 0.1U_0402_16V4Z
(18,26,28) LAN_PME# 145 D5 GPIK0/KSI0 71
2 2

X-BUS Interface
ADB6 146 72 KSI1 0.1U_0402_16V4Z

1
D6 GPIK1/KSI1
(18,26,28) PCI_PME# 1 2 3GSW_EN# ADB7 147 D7 GPIK2/KSI2 73 KSI2
R706 100K_0402_5% KBA0 124 74 KSI3
A0 GPIK3/KSI3
1 2 BTSW_EN# KBA1 125 A1/XIOP_TP GPIK4/KSI4 77 KSI4 R168 change to 8.2K (GM@)
R369 100K_0402_5% KBA2 126 78 KSI5
A2 GPIK5/KSI5
1 2 WLSW_EN# KBA3 127 A3 GPIK6/KSI6 79 KSI6
R403 100K_0402_5% KBA4 128 80 KSI7
KBA5 A4/DMRP_TP GPIK7/KSI7
131 A5/EMWB_TP
+3VALW 1 2 TV_BTN# KBA6 132 32 INVT_PWM
C A6 GPOW0/PWM0 INVT_PWM (15) C
R708 100K_0402_5% KBA7 133 33 BEEP#
A7 GPOW1/PWM1 BEEP# (36)
1 2 MUSIC_BTN# KBA8 143 A8 FAN2PWM/GPOW2/PWM2 36 MUTE_WOOFER# (37)
2

R709 100K_0402_5% KBA9 142 37 ACOFF

A9 GPOW3/PWM3 ACOFF (41,43)
R337 1 2 MOVIE_BTN# KBA10 135 A10 Pulse Width GPOW4/PWM4 38 USB_EN# (29,34)
10K_0402_5% R710 100K_0402_5% KBA11 134 39 EC_ON
A11 GPOW5/PWM5 EC_ON (35)
KBA12 130 40 EC_LID_OUT#
A12 GPOW6/PWM6 EC_LID_OUT# (20)
KBA13 129 43 EC_MUTE
EC_MUTE (37)
1

D12 KBA14 A13 FAN1PWM/GPOW7/PWM7

121 A14
KBA15 120 2 ON/OFF
A15 GPWU0 ON/OFF (35)
1 2 EC_RCIRRX KBA16 113 26
(34,37) RCIRRX A16 GPWU1 ACIN (20,45) +3VS
KBA17 112 29 5WAY_BTN R296
KBA18 A17 GPWU2 PM_SLP_S3# 5WAY_BTN (34) 100K_0402_5%
RB751V_SOD323 104 A18 GPWU3 30 PM_SLP_S3# (20)
KBA19 103 Wake Up Pin 44 PM_SLP_S5# TV_THERM# 2 1
A19 GPWU4 PM_SLP_S5# (20)
+5VS TV_BTN# 108 76 EC_RCIRRX
(34) TV_BTN# A20/GPIO23 GPWU5
RP14 +3VALW 2 1 105 172 EC_PME#
KB_CLK R271 100K_0402_5% E51CS#/GPIO20/ISPEN TIN1/GPWU6 FAN_SPEED2
1 8 TIN2/FANFB2/GPWU7 176 FAN_SPEED2 (39)
2 7 KB_DATA KB_CLK 110 2 1 ECAGND
PS_CLK KB_DATA PSCLK1 BATT_TEMP C459 0.01U_0402_16V7K
3 6 111 PSDAT1 GPIAD0/AD0 81 BATT_TEMP (44)
4 5 PS_DATA PS_CLK 114 82 SKU_ID
PS_DATA PSCLK2 GPIAD1/AD1 BATT_OVP
4.7K_1206_8P4R_5% TP_CLK
115 PSDAT2PS2 Interface GPIAD2/AD2 83
MOVIE_BTN#
BATT_OVP (43)
R405
(35) TP_CLK 116 PSCLK3 GPIAD3/AD3 84 MOVIE_BTN# (34)
+3VALW TP_DATA 117 Analog To Digital 87 MUSIC_BTN# 100K_0402_5%
(35) TP_DATA PSDAT3 GPIAD4/AD4 MUSIC_BTN# (34)
RP15 88 TV_THERM# 5WAY_BTN 2 1
GPIAD5/AD5 TV_THERM# (28,47)
1 8 EC_SMB_CK1 163 89 AD_BID0
(33,38,44) EC_SMB_CK1 SCL1 GPIAD6/AD6
2 7 FR D# EC_SMB_DA1 164 90
(33,38,44) EC_SMB_DA1 SDA1 GPIAD7/AD7 POUT (47)
3 6 SELIO# EC_SMB_CK2 169 SMBus
(4) EC_SMB_CK2 SCL2
4 5 FSEL# EC_SMB_DA2 170 99 DAC_BRIG
(4) EC_SMB_DA2 SDA2 GPODA0/DA0 DAC_BRIG (15)
100 EN_DFAN2 C RY1 C RY2
GPODA1/DA1 EN_DFAN2 (39)
10K_1206_8P4R_5% EMPWR_BTN# 8 101 IR EF
(34) EMPWR_BTN# GPIO04 GPODA2/DA2 IREF (43)
+3VALW EC_SCI# 20 102 EN_DFAN1 1 1
(20) EC_SCI# GPIO07 GPODA3/DA3 EN_DFAN1 (39)
RP22 E-MAIL_BTN# 21 Digital To Analog 1 C471 C470
(34) E-MAIL_BTN# GPIO08 GPODA4/DA4 WL_OFF# (28)

4
1 8 IE_BTN# IE_BTN# 22 42
B (34) IE_BTN# GPIO09 GPODA5/DA5 MINI1_OFF# (28) B
2 7 EMPWR_BTN# ENBKL 27 47 10P_0402_50V8K 10P_0402_50V8K

IN

OUT
(8) ENBKL GPIO0D GPODA6/DA6 MINI2_OFF# (28) 2 2
3 6 E-MAIL_BTN# BKOFF# 28 174 EC_PWROK
(15) BKOFF# GPIO0E GPODA7/DA7 EC_PWROK (35)
4 5 USER_BTN# FSTCHG 48
(43) FSTCHG GPIO10
EC_SMI# 62 85 PW R_LED PWR_LED (34) 2005/11/01 X1
(20) EC_SMI# GPIO13 * GPIO18/XIO8CS#
100K_1206_8P4R_5% IDE_LED# PWR_SUSP_LED#

NC

NC
(22,23) IDE_LED# 63 GPIO14 86 PWR_SUSP_LED# (34)
USER_BTN# 69 * GPIO19/XIO9CS# 91 BATT_GRN_LED#
+3VS (34) USER_BTN# GPIO15 *GPIO1A/XIOACS# BATT_GRN_LED# (34)
70 GPIO 92 BATT_AMB_LED# BATT_AMB_LED# (34) 2005/11/01
(20) EC_SWI# * GPIO1B/XIOBCS#

3
GPIO16 WL_LED#
(34) ARCADE# 75 GPIO17 Expanded I/O * GPIO1C/XIOCCS# 93 WL_LED# (34)
1 2 5IN1_LED# (34) 3GSW_EN#
3GSW_EN# 109 GPIO24 94 BT_LED# BT_LED# (34)
R357 10K_0402_5% LID_SW# 118 * GPIO1D/XIODCS# 97 E-MAIL_LED#
(35) LID_SW# GPIO25 E-MAIL_LED# (34)
BT_ON# 119 * GPIO1E/XIOECS# 98 MEDIA_LED# MEDIA_LED# (34) 32.768KHZ_12.5P_1TJS125DJ2A073
(34) BT_ON# GPIO26 * GPIO1F/XIOFCS#
SYSON 148
(29,40,46) SYSON GPIO27
SUSP# 149 171 FAN_SPEED1 Change P/N SJ100001V00
+5VALW (29,33,40,45) SUSP# GPIO28 GPIO2E/TOUT1/FANFB1 FAN_SPEED1 (39)
VR_ON 155 12 DPLL_TP
(47) VR_ON GPIO29 DPLL_TP/GPIO06/FANFB3
RP19 156 FANTEST_TP/GPIO05/FAN3PWM 11 TEST_TP
(24) 5IN1_LED# GPIO2A
1 8 EC_SMB_CK1 BTSW_EN# 162
(34) BTSW_EN# GPIO2B
2 7 EC_SMB_DA1 PBTN_OUT# 168 175 EC_THERM#
(20) PBTN_OUT# GPIO2D
3 6 EC_SMB_CK2 Timer PinTOUT2/GPIO2F EC_THERM# (20)
4 5 EC_SMB_DA2 55 3
C492 0.1U_0402_16V4Z CAPS_LED# FnLock#/GPIO12 * E51IT0/GPIO00 WLSW_EN# EC_RSMRST# (20)
(34) CAPS_LED# 54 CapLock#/GPIO011 * E51IT1/GPIO01 4 WLSW_EN# (34)
4.7K_1206_8P4R_5% 2 1 NUM_LED# 23 106 E51_RXD 1 2 EAPD
(34) NUM_LED# NumLock#/GPIO0A * E51RXD/GPIO21/ISPCLK EAPD (36)
(19) SATA_LED# SATA_LED# 41 107 E51_TXD R270 0_0402_5%
+5VS ScrollLock#/GPIO0F * E51TXD/GPIO22/ISPDAT
+3VALW 2 1 19 ECRST# MISC 1 2 HD_EAPD# (36)
R409 47K_0402_5% 5 158 C RY2 R793 @ 0_0402_5%
TP_CLK (19) EC_GA20 GA20/GPIO02 XCLKI C RY1
2 1 (19) EC_KBRST# 6 KBRST#/GPIO03 XCLKO 160
4.7K_0402_5% R269 31 2005/11/01
GND
GND
GND
GND
GND
GND

ECSCI#
2 1 TP_DATA
4.7K_0402_5% R268
KB910Q B4_LQFP176 +3VS
17
35
46
122
137
167

+3VALW R260
KB910 C1 VERSION 100K_0402_5%
A KBA1 ENBKL EAPD A
2 1 1 2 2 1
1K_0402_5% R267 R404 100K_0402_5%
2 1 KBA4 1 2 DPLL_TP @
1K_0402_5% R266 R401 1K_0402_5%
2 1 KBA5 1 2 TEST_TP
1K_0402_5% R265 R400 1K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB910
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 32 of 47
5 4 3 2 1
 +3VALW +3VALW
C526

1
1 2 R434
100K_0402_5%
SUSP# (29,32,40,45)
0.1U_0402_16V4Z

2
G
5
U29

2
2 1 3

G Vcc
B EC_FLASH# (20)
FWE# 4

S
Y
A 1
Q18
NC7SZ32P5X_NL_SC70-5 2N7002_SOT23

3
FWR# (32)

Check PCB Footprint

INT_KBD Conn.
KSI[0..7]
KSI[0..7] (32,34)
KSO[0..15]
KSO[0..15] (32)
+5VALW +5VALW

1
C503 1 2 0.1U_0402_16V4Z
R413

100K_0402_5%
U24 (Right) JP8

2
8 1 KSO15
VCC A0 KSO14 24
7 WP A1 2 23
6 3 KSO13
(32,38,44) EC_SMB_CK1 SCL A2 22
5 4 KSO12
(32,38,44) EC_SMB_DA1 SDA GND 21
KSI0
AT24C16N10SC-2.7_SO8 KSO11 20
KSO10 19
KSI1 18
17
1

KSI2
R398 KSO9 16
KSI3 15
100K_0402_5% KSO8 14
KSO7 13
2

KSO6 12
KSO5 11
KSO4 10
KSO3 9
KSI4 8
KSO2 7
KSO1 6
KSO0 5
KSI5 4
KSI6 3
KSI7 2
2005/11/03 1
(Left)
ACES_85201-24051

INT_FLASH_EN# C490 1 2 @ 0.1U_0402_16V4Z

+3VALW
R391 1 2 100K_0402_5%
+3VALW

1
SB_INT_FLASH_SEL# (20) @

OE#
5

FSEL# 2 4 1 2 INT_FSEL#
(32) FSEL# A Y R390 @ 22_0402_5%
P

OE#

1
2 4 INT_FLASH_SEL
(20,31) SUS_STAT# A Y R388
3
G

U30 @
U21 10K_0402_5%
3

SN74AHCT1G125DCKR_SC70-5 @

2
SN74AHCT1G125DCKR_SC70-5
@ +3VALW KSO15 C759 1 2 @ 100P_0402_50V8J KSO7 C771 1 2 @ 100P_0402_50V8J

1 2 KSO14 C760 1 2 @ 100P_0402_50V8J KSO6 C772 1 2 @ 100P_0402_50V8J

R418 0_0402_5%
KSO13 C761 1 2 @ 100P_0402_50V8J KSO5 C773 1 2 @ 100P_0402_50V8J

1MB Flash ROM KSO12 C762 1 2 @ 100P_0402_50V8J KSO4 C774 1 2 @ 100P_0402_50V8J

KBA[0..19]
(32) KBA[0..19] KSI0 C763 1 KSO3
2 @ 100P_0402_50V8J C775 1 2 @ 100P_0402_50V8J
ADB[0..7]
(32) ADB[0..7]
+3VALW 1MB ROM Socket KSO11 C764 1 2 @ 100P_0402_50V8J KSI4 C776 1 2 @ 100P_0402_50V8J

U25 KSO10 C765 1 2 @ 100P_0402_50V8J KSO2 C777 1 2 @ 100P_0402_50V8J

KBA0 21 31 JP10 KSI1 C766 1 2 @ 100P_0402_50V8J KSO1 C778 1 2 @ 100P_0402_50V8J

KBA1 A0 VCC0 KBA16 KBA17
20 A1 VCC1 30 1 1 2
KBA2 19 KBA15
KBA3 A2 C499 KBA14 3 4 KSI2 C767 1
18 A3 5 6 2 @ 100P_0402_50V8J KSO0 C779 1 2 @ 100P_0402_50V8J
KBA4 17 25 ADB0 0.1U_0402_16V4Z KBA13 KBA19
KBA5 A4 D0 ADB1 2 KBA12 7 8 KBA10 KSO9 C768 1
16 A5 D1 26 9 10 2 @ 100P_0402_50V8J KSI5 C780 1 2 @ 100P_0402_50V8J
KBA6 15 27 ADB2 KBA11 ADB7
KBA7 A6 D2 ADB3 KBA9 11 12 ADB6 KSI3 C769 1 KSI6
14 A7 D3 28 13 14 2 @ 100P_0402_50V8J C781 1 2 @ 100P_0402_50V8J
KBA8 8 32 ADB4 KBA8 ADB5
KBA9 A8 D4 ADB5 FWE# 15 16 ADB4 KSO8 C770 1 KSI7
7 A9 D5 33 17 18 2 @ 100P_0402_50V8J C782 1 2 @ 100P_0402_50V8J
KBA10 36 34 ADB6 RESET# +3VALW
KBA11 A10 D6 ADB7 INT_FLASH_EN# 19 20
6 A11 D7 35 21 22
KBA12 5 INT_FLASH_SEL
KBA13 A12 KBA18 23 24 ADB3
4 A13 25 26
KBA14 3 10 RESET# 1 2 +3VALW KBA7 ADB2
KBA15 A14 RP# R412 100K_0402_5% KBA6 27 28 ADB1
2 A15 NC 11 29 30
KBA16 1 12 KBA5 ADB0
KBA17 A16 READY/BUSY# KBA4 31 32 FR D#
40 A17 NC0 29 33 34
KBA18 13 38 KBA3
KBA19 A18 NC1 KBA2 35 36 FSEL#
37 A19 37 38
KBA1 KBA0
INT_FSEL# 39 40
22 CE#
FR D# 24 23 @ SUYIN_80065AR-040G2T
(32) FRD# OE# GND0
FWE# 9 39
WE# GND1

SST39VF080-70_TSOP40
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 33 of 47
 1 2 +3VALW
R343 100K_0402_5%
D13
2 ARCADE# (32)
ARCADE_BTN#1
3 51ON#
51ON# (35,41)
To LCM/B Conn. DAN202U_SC70
GEN@ +3VALW
JP11
ARCADE_BTN#
MOVIEBTN# 24
D32
2
MDC Conn. 1
C599
23 TV_BTN# (32)
TVBTN# TVBTN# 1 JP3
MUSICBTN# 22 51ON# 1U_0603_10V4Z
21 3
2
20 1 GND1 RES0 2
DAN202U_SC70 ICH_SDOUT_MDC 3 4 20mil
19 (19) ICH_SDOUT_MDC IAC_SDATA_OUT RES1
GEN@ 5 6
18 GND2 3.3V +3VALW
+5VS (19) ICH_SYNC_MDC ICH_SYNC_MDC 7 8
17 D33 R491 1 IAC_SYNC GND3
16 (19) ICH_AC_SDIN1 2 33_0402_5% 9 IAC_SDATA_IN GND4 10
2 ICH_RST_MDC# 11 12 ICH_BITCLK_MDC
15 MOVIE_BTN# (32) (19) ICH_RST_MDC# IAC_RESET# IAC_BITCLK ICH_BITCLK_MDC (19)
MOVIEBTN# 1 1
14 51ON# C598
13 2005/09/04 3
KSI6

GND
GND
GND
GND
GND
GND
(32,33) KSI6 12 DAN202U_SC70 22P_0402_50V8J
11 GEN@ 2
KSI0 10 D34 ACES_88018-124G
(32,33) KSI0

13
14
15
16
17
18
KSI1 9
(32,33) KSI1 8 2 MUSIC_BTN# (32)
KSI2 MUSICBTN# 1
(32,33) KSI2 7
KSI5 3 51ON# Connector for MDC Rev1.5
(32,33) KSI5 6 +5VS
KSO16
(32) KSO16 5
KSI3 DAN202U_SC70
(32,33) KSI3 4
KSI4 GEN@
(32,33) KSI4 3
KSO17 C555 LED9
(32) KSO17 2
5WAY_BTN GEN@ 2 1
(32) 5WAY_BTN 1 0.1U_0402_16V4Z
ACES_85201-24051 HT-170UYG-DT GRN_0805
GEN@ GEN@ JP37 2005/09/04 JP6
R472 LED3 +5VS
300_0402_5% 1 1
PWR_LED# WLSW_EN# 2 2
+5VS 1 2 2 1 3 3
3 WL_LED#
BTSW_EN# 4 KSO17 4
HT-110UYG_1204 BT_LED# 5 KSI2 5
GRA@ 3GSW_EN# 6 KSI5 6
LED8 3G_LED# 7 KSO16 7
8 KSI3 8
2 1 9 9
KSI4
HT-170UD_0805 10 10
GEN@ ACES_85201-10051 ACES_85201-10051
R704 LED6 GEN@ GRA@
300_0402_5%
PWR_LED# +5VALW 1 2 2 1 PWR_SUSP_LED# PWR_SUSP_LED# (32)
3

HT-110UD_1204
GRA@ +5VALW
LED10
1

D
2 1
(32) PWR_LED 2
G HT-170UYG-DT GRN_0805 C2 2005/11/01
S Q9 GEN@
3

2N7002_SOT23 R473 LED4 0.1U_0402_16V4Z del c7

300_0402_5%
1 2 2 1 BATT_GRN_LED#
To LED/B Conn.
+5VALW BATT_GRN_LED# (32)
3
+5VS +5VS HT-110UYG_1204
GRA@ +5VS
LED11 JP2
1

2 1 1 1 2 2 +5VALW
R470 R471 PWR_LED# 3 4
HT-170UD_0805 3 4
(32) MEDIA_LED# 5 5 6 6
300_0402_5% 300_0402_5% GEN@ 7 8
(32) CAPS_LED# 7 8
R703 LED5 9 10 USB20_N4
(32) NUM_LED# USB20_N4 (20)
2

300_0402_5% 9 10 USB20_P4
(32) E-MAIL_LED# 11 11 12 12 USB20_P4 (20)
+5VALW 1 2 2 1 BATT_AMB_LED# BATT_AMB_LED# (32) 13 14
(35) ON/OFFBTN# 13 14
3
2

3
2

3 15 16 USB20_N6
(32) E-MAIL_BTN# 15 16 USB20_N6 (20)
LED2 LED1 17 18 USB20_P6
(32) IE_BTN# 17 18 USB20_P6 (20)
HT-110UD_1204 HT-110NBQA_BULE_1204 HT-110UD_1204 19 20
(32) USER_BTN# 19 20
(32) EMPWR_BTN# 21 21 22 22 USB_EN# (29,32)
23 23 24 24
R707 LED7 25 26
(28) CVBS_IN
1

MINI2@ 300_0402_5% 25 26
(28) S_YIN 27 27 28 28 AUDIO_INL (28)
1 2 2 1 29 30

GND
GND
GND
GND
GND
GND
WL_LED# (32) BT_LED# (32) +5VS 3G_LED# (32) (28) S_CIN 29 30 AUDIO_INR (28)
3

94/08/04 HT-110UYG_1204 ACES_88018-304G

31
32
33
34
35
36
MINI2@
BT_SW & 3G_SW
+3VALW
5

2005/09/12
2005/10/17 1 +3VALW
5

1
1

2 R705
2
1
6

100_0805_5%
CIR

1
2 3GSW_EN# 3 CIR@ 09/06:CHANGE P/N to SCR36236000 1
3GSW_EN# (32) 3 R796 C932 C874 Bluetooth Conn.
2

4 WLSW_EN# IR2 100K_0402_5% @

4 WLSW_EN# (32)
6

3 3 4 RCIRRX 0.1U_0402_16V4Z 1U_0603_10V4Z

Vs OUT RCIRRX (32,37)

3
2
S
4 BTSW_EN# SW8 1 2 +BT_VCC
BTSW_EN# (32)
6

2
HSS110_4P GND GND G
Q37
1 (32) BT_ON# 2
SW9 GRA@ C894 TSOP36236TR_4P 1 JP36
5
7

HSS112_7P CIR@ CIR@ C893 SI2301BDS_SOT23

GRA@ 4.7U_0805_10V4Z CIR@ 1
2 1000P_0402_50V7K
D 2
(20) USB20_P5

1
2 3
W=40mils (20) USB20_N5 4
Geneva 2005/09/04 Grapevine +BT_VCC 5
(28) WLAN_BT_DATA 6
1 (28) WLAN_BT_CLK 7
KSO16 KSO17 KSO16 KSO17 C875 C877
8

KSI0 VOL_UP LEFT 4.7U_0805_10V4Z 0.1U_0402_16V4Z ACES_87212-0800

2
KSI1 RIGHT VOL_DOWN
KSI2 PLAY ENTER KSI2 PLAY
KSI3 STOP KSI3 STOP VOL_UP Security Classification Compal Secret Data Compal Electronics, Inc.
KSI4 NEXT KSI4 NEXT VOL_DOWN Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

REV REV ARCADE_TV

LCM / MDC / BT / CIR / LED
KSI5 KSI5 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.2
KSI6 RECORD DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 34 of 47
 A B C D E

Change BATT1 P/N : SP093PA0200 (Panasonic)

SP093MX0000 (MAXELL)
ON/OFF switch
TOP Side +3VALW RTC Battery
2005/11/01
2 1
J2 @ JOPEN
- +

1
2 1 BATT1 +RTCBATT
J1 @ JOPEN +3VALW R8
Bottom Side Power Button Lid Switch 100K_0402_5% 2 1 +RTCBATT

1 1

2
2
Change P/N : SN111000207
R399 45@ RTCBATT
SW1

1
3 1 LID_SW# (32)
100K_0402_5% D30

1
D14 BAS40-04_SOT23

3
2 +RTCVCC
ON/OFF (32)
ON/OFFBTN# 1 4 2
(34) ON/OFFBTN#

2
3 51ON# D3
51ON# (34,41) MPU-101-81_4P @
DAN202U_SC70 PSOT24C_SOT23
CHGRTC
2005/09/04 1

1
C833

0.1U_0402_16V4Z

1
2
2
C495 D15

1000P_0402_50V7K RLZ20A_LL34
1

2
Scroll Up
1
D
EC_ON 2 Q16 SW2
(32) EC_ON
G EVQPLHA15_4P
2

S 2N7002_SOT23 SCRL_U 3 1
3

2 R414 2
4 2 SCRL_R
10K_0402_5%
BTN_R
1

5
6
Scroll Left Scroll Right

3
SW5 SW6 D17
EVQPLHA15_4P EVQPLHA15_4P @
SCRL_L 3 1 SCRL_R 3 1 PSOT24C_SOT23

Power ON Circuit

1
4 2 4 2

5
6

5
6
SCRL_L

+3VS
Scroll Down
SCRL_U
SW7

3
+3VALW +3VALW EVQPLHA15_4P
SCRL_D 3 1
1

2005/11/01 D19
U28A U28B 4 2 @
R420 SN74LVC14APWLE_TSSOP14 PSOT24C_SOT23
14

14

180K_0402_5% SN74LVC14APWLE_TSSOP14

5
6

1
Left Right
P

P
2

1 I O 2 3 I O 4 1 2 SYS_PWROK (6,20)
R789 0_0402_5%
G

+3VALW POWER +3VALW POWER SW3 SW4 SCRL_D

2 For South Bridge EVQPLHA15_4P EVQPLHA15_4P
7

C512 BTN_L 3 1 BTN_R 3 1 BTN_L

1U_0805_25V4Z
2

3
1
4 2 4 2
3 D35 3
RB751V_SOD323 1 2 D18
(32) EC_PWROK

5
6

5
6
R790 @ 0_0402_5% @
PSOT24C_SOT23
1

2005/11/01

1
+3VS

+3VALW +3VALW To TP/B Conn.

1

2005/11/02
R425
U28C U28D JP7
14

14

62K_0402_1% SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14

D36 +5VS 1 BTN_R C168 1 2 @ 100P_0402_50V8J
P

P
2

R779 1 TP_DATA 2
(40) SYS_VS_OFF 2 1 2 5 I O 6 9 I O 8 VS_ON (46) (32) TP_DATA 3
+5VS TP_CLK SCRL_R C169 1 2 @ 100P_0402_50V8J
2 (32) TP_CLK 4
G

33_0402_5%
C521
For +VCCP/+1.05VS 5 SCRL_U C170 1 2 @ 100P_0402_50V8J
7

C176 BTN_R 6
RB751V_SOD323 1 0.1U_0402_16V4Z SCRL_R 7 SCRL_L C158 1
8 2 @ 100P_0402_50V8J
0.1U_0402_16V4Z SCRL_U
SCRL_L 9 SCRL_D C166 1
10 2 @ 100P_0402_50V8J
SCRL_D
BTN_L 11 BTN_L C173 1
12 2 @ 100P_0402_50V8J

ACES_87151-1207 TP_DATA C167 1 2 @ 100P_0402_50V8J

+3VALW
C511
TP_CLK C159 1 2 @ 100P_0402_50V8J
1 2 0.1U_0402_16V4Z +3VALW

U28E U28F
14

14

SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
4 4
P

11 I O 10 13 I O 12
G

G
7

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK, Reset and RTC Circuit, TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 35 of 47
A B C D E
 A B C D E F G H

+VDDA
28.7K for Module Design (VDDA = 4.702)

1
R689 +5VAMP (output = 250 mA)
10K_0402_5% 60mil U34
+5VS L32 1 2 4 VIN VOUT 5 40mil +VDDA
KC FBM-L11-201209-221LMAT_0805

2
1 1 2 DELAY SENSE or ADJ 6 1 4.85V
1 2 L33 1 2 C550 C553 R452
C542 1U_0603_10V4Z KC FBM-L11-201209-221LMAT_0805 7 1 30K_0402_1% C558
ERROR CNOISE

1
10U_0805_10V4Z 10U_0805_10V4Z
R688 2 2
0.1U_0402_16V4Z 2
8 3 1

1
10K_0402_5% SD GND C548
1 SI9182DH-AD_MSOP8 1
R430

1
C527 1 2 1 2
(32) BEEP#

2
1U_0603_10V4Z C535 2
560_0402_5% 1 2 MONO_IN R451
0.1U_0402_16V4Z 10K_0402_1%
1U_0603_10V4Z

2
1
C 1 2
C528 1 R433 Q19
(24) PCM_SPK# 2 1 2 2 R687
1U_0603_10V4Z B
560_0402_5% E 2SC2411K_SC59 2.4K_0402_5%

3
C533 1 R438
(20) SB_SPKR 2 1 2
1U_0603_10V4Z

1
560_0402_5%
D16
R442 RB751V_SOD323
10K_0402_5%

2
HD Audio Codec
+AVDD_AC97
20mil 0.1U_0402_16V4Z +3VS
L34 1 2 0.1U_0402_16V4Z 40mil 1 1 1
+VDDA
FBM-L11-160808-800LMT_0603 1 1 1 C537 C539 C532
C545 C559
2 C549 10U_0805_10V4Z 2
10U_0805_10V4Z 2 2 2

25

38

9
2 2 2 U33
0.1U_0402_16V4Z 0.1U_0402_16V4Z

AVDD1

AVDD2

DVDD1

DVDD2
14 35 AMP_LEFT
LINE2_L FRONT_OUT_L AMP_LEFT (37,38)
15 36 AMP_RIGHT
LINE2_R FRONT_OUT_R AMP_RIGHT (37,38)
16 MIC2_L SURR_OUT_L 39

17 MIC2_R SURR_OUT_R 41

LINE_L 1 2 LINE_C_L 23 45
(37) LINE_L LINE1_L SIDESURR_OUT_L
C556 1U_0603_10V4Z
LINE_R 1 2 LINE_C_R 24 46
(37) LINE_R LINE1_R SIDESURR_OUT_R
C557 1U_0603_10V4Z
1 2 CD_L_RC 18 43
C543 @ 1U_0603_10V4Z CD_L CEN_OUT
1 2 C D_R_RC 20 44
CD_R LFE_OUT MONO_OUT (37)
C546 @ 1U_0603_10V4Z
2005/11/01 1 2 CD_AGND_RC19 C538 1 2 22P_0402_50V8J
C544 @ 1U_0603_10V4Z CD_GND
BIT_CLK 6 ICH_BITCLK_AUDIO (19)
MIC1_L 1 2 MIC1_C_L 21
(37) MIC1_L MIC1_L
C547 1U_0603_10V4Z
MIC1_R 1 2 MIC1_C_R 22 8 R443 1 2 33_0402_5% ICH_AC_SDIN0 (19)
(37) MIC1_R MIC1_R SDATA_IN
C554
1U_0603_10V4Z MONO_IN 12 37
PCBEEP PIN37_VREFO

LINE1_VREFO 29
3 3
(19) ICH_RST_AUDIO# 11 RESET#
LINE2_VREFO 31
(19) ICH_SYNC_AUDIO 10 SYNC 10mil
MIC1_VREFO_L 28 MIC1_VREFO_L
(19) ICH_SDOUT_AUDIO 5 SDATA_OUT
MIC1_VREFO_R 32 MIC1_VREFO_R
(32) EAPD 2 GPIO0
(37) NBA_PLUG 3 GPIO1 MIC2_VREFO 30
J4 13 10mil
SENSE A AC97_VREF
1 1 2 2 34 SENSE B VREF 27
2005/11/01 1
JUMP_43X79 47 40
(32) HD_EAPD# SPDIFI/EAPD JDREF C561

1
J5 @ SPDIF 48 33 10U_0805_10V4Z
(37) SPDIF SPDIFO VAUX R445 2
1 1 2 2
1 4 26 20K_0402_1%
JUMP_43X79 DVSS1 AVSS1
7 DVSS2 AVSS2 42 @
C100
2
@ 100P_0402_25V8K ALC883-LF_LQFP48
2
(37) SPDIF_R 2 1
1 2 R753
R465 0_0603_5% 0_0402_5% DGND AGND

1 2
2005/09/16 (for EMI)
R440 0_0603_5%

1 2
R695 0_0603_5%

4 4

GND GNDA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC883
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 36 of 47
A B C D E F G H
 A B C D E

+5VAMP
SUB@ fo= 725 Hz
BYPASS
BYPASS 1
R460
2
0_0402_5%
C567
1 2
1U_0603_10V4Z
C889 1
SUB@
2 0.68U_0603_10V6K Subwoofer
SUB@ +5VAMP
1 2 U57A

8
C565 TLV2462CDR_SO8

8
0.1U_0402_16V4Z 3 SUB@ R700 R701

P
SUB@ + C890
O 1 2 1 2 1 5

P
+
(36) MONO_OUT 1 2 2 1 R459 1 2 C564 2 -
1K_0402_5% 10K_0402_5%
O 7 2 1 MIX_OUT

G
C560 1U_0603_10V4Z 100K_0402_5% SUB@ SUB@ 6 - 10mil

G
SUB@ SUB@ 1U_0603_10V4Z U57B 0.22U_0603_16V7K

4
SUB@ 2 TLV2462CDR_SO8 SUB@

4
1 C570 SUB@ 1
2 1 SUB@
R461 0.47U_0603_16V4Z
43K_0402_5% 1
SUB@

BYPASS

Fc(high)= 33.8Hz 10mil

+5VAMP

R697 U55 JP20

MIX_OUT 2 1 WOOFER_IN 1 IN VO- 8 W OOFER- 30mil 1
20K_0402_5%
MUTEWOOFER# SUB@ 2
(32) MUTE_WOOFER# 1 2 2 SD# GND 7
R694 10K_0402_5% ACES_85204-0200
SUB@ 3 6 SUB@
VDD SE/BTL#

1
D WOOFER+
4 BYPASS VO+ 5
2 Q24 9
(36) NBA_PLUG GND1
1

1
D G 2N7002_SOT23 2 2
2 Q23 S SUB@ C880 C878 SUB@ R691
(32) EC_MUTE

3
G 2N7002_SOT23 SUB@ SUB@ TPA0211DGN_MSOP8 SUB@
S SUB@ 100K_0402_5%
3

0.1U_0402_16V4Z 1 1 0.47U_0603_16V4Z

2
2 2
C929 2005/11/01
0.47U_0603_16V4Z +5VAMP
2 2
1 2 AMP_LEFT_C-1 C563 C562
(36,38) AMP_LEFT
S/PDIF Out JACK

1
1 2 AMP_RIGHT_C-1 330P_0402_50V7K 330P_0402_50V7K
(36,38) AMP_RIGHT C928 R458 1 1
0.47U_0603_16V4Z
1

10K_0402_5% JP40
R791 R792 VOL_AMP 1

1 2
@ @ HPOUT_L_2 1 2 HPOUT_L_3 2

1
1K_0402_5% 1K_0402_5% (0.65V -> 10dB ) L51 FBM-11-160808-700T_0603 6
+5VAMP R455 R457 HPOUT_R_2 1 2 HPOUT_R_3 3
2

2
W=40mil +5VAMP @ R702 L50 FBM-11-160808-700T_0603

2
5.1K_0402_1% 1.5K_0402_1% +5VAMP 2 1 SPDIF_PLUG# 5
HPF Fc = 338Hz 1 1 47_0603_5% R699 R456 100K_0402_5%

1 2

2
1

D 47_0603_5% 4
C881 C892 R467 SPDIF 7
(36) SPDIF

1
0.1U_0402_16V4Z 4.7U_0805_10V4Z 100K_0402_5% SPDIF_PLUG#2 +5VSPDIF 8

1
2 2 Q20 G 10
R468 2N7002_SOT23 @ S
2

3
100K_0402_5% 9
1 2
U56 SPKL+ 1 2 HPOUT_L_1 ACES_20234-0101

+
10 1 EC_MUTE +5VAMP C891 150U_D_6.3VM GRA@
VDD MUTE EC_MUTE (32) SPKR+ 1 2 HPOUT_R_1

+
15 VDD SHUTDOWN# 2
C882 2 1 0.1U_0402_16V4Z C888 150U_D_6.3VM
9 SPKL-
LOUT-
LINE-IN JACK

3
S
VOL_AMP 7 VOLUME SPKR-
G
ROUT- 16 2 SPDIF_PLUG#
2 1 VOLMAX 8 09/06: SWAP SPKL+ & SPKL- JP41
R690 0_0402_5% VOLMAX SPKL+ Q22
LOUT+ 11 5
3 NBA_PLUG SI2301BDS_SOT23 3
13 SE/BTL# D
AMP_LEFT_C-1 1 2 14 SPKR+ 4

1
C566 1U_0603_10V4Z AMP_LEFT_C ROUT+ L48 FBM-11-160808-700T_0603
6 LIN-
AMP_RIGHT_C-1 1 2 AMP_RIGHT_C 3 LINE_R 1 2 LINE_R_R 3
RIN- (36) LINE_R
C568 1U_0603_10V4Z 5 +5VSPDIF 20mil 6
BYPASS GND +5VAMP LINE_L LINE_L_R
BYPASS 4 BYPASS GND 12 (36) LINE_L 1 2 2
20mil L49 FBM-11-160808-700T_0603 1
1 APA2068KAI-TRL_SOP16 1 1

1
SUYIN_010164FR006G118ZL
C886 R698 C885 C884 GRA@
4.7U_0805_10V4Z 100K_0402_5% 220P_0402_50V7K 220P_0402_50V7K
2 2 2
JP12

2
SPKL+ R462 1 2 0_0603_5% SPK_L+ NBA_PLUG
1 (36) NBA_PLUG
SPKL- R464 1 2 0_0603_5% SPK_L- Q21 2N7002_SOT23
2
1
SPKR+ R466 0_0603_5% SPK_R+ D
1 2 3
SPKR- R469 1 2 0_0603_5% SPK_R- 2 SPDIF_PLUG# DSP_ENABLE#
4 DSP_ENABLE# (38)
G
ACES_85204-0400 S MIC1_VREFO_L MIC1_VREFO_R
MIC JACK
3

1
JP42
Int MIC Conn. R775 R776
5
20mil
2005/09/09
INT_MIC_L
JP44 Speaker Conn. (38) MIC1_DSP_P
INT_MIC_L (38)
2.2K_0402_5% 2.2K_0402_5% 4
1 2005/09/06

2
MIC1_L_1 1 JP13 MIC1_R_1
2 2 15mil (36) MIC1_R 1 2 FBM-11-160808-700T_0603 3
MIC1_R_1 3 1 2 INT_MIC_L L54 6
LINE_R_R 3 1 R777 MIC1_L_1
4 4 2 (36) MIC1_L 1 2 FBM-11-160808-700T_0603 2
LINE_L_R 5 0_0402_5% L35 1
5 ACES_85204-0200
6 6 1 1
HPOUT_R_3 7 SUYIN_010164FR006G118ZL
4 7 C569 C876 4
8 8 MIC1_DSP_N (38) GRA@
HPOUT_L_3 9 220P_0402_50V7K 220P_0402_50V7K
DSP_ENABLE# 9 2 2
10 10
SPDIF_PLUG# 11 11
+5VSPDIF 12 12
SPDIF_R 13
(36) SPDIF_R 13
14 14
(32,34) RCIRRX
+3VALW
15
16
15 Security Classification Compal Secret Data Compal Electronics, Inc.
16 2005/06/20 2006/06/20 Title
Issued Date Deciphered Date
ACES_87213-1600G THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack & Subwoofer
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 37 of 47
A B C D E
 A B C D E

+1.8VS_DSP +1.8VS_DSPA
+1.8VS_DSP U58
+3VS +3VS_DSP
1 VOUT BP 5 1 2 1 2
C896 L52 FBM-L11-160808-800LMT_0603
+5VAMP 2 0.01U_0402_16V7K VP1020@ VP1020@ 1 2
2 GND 1 2 1 1 1
VP1020@ C899 C900 C901 L53 FBM-L11-160808-800LMT_0603
C897 3 4 +5VAMP C898 C902 1 VP1020@ 2 1
1U_0603_10V4Z VIN SHDN# 4.7U_0805_10V4Z 1U_0603_10V4Z 0.1U_0402_16V4Z C904 C905
VP1020@ 1 2 VP1020@ VP1020@1 2
0.1U_0402_16V4Z 2 2
4.7U_0805_10V4Z C903
1
APL5301-18BC-TR_SOT23-5 VP1020@ VP1020@ 4.7U_0805_10V4Z 1U_0603_10V4Z
C906 VP1020@ 2 VP1020@ 1
VP1020@ 2
0.1U_0402_16V4Z
1U_0603_10V4Z VP1020@
VP1020@ 2 closed to Pin37
1 1
+3VS_DSP
+1.8VS_DSPA

VP1020@
closed to Codec
C907 1 2 4.7U_0805_10V4Z U59 GPIO5: High for SHI, Low for EEPROM

33

37

19

35
2

4
INT_MIC_L
INT_MIC_L (37)
MIC1_DSP_P R715 1 2 1 2

VDD_S
NC

NC

VDD_D
V10

V15
(37) MIC1_DSP_P MIC1_VREFO_L
2.2K_0402_5% R716 1K_0402_5% 5 20 VP1020@ R717 1 2 100K_0402_5%
NC GPIO6

2
MIC1_DSP_N VP1020@ VP1020@ 6 21 VP1020@ R718 1 2 100K_0402_5%
(37) MIC1_DSP_N NC GPIO5 @ R719 1 10K_0402_5% R724
GPIO7 17 2 +3VS_DSP
1 2 VP1020@ VP1020@ VP1020@ R720 1 2 10K_0402_5% VP1020@
2.2K_0402_5% R7211 0_0402_5%
2 100_0402_5% C908 2 1 R722 1 2 39 MIC0_P
0.1U_0402_16V4Z
VP1020@
+5VS R726 VP1020@ 1 0.1U_0402_16V4Z 1K_0402_5% 47 VP1020@
2 1 R723 1 2 C910 2 1

1
R748 R749 VP1020@C912 C911 2 R725 1 LINE_OUT C909 100_0402_5%
1 2 40 MIC0_N
1 2 1 2 0.1U_0402_16V4Z 1K_0402_5% 0.1U_0402_16V4Z VP1020@ 1 2
0.012U_0603_25V7K VP1020@ VP1020@
41 16 DSP_EECK C913
1M_0402_5% 1M_0402_5% 2 NC SCL_EE DSP_EEDA 0.039U_0603_16V7K
1 2 SDA_EE 15
8

VP1020@ U61A R727 100_0402_5% 42 VP1020@

VP1020@ VP1020@ VP1020@ VP1020@ VP1020@ NC R728 1
1 2 3 13 2 100K_0402_5%
P

(36,37) AMP_RIGHT IN+ LINEIN_DSP_R1 UART_TX

O 1 2 1U_0603_10V4Z R7291 2 1K_0402_5% C915 2 1 1 2 43 LINE_IN UART_RX 12 VP1020@
C925 2 VP1020@ R7311 2 1K_0402_5% R730 1K_0402_5%
1U_0402_6.3V6K IN-
G

C914 VP1020@ 0.1U_0402_16V4Z 11

VP1020@ NC

VP1020
C917 2 1 0.039U_0603_16V7K 34
4

LM358M_SO8 VP1020@ SW10

SW15 36
VP1020@ +3VS_DSP VP1020@ R732 1 2 10K_0402_5% 30
DSP_RST# PWD#
31 RST#
+5VS 48 VP1020@ C918 1 2 1U_0603_10V4Z
R750 R751 SPK_OUT_P
VP1020@ 3
2 DSP_SMB_CK SPK_OUT_N VP1020@ C919 1 2
1 2 1 2 23 SCL 2 1U_0603_10V4Z
1M_0402_5% 1M_0402_5% LINEIN_DSP_L 1 2 1U_0603_10V4Z VP1020@ 1 2 DSP_SMB_DA 24 VP1020@
SDA
8

VP1020@ U61B VP1020@ 1 2 R733 100K_0402_5% 32 VP1020@ R7341 2 100K_0402_5% R735100K_0402_5%

C916 VP1020@ C920 TEST1 DSP_ENABLE#
1 2 5 8 14 1 2
P

(36,37) AMP_LEFT IN+ NC BYPASS

2
C926 7 20P_0402_50V8J 9
O NC
1U_0402_6.3V6K 6 IN- 1
G

VP1020@ Y5 VP1020@R736 27 10 VP1020@ R7371 2 100K_0402_5%

VP1020@ LM358M_SO8 13MHZ_16PF_X6G013000FG1H 1M_0402_5% XTAL_IN SEG_SEL C921
28
4

2
VP1020@ XTAL_OUT
46 VP1020@ C922 1 2 1U_0603_10V4Z 1U_0603_10V4Z

1
VP1020@ R738 1 REF2 2
1 2 2 330_0402_5% VP1020@
VP1020@ C923 44 VP1020@ C924 1 2 1U_0603_10V4Z
20P_0402_50V8J VP1020@ R739 1 REF1
2 100K_0402_5% 25

VSS_REF
VP1020@ R740 1 VOLDN
2 100K_0402_5% 26 22 VP1020@ R7411 2 100K_0402_5%

GND_D
VSS_D
VSS_D
VSS_A

VSS_A
VOLUP GPIO4

VP1020-N_QFN48

45

38

7
18

29
VP1020@
DSP_SMB_CK 1 2 +3VS_DSP
R769 10K_0402_5%
VP1020@

DSP_SMB_DA 1 2 +3VS_DSP
R773 10K_0402_5%
DSP_WP# VP1020@
(32) DSP_WP#
2
G

+3VS_DSP +3VS_DSP
1 3 DSP_EECK
3 (32,33,44) EC_SMB_CK1 3
Q39
D

2N7002_SOT23 +3VS

2
VP1020@
R802
2

2
DSP_WP# R770 R771 R772 Need to change P/N to "24C02BN-10SU-1.8" R803 +3VS 10K_0402_5%
(32) DSP_WP#
VP1020@

1
10K_0402_5% 10K_0402_5% U60 10K_0402_5% DSP_RST#
2

VP1020@ 10K_0402_5% VP1020@ VP1020@

G

8 VCC 1
1

1
A0

5
VP1020@ 7 WP 2 VP1020@
A1

1
DSP_EEDA DSP_EECK DSP_ENABLE# D
1 3 6 SCL 3 1

P
(32,33,44) EC_SMB_DA1 A2 (37) DSP_ENABLE# A 2N7002_SOT23
Q40 DSP_EEDA 5 SDA 4 4 2
D

2N7002_SOT23 GND Y G Q44

2 B
1

G
VP1020@ AT24C02N-10SU-2.7_SO8 S

3
2
R774 VP1020@ +3VS U62

3
10K_0402_5% R801 VP1020@
VP1020@ SN74AHCT1G86DCKR_SC70-5

2
10K_0402_5%

G
1 2

VP1020@

1
D Q42 1 3
DSP_WP# 2 VP1020@

S
G 2N7002_SOT23 1
S
3

C931 Q43
1U_0603_10V4Z 2N7002_SOT23
2 VP1020@
VP1020@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Friday, November 11, 2005 Sheet 38 of 47
A B C D E
 H1 H4 H3 H2 H5
H_S394D138 H_S315D138 H_C236D162 H_S366D138 H_C197D197N

FAN1 Conn @ @ @ @ @

1
+5VS
C47 10U_1206_16V4Z +5VS
1 2
H7 H8 H9 H10 H6

1
H_TC236BC165D165 H_TC236BC165D165 H_TC236BC165D165 H_TC236BC165D165 H_C236D162
U2 D4
1 8 1SS355_SOD323
VEN GND @ @ @ @ @
2 7

1
+VCC_FAN1 VIN GND D5
3 6

2
EN_DFAN1 VO GND 1N4148_SOT23
(32) EN_DFAN1 4 VSET GND 5
1 2
G993P1UF_SOP8
H14 H15 H13 H23 H22
C51 H_S394D138 H_S394D138 H_S374X354D138 H_TS559X295BS394X276D138 H_S394D138
10U_1206_16V4Z
1 2
@ @ @ @ @

1
+3VS C58
1000P_0402_50V7K
1 2

1
R45 H20 H21 H24
10K_0402_5% H_C158D158N H_S394X374D138 H_S354X293D138
40mil JP19
2

+VCC_FAN1 @ @ @

1
1
(32) FAN_SPEED1 2
3
1
C59 ACES_85205-03001
1000P_0402_50V7K H29 H28 H26 H27 H25
H_C236D162 H_S354X335D138 H_O217X157D217X157N H_S315D138 H_S374X354D138
2

@ @ @ @ @

1
H18 H12 H17 H11
H_O87X68D47X28 H_O87X68D47X28 H_O87X68D47X28 H_O87X68D47X28

@ @ @ @

1
FAN2 Conn
+5VS
C338 10U_1206_16V4Z +5VS
1 2
@ FD2 FD1 FD3 FD5 FD4 FD6
1

U10 D8
1 8 @ 1SS355_SOD323 @ @ @ @ @ @

1
VEN GND
2 VIN GND 7
+VCC_FAN2 3 6 D9
2

EN_DFAN2 VO GND 1N4148_SOT23

(32) EN_DFAN2 4 VSET GND 5
1 2
G993P1UF_SOP8 @ CF20 CF14 CF18 CF21 CF7 CF10 CF12 CF4 CF6 CF15
@
C339
10U_1206_16V4Z @ @ @ @ @ @ @ @ @ @

1
1 2
@
+3VS C343
1000P_0402_50V7K CF17 CF16 CF19 CF13 CF9 CF1 CF2 CF3 CF5 CF11
1 2
1

@
R207 @ @ @ @ @ @ @ @ @ @

1
10K_0402_5%
@ 40mil JP25 CF8
2

+VCC_FAN2
1
(32) FAN_SPEED2 2 @

1
3
1
C344 ACES_85204-0300
1000P_0402_50V7K @
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 39 of 47
 A B C D E

+5VALW

2
R294
100K_0402_5%

1
SYSON#
+5VALW TO +5VS

1
D
1 +5VALW +5VS SYSON 2 Q8 1
(29,32,46) SYSON
G 2N7002_SOT23
U16 S

3
1
8 D S 1
7 2 R295
D S

2
6 3 1 1 100K_0402_5%
D S C464 C465 R358
1 1 5 D G 4
C418 C419 470_0603_5%

2
SI4800BDY_SO8 10U_0805_10V4Z
10U_0805_10V4Z 2 2
1U_0603_10V4Z
AOS 4422

1
2 2
10U_0805_10V4Z

1
D
2 SUSP
G
+VSB 2 1 5VS_GATE S Q12

3
R317 2N7002_SOT23
200K_0402_5% 1
1

D C455
SUSP 2
Q11G 0.1U_0603_25V7K
2N7002_SOT23 S 2
3

2005/11/02

+5VALW

2
R362
100K_0402_5%

2 2

1
SUSP
(44,45) SUSP

1
D
2 Q13
(29,32,33,45) SUSP#
G 2N7002_SOT23
S

3
1
R363
100K_0402_5%

2
+3VALW TO +3VS
+1.8V to +1.8VS
+3VALW +3VS +1.8V +1.8VS

U27 U44
8 D S 1 8 D S 1
7 D S 2 7 D S 2 1 1
2

2
6 3 1 1 2005/11/02 6 3 C755 C756
D S C514 C518 R423 D S R590
1 1 5 D G 4 1 1 5 D G 4
C508 C509 470_0603_5% C741 C740 10U_0805_10V4Z 470_0603_5%
SI4800BDY_SO8 10U_0805_10V4Z SI4800BDY_SO8 2 2
1U_0603_10V4Z
10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z
AOS 4422 AOS 4422
1 1

1
2 2
10U_0805_10V4Z SYS_VS_OFF (35) 2 2
10U_0805_10V4Z
D

1
D
2 SUSP
G 2 SUSP
3 S Q17 G 3
3

5VS_GATE 2N7002_SOT23 +VSB 2 1 1.8VS_GATE S Q33

3
R586 @ 2N7002_SOT23
510K_0402_5% 1
C746
1

D
SUSP 2 0.1U_0603_25V7K
G 2
Q31 S 2005/11/02
3

2N7002_SOT23

+1.5VS +2.5VS +1.05VS +0.9VS +1.8V

2

R290 R238 R497 R43 R583

470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% 470_0603_5%
@ @
1

1
1

D D D D D
2 SUSP 2 SUSP 2 SUSP 2 SUSP 2 SYSON#
G G G G G
S Q10 S Q7 S Q29 S Q2 S Q32
3

2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23 2N7002_SOT23

4 @ @ 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL51 LA-3081P
Date: Wednesday, November 09, 2005 Sheet 40 of 47
A B C D E
 A B C D

PL2 PR1
PCN1 ADPIN VIN
VIN PD1 1K_1206_5% PQ1 B+
FBMA-L18-453215-900LMA90T_1812 2 1 1 2 3 TP0610K-T1-E3_SOT23
1
1 1 2

1
1 1N4148_SOD80 PR3 1

PR2 1K_1206_5%
G 2 10_1206_5% 1 2

12P_0402_50V8J
560P_0402_50V7K

470K_0402_5%

470K_0402_5%
G

1
PR4
12P_0402_50V8J

560P_0402_50V7K
3 PR6

1 2
1

1
PC1

PR5
1K_1206_5%

2
PC2

PC3

PC4
SINGA_2DC-G756I200 1 2
PD2

2
RLZ24B_LL34 PR7

2
1K_1206_5%
1 2

1
PR8
470K_0402_5%

1 2
1
PQ2 PQ3
DTC115EUA_SC70 DTC115EUA_SC70

(32,43) ACOFF 2 2

3
2 2

BATT+ VIN
2

2
PD4

PD3 1N4148_SOD80
RB751V-40TE17_SOD323-2
1

PR9
1

33_1206_5%
PQ4 VL PR10 B+
TP0610K-T1-E3_SOT23 2.2M_0402_5%
2 1
2

CHGRTCP 3 1 VS
0.22U_1206_25V7K

1
1

VS PR11
1

PR12 499K_0402_1%

1
PC5

100K_0402_5% PC6
0.1U_0603_25V4Z PR13
2

2
PR14 100K_0402_1% LM393DR_SO8
2

22K_0402_5% PU1A
(34,35) 51ON# 1 2

8
(19,42,44) MAINPWON PD5
2 3

P
3 3
+
1 1 O

0.01U_0402_25V7Z
(43) ACON 3 - 2

PC7
1000P_0402_50V7K
RB715F_SOT323 PR15

4
1

1
191K_0402_1%

PC9
PC8 PR16

2
0.1U_0402_16V7K

PRG++ 2

2
1

499K_0402_1%
PR17 RTCVREF
200_0603_5% PU2
G920AT24U_SOT89 3.3V ACIN RHU002N06_SOT323
2

PR18 PR19 PR20 PQ5 PR21

Precharge detector

1
34K_0402_1% D 47K_0402_5%
2 IN OUT 3 1 2 1 2 CHGRTC
Min. typ. Max. RTCVREF 2 1 2 2 1
PACIN (43,45)
1

4.7U_0805_6.3V6K

560_0402_5% 560_0402_5% G
1

1
GND
PC11

PC10
H-->L 14.589V 14.84V 15.243V S

3
1U_0805_25V4Z
2

1
1 PQ6
L-->H 15.562V 15.97V 16.388V
2

PR22 DTC115EUA_SC70
@ 66.5K_0402_1% 2 +5VALWP
BATT ONLY

2
Precharge detector

3
Min. typ. Max.
4
H-->L 6.138V 6.214V 6.359V 4

L-->H 7.196V 7.349V 7.505V

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN/DECTOR/RTC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 41 of 47
A B C D
 A B C D

1 1

PC12 PC13
0.1U_0603_25V7K 0.1U_0603_25V7K
B+
1 2 BST5B_5V BST3B_3V 1 2

2
2

PR23
0_0402_5% PD6 3HG
PL3 5HG 1 2 MAX8734A_B+ CHP202UPT_SOT323-3
FBMA-L11-322513-151LMA50T_1210

1
VL
1

MAX8734A_B+

4.7_1206_5%
2

1
PR24
MAX8734A_B+ PQ7 MAX8734A_B+
8 1 PR26
G2 D2

1
2200P_0402_50V7K

7 2 0_0402_5% PQ8
D1/S2/K D2
4.7U_1206_25V6K

2200P_0402_50V7K
6 3 DL5 PC14 1 8
D1/S2/K G1 D2 G2

4.7U_1206_25V6K
5 4 0.1U_0603_25V7K 2 7

2
D1/S2/K S1/A D2 D1/S2/K
1

1
PC16

3 G1 D1/S2/K 6

1
PC15

0.1U_0603_25V7K

47_0402_5%
AO4916L_SO8 4 5
S1/A D1/S2/K

PC17

PC18
2

1U_1206_25V7K

PR27
AO4916L_SO8

2
1

PC20
2 2

2
PC19

1
VL PR28

2
10U_LF919AS-100M-P3_4.5A_20%

0_0402_5%

4.7U_0805_6.3V6K

1
1U_0805_16V7K
1

PC21
1

10U_LF919AS-100M-P3_4.5A_20%
PC22

2
PR29

2
2

0_0402_5%
PL4

18

20

13

17
BST5A_5V 14

V+
LD05

TON

VCC

1
BST5 ILM3
ILIM3 5

2
DH5 16
1

DH5

PL5
LX5 15
+5VALWP DL5 19
LX5
11 ILM5
DL5 ILIM5
21 OUT5
9 PU3 28 BST3A

1
FB5 BST3
10.2K_0402_1%

PR31 1 26 DH3
N.C.MAX8734AEEI+_QSOP28 DH3
2

47K_0402_5% 24 DL3
DL3
PR30

VS 1 2 1 2 6 27 LX3 +3VALWP
SHDN# LX3
1 4 ON5 OUT3 22
2
100K_0402_5%

3 ON3
1
150U_D_6.3VM

PR32

@ 3.57K_0402_1%
+ @ PZD1 7
1

FB3

2
PC23

RLZ5.1B_LL34 PC24 12 2
SKIP# PGOOD SPOK (44)

PR33
3 0.047U_0402_16V7-K 3
2

PRO#
LDO3
0_0402_5% 8

GND
1
1

REF
2

0_0402_5%

PR34
PR35

+ PC25

1
2

150U_D_6.3VM

23

25

10
PR36 2VREF_1999
2VREF_1999
1

0_0402_5% 2
1

2
100K_0402_1%

100K_0402_1%
2

2
0.22U_0603_10V7K

4.7U_0805_10V6K

PR38

PR39

PR37
0_0402_5%
1

2
PC27
PC26

PR40
0_0402_5%
2

1
1

1
ILM3 ILM5

1
(19,41,44) MAINPWON 1 2

2
499K_0402_1%
PR42

499K_0402_1%
PR41

PR43
47K_0402_5%
1

PC28 PC29

1
1U_0603_6.3V6M 0.047U_0402_16V7-K
2

+5VALWP Ipeak = 6.66A ~ 10A +3VALWP Ipeak = 6.66A ~ 10A

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+5VALWP/+3VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 42 of 47
A B C D
 A B C D E

Charger
Iadp=0~4.74A(90W)

P2
PQ9 PQ10 PR44 B+ PL6 CHG_B+ PQ11
AO4407L_SO8~N AO4407L_SO8~N P3 AO4407L_SO8~N
0.01_2512_1% FBMA-L18-453215-900LMA90T_1812
VIN 8
7
1
2
1
2
8
7
2 1 1 2 1
2
8
7

2200P_0402_50V7K
0.1U_0603_25V7K
6 3 3 6 3 6

4.7U_1206_25V6K

4.7U_1206_25V6K
5 5 5

1
1 1

PC30

PC31

PC32

PC33
4

4
1
PC146 PC147 PR47

2
1
0.1U_0603_25V7K 0.1U_0603_25V7K 47K_0402_1%

1
1 2
VIN

2
PR45

2
1

10K_0402_1%
0.1U_0603_25V7K

SI4810BDY-T1-E3_SO8
200K_0402_1%

2
PR46

5
6
7
8
47K_0402_5%

2
1

PR49
D
D
D
D
3

PC34
PQ12 1SS355_SOD323
2

PQ15
DTA144EUA_SC70
PD13
2

1
47K
ACOFF#

G
S
S
S
2 47K VIN 2 1

4
3
2
1

1
(44) 6C/8C#

2
G
PC149 PQ13
0.1U_0603_25V7K PU4 DTC115EUA_SC70

SI4810BDY-T1-E3_SO8
3 1 MAX1908ETI_QFN28
1

2
1

ACOFF

D
1 DCIN 2 ACOFF (32,41)

5
6
7
8
PQ42 27
PC148 SI2301DS_SOT23~D CSSP

D
D
D
D

1
1U_0603_10V6K

PQ41
2 PQ14 2 1 17 PC150

3
DTC115EUA_SC70 57.6K_0402_1% PR197 CELLS @ 1000P_0402_50V7K
26

2
CSSN

G
S
S
S
PR198 @ 0_0402_5%
2 1 4

4
3
2
1
REF
150K_0402_5%

25 charger_DHI
3

DHI
1
RHU002N06_SOT323

3 PR61
CLS
PQ16

PR55

0.015_2512_1%
1908LDO BATT+
1

D charger_LX
LX 23 1 2 1 2
1
100K_0402_1%

2 2 1 2 1 12 REFIN
1

2 G 2
2

10U_LF919AS-100M-P3_4.5A_20%
PR201

S PC151 PR199 PR200 21 charger_DLO

3

DLO

4.7U_1206_25V6K

4.7U_1206_25V6K

4.7U_1206_25V6K
PL7
0.1U_0402_16V7K 9.31K_0402_1% 15K_0402_1% PC152
2

15 0.1U_0603_25V7K
2

1
VCTL

1
PC46

PC47

PC48
13 24 charger_BST 1 2
ICTL BST

1
11 PR202 0_0402_5%

2
ACOK# charger_DLOV PD14
8 SHDN# DLOV 22
1

D
10 ACIN 1SS355_SOD323
2 9 ICHG LDO 2 2 1

0.01U_0402_25V7K
G 2 1

2
S PQ17 (32) IREF 28 PR203
3

RHU002N06_SOT323 24.9K_0402_1% IINP 1908LDO 33_1206_5%

7

2
CCV

PC153
PR204 19
CSIP
1

2
PGND
18

GND
CCS
PD8 CSIN

CCI
PR205 16 PC154
BATT

2
ACOFF# 1 2 100K_0402_1% 1U_0603_10V6K

1
1K_0402_1%
PC155

14

20
2
1U_0805_25V4Z
2

1
1N4148_SOD80

PR206
PR64 MAX1908-CCS
22K_0402_5%

0.01U_0402_25V7K

0.01U_0402_25V7K
(41,45) PACIN 1 2

2
PC156

PC157
1

1
(41) ACON

2
3 BATT+ 3
PC158
PR207 0.1U_0402_16V7K
0_0402_5%
Charge voltage
1 2
(32) FSTCHG VS BATT+
4S CC-CV MODE : 16.8V
2

1
10K_0402_5%

1
PR209

PR67

0.01U_0402_25V7Z
PR208 PC159 845K_0603_1%
100K_0402_5% 0.1U_0402_16V7K
2

LI-4S :17.8V--BATT-OVP=1.9758V
1

2
1

PC49
+3VALWP
BATT-OVP=0.111*BATT+

1
2
PR68

1
300K_0603_0.1%
IREF=0.832*Icharge PR210 PR211

8
PU5B 511K_0402_1% RHU002N06_SOT323 10K_0402_5%

2
IREF=0.73~3.3V 5 1 2

P
+ PQ43
7

2
0
VS (32) BATT_OVP - 6

1
D

1
LM358ADR_SO8 2

1
PR71 G
2P4S:4800mAH/cell
8

PU5A 200K_0402_1% PC50 S

1
0.01U_0402_25V7Z D
0.8C=3.84A + 3
P

2
1 2 6C/8C# (44)

2
0 G
- 2
G

S RHU002N06_SOT323

3
4 LM358ADR_SO8 4
PQ44
4

OVP voltage :
LI-3S :17.8V----BATT-OVP=1.9758V
BATT-OVP=0.111*BATT+ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 43 of 47
A B C D E
 A B C D

PR212
100K_0402_5%

1 2
PH1 under CPU botten side :
+3VALWP
BATT+ BATT++ CPU thermal protection at 80 degree C
PR213
PL8 1K_0402_5%
Recovery at 44(45) degree C

BATT+
2 1
FBMA-L18-453215-900LMA90T_1812 6C/8C# (43) 1 2
1 2 BATT++
1
VL PR77 1

2
442K_0603_1%
1

1
PR214 VL
PC54 @1K_0402_5% VS

2
1000P_0402_50V7K
2

0.1U_0603_25V7K
PC53 PR81 PR80

1
0.01U_0402_25V7Z 10.7K_0402_1% 150K_0402_1%

PC55

1
2

2
61.9K_0402_1%

8
PR83 PU1B
PR84 1 2 5

P
7 1K_0402_5% + MAINPWON (19,41,42)
PJP2 battery connector 6
2 1 TM_REF1 6
O 7
5 -

G
4
SM ART LM393DR_SO8

4
3

100K_0603_1%_TH11-4H104FT
PR85
Batter y: 2
1
1K_0402_5%
1 .GND 1 2 BATT_TEMP
BATT_TEMP (32)

1U_0805_25V4Z
2. SMC

1
SUYIN_200275MR007G161ZL PC56
PJP1

PC57
1000P_0402_50V7K PR86
3.SMD

PH1
PR87 2 1 VL

2
4.TS 6.49K_0402_1%
150K_0402_1%
1 2 +3VALWP
5 . B/I

2
6. ID PR88

1
150K_0402_1%
2 7 .BA TT+ PR89 2

100_0402_5%
1 2 EC_SMB_DA1 (32,33,38)

2
PR90
100_0402_5%
1 2 EC_SMB_CK1 (32,33,38)

+1.8V

PU6
1 VIN VCNTL 6 +3VALW
PQ20
TP0610K-T1-E3_SOT23 2 5
GND NC

1
1
PC58 3 7 PC59
10U_1206_6.3V7K VREF NC 1U_0603_6.3V6M

2
3
B+ 3 1 +VSBP PR91 4 8 3

1K_0402_1% VOUT NC
9

2
TP
1

PR92 APL5331KAC-TRL_SO8
100K_0402_5% PC60 PC61
0.22U_1206_25V7K 0.1U_0603_25V7K
+0.9VSP
2

0.1U_0402_16V7K
1K_0402_1%
2

22U_1206_6.3V6M
1

1
PR93

PC62

PC63
@ PC64

2
2

22U_1206_6.3V6M

2
VL PR94 PR95
22K_0402_5%

1
0_0402_5% D
2

SUSP 1 2 2
(40,45) SUSP
1

PR96 G PQ21
100K_0402_5% S

3
1
RHU002N06_SOT323
PR97 PC65
1

0_0402_5% D PQ22 @ 0.1U_0402_16V7K

2
(42) SPOK 1 2 2
G RHU002N06_SOT323
S
3
1

PC66
@ 0.1U_0402_16V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN. / OTP/+0.9VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 44 of 47
A B C D
 5 4 3 2 1

AC Adapter Detector
PJ1 PJ2
+1.5VSP 1 2 +1.5VS +1.8VP 1 2 +1.8V
PAD-OPEN 3x3m PAD-OPEN 3x3m Vin Detector
(2.5A,100mils ,Via NO.=5) (6A,240mils ,Via NO.= 12) 17.90V/17.24V
D D

PJ3 PJ4 PR75

+5VALWP 1 2 +5VALW +0.9VSP 1 2 +0.9VS 1 2
VIN 1M_0402_1% VIN
PAD-OPEN 3x3m PAD-OPEN 3x3m
(5A,200mils ,Via NO.= 10) (0.3A,40mils ,Via NO.= 2) PR73

1
10K_0402_5% PR98
PR69 VS 10K_0402_5%
PJ5 PJ6 84.5K_0402_1% AC IN
1 2 ACIN (20,32)
+3VALWP 1 2 +3VALW +2.5VSP 1 2 +2.5VS
PR74

2
8
22K_0402_5% PU7A
PAD-OPEN 3x3m PAD-OPEN 3x3m
1 2 3

P
+ PACIN
(4.5A,180mils ,Via NO.= 9) (0.3A,40mils ,Via NO.= 2) O 1 PACIN (41,43)
2 -

G
20K_0402_1%
1

1
PJ7

PR72
PJ8 LM393DR_SO8

4
1 2 +1.05VS +VSBP 1 2 +VSB PC51 PZD2 PR99
+1.05VSP 1 2 0.1U_0603_25V7K 10K_0402_5%
RLZ4.3B_LL34

2
JUMP_43X79 PC52
PAD-OPEN 3x3m

2
1000P_0402_50V7K

2
(2A,80mils ,Via NO.= 4)

2 1 RTCVREF

C PL9 PR70 C
FBMA-L11-322513-151LMA50T_1210 10K_0402_5%
1 2 MAX8578_B+
B+

8
PU7B
0.1U_0603_25V7K

4.7U_1206_25V6K

P
+
O 7
1

6 -

G
PC70

PC71

0_0402_5%
PR106 LM393DR_SO8
2

4
1.5V_EN 1 2 SUSP# (29,32,33,40)
2

PC72
2
2

PR107 @ 1U_0805_25V4Z
1

4.99K_0402_1% PC73
1

0.01U_0402_25V7Z
1

PU8
1.5V_OCSET 10 9 PR108
OCSET EN 0_0402_5% PQ23 PU9
1.5V_SS 2 81.5V_DH1 2 1 1.5V_DH2 8 1 CM8562IS_PSOP8
SS DH G2 D2
7 D1/S2/K D2 2
1

1.5V_FB 1 71.5V_LX 6 3 +3VALW 1 8

FB LX D1/S2/K G1 VIN PGND
3300P_0402_50V7K

5 D1/S2/K S1/A 4
1.5V_VL 3 5 +2.5VSP
2

VL DL

2
PC74

4.7U_1206_25V6K
AO4916L_SO8 2 7AGND +5VALW
1.5V_DL1

VFB AGND
1

PC75
4 GND BST 6

1
B B

10_0603_1%
MAX8578EUB+T_UMAX10 3 6
2

VTT VCCA
1.5V_BST

PR110
1 2 1.5V_DL2

AGND
PC76
4.7_0402_5% 4 5
VTT REFEN

2
1U_0603_6.3V6M
4.7U_0805_6.3V6K PR109 PL10
PD9

PC77
3.0UH_SPC-07040-3R0GP_5A_30%

REF_EN
9
2 1 1 2 1 2 +1.5VSP

1
2
1 2
1

0.1U_0603_25V7K
PR111
1SS355_SOD323 PC78
PR112
4.7_1206_5%

PR113 PR114 PC79

AGND
1 200K_0402_1%

1
2
+5VS 0.1U_0603_25V7K 7.15K_0402_1% 30_0402_5% 330U_D2E_2.5VM 22U_1206_6.3V6M
PC80

PC81
+
PR116 2 1 2 1 RTCVREF
1 2

1
1.5K_0402_1%
PC83 2 PR115
1 2
680P_0603_50V8J PC82 64.9K_0402_1%
0.047U_0402_16V4Z
2

1 2
RHU002N06_SOT323
1

1
D PQ24
PR117 PC84 PC85 2 SUSP
SUSP (40,44)
825_0402_1% 0.033U_0603_25V7K 0.1U_0603_25V7K G
1

3
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VSP/RTCVREF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 45 of 47
5 4 3 2 1
 5 4 3 2 1

D D

MAX8743_B+
PL1
1 2 B+

4.7U_1206_25V6K
2200P_0402_50V7K
FBMA-L11-322513-151LMA50T_1210

PC87
PC86
+5VALW

4.7U_0805_6.3V6K
1
@

PC88

4.7U_1206_25V6K

4.7U_1206_25V6K
2200P_0402_50V7K
C C

2
PD10

PC91
DAP202U_SOT323

5
6
7
8

PC89

PC90
PQ26 PQ25
SI4800BDY-T1-E3_SO8

D
D
D
D

2
5
6
7
8

SI4800BDY-T1-E3_SO8

3
BST2B_1.05V
D
D
D
D

BST1B_1.8V

G
S
S
S
1U_0805_25V4Z
0.1U_0603_25V7K PC95

4
3
2
1
G
S
S
S

PL11 PC94 PR118 PL12

0.1U_0603_25V7K 20_0603_5% 0.1U_0603_25V7K
4
3
2
1

1.8U_D104C-919AS-1R8N_9.5A_30% PC92 1 2 PC93 1.8U_D104C-919AS-1R8N_9.5A_30% +1.05VSP

+1.8VP 1 2 2 1 2 1 1 2

1
5
6
7
8

5
6
7
8
PQ27 PR119
D
D
D
D

4.7U_0805_6.3V6K
SI4810BDY-T1-E3_SO8 0_0402_5% PQ28

D
D
D
D
150U_D_6.3VM

150U_D_6.3VM
4.7U_0805_6.3V6K

PR120

22
1 SI4810BDY-T1-E3_SO8 1

9
PU10 0_0402_5%
1
1

1
S
S
S
PC96

PC99

PC97
+ BST1A_1.8V 25 21 +

UVP
V+

VCC
BST1 VDD

G
S
S
S
PC98

4
3
2
1

1
DH_1.8V 26 19 BST2A_1.05V
2

4
3
2
1

2
2 PR219 DH1 BST2 DH_1.05V 2
DH2 18
LX_1.8V 27 17 LX_1.05V PR121
LX1 LX2
1

@ 8.2K_0402_5% DL_1.8V 24 20 DL_1.05V 499_0402_1% @

@ DL1 DL2
16

2
28 MAX8743EEI_QSOP28 CS2
B CS1 B
1 OUT1 OUT2 15
14
2

FB2
2 FB1 ON2 12
1

1
PGOOD 7
PR220 5
(29,32,40) SYSON TON PR122
2 1 11 ON1
0_0402_5% 13 10K_0402_1%
PR123 ILIM2 VS_ON (35)
3 1 2
SKIP
GND
OVP

REF
2

2
0_0402_5% ILIM1
1

PR124
PC100 PR125 0_0402_5%
8

23

10

@ 0.01U_0402_25V7Z 33K_0402_1%
2

2 1
PR126
2 1 100K_0402_1%
1

100K_0402_1%
15K_0402_1%
1

PR127

PR128
PC101
0.22U_0603_10V7K
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VSP/+1.8VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 46 of 47
5 4 3 2 1
 5 4 3 2 1

+5VS

CPU_B+ PL13 B+
PR129 FBMA-L11-322513-201LMA40T_1210
5VS12 1
2 1

0.01U_0402_25V7Z
0_1206_5% 1

2200P_0402_50V7K
0.1U_0603_25V7K
PR130

PC103
10_0402_5% + PC102

1
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK
100U_25V_M

200K_0402_5%

PC104

PC105

PC106

PC107

PC108
2

2
2 PR131 1
2

2
D D

2
PC109

2
2.2U_0603_6.3V6K

2
PR132 PC110

1
13K_0402_1% 1U_0603_6.3V6M

5
PQ29
PU11 SI7840DP_SO8

1
NTC
PH2 V CC 19 25
100K_0603_1%_TH11-4H104FT Vcc VDD 0_0402_5% 0.22U_0603_16V7K 4
1 2 6 THRM TON 8
PR135 PC111 0_0402_5%
PR134 0_0402_5% 2 1 31 30 BST1_CPU 1 2 BSTM1_CPU 1 2
(5) CPU_VID0 D0 BST1 +CPU_CORE
PR215

3
2
1
PR136 0_0402_5% 2 1 32 29 1 2 PL14
(5) CPU_VID1 D1 DH1 P_0.36H_ETQP4LR36WFC_24A_20%

4.7_1206_5%
PR137 0_0402_5% 2 1 33 28 LX1__CPU 2 1 +CPU_CORE
(5) CPU_VID2 D2 LX1

680P_0402_50V7-K 2.1K_0402_1%
PR138 0_0402_5% 2 1 34 26 DL1__CPU
(5) CPU_VID3 D3 DL1

5
6
7
8

5
6
7
8

10_0402_5%
PR139

PR141
PR140 0_0402_5% 2 1 35 27
(5) CPU_VID4 D4 PGND1
PR142 0_0402_5% 2 1 36 18 @
(5) CPU_VID5

2
D5 GND

1
3.48K_0402_1% NTC PH3

1
IRF8113PBF_SO8
PR143 0_0402_5% 1 2 37 17 CSP1__CPU 4 4 PR145
(5) CPU_VID6 D6 CSP1

1
1 2 1 2 @

VCCSENSE

(5)
DL1__CPU
PR1472 71.5K_0402_1%
1 7 16 CSN1_CPU
TIME CSN1

PC112

PR144
PQ30 10KB_0603_1%_TH11-3H103FT

2
PQ31
2 1 9 12 FB_CPU 1 2

3
2
1

3
2
1
470P_0402_50V8J PC113 CCV FB IRF8113PBF_SO8
1 2 11 10 C CI_CPU PC114 0.22U_0603_16V7K
C REF CCI C

1 2 PC115 0.22U_0603_16V7K 39 21 DH2_CPU

(6,20) PM_DPRSLPVR DPRSLPVR DH2
PR148 499_0402_1% @
1 2 40 20 BST2_CPU
(4,19) H_DPRSTP# DPRSTP BST2

1
PR149 0_0402_5%
1 2 3 22 LX2_CPU PR151 0_0402_5% PR194
(5) PSI# PSI LX2
PR150 0_0402_5% 1 2 0_0402_5%
+3VS 2 24 DL2__CPU
PWRGD DL2 PR152 @ 1K_0402_1% PC116 @ 1000P_0402_50V7K

2
2

0_0402_5%
1 23 1 2 1 2 CPU_VCC_SENSE
CLKEN PGND2

PR153
2

38 14 CSP2_CPU PR156 3.65K_0402_1%

PR154 PR155 SHDN CSP2
1 2 1 2
PR158 @ 2K_0402_1% @ 2K_0402_1% 5 15 CSN2__CPU

1
0_0402_5% VRHOT CSN2 PR157 100_0402_5%

2
4 13
1

POUT GNDS PC117

1 2 1 2 1 2

BSTM2_CPU
(6,14,20) VGATE 0_0402_5% 4700P_0402_25V7K

1
PR161 NTC PR159 PR160
1 2 @ 3K_0603_1% @ 3K_0603_1%
(14) CLK_ENABLE# MAX8770GTL+_TQFN40

2
1 2 1 2
1 2 PC119
(32) VR_ON
1000P_0402_50V7K PC118
1
2

CPU_B+

0.22U_0603_16V7K
PR163 PR162 470P_0402_50V8J

1
0_0402_5% PR164 +3VS 2 20K_0402_1%

PC120
@ 10K_0402_5%
1

PR165

2200P_0402_50V7K
10U_1206_25VAK

10U_1206_25VAK

10U_1206_25VAK

0.1U_0603_25V7K
PR166 100_0402_5%
VRHOT
1

56_0402_5%

1
PC122
PR167 PQ32
1

PC121

PC123

PC124

PC125
B @ 0_0402_5% SI7840DP_SO8 B
2

1 2 (5) VSSSENSE VSSSENSE 0_0402_5%

2
(28,32) TV_THERM#
PR216
1

1 2 4
1 2 PR169
(32) POUT
@ 10_0402_5%
2

PR168 10K_0402_5%
PC126
2

3
2
1
0.1U_0402_16V7K 2 1
1

4.7_1206_5%
PL15

1
P_0.36H_ETQP4LR36WFC_24A_20%

5
6
7
8

5
6
7
8

PR170

2.1K_0402_1%
IRF8113PBF_SO8

1
PQ34 @

PR171
IRF8113PBF_SO8

680P_0402_50V7-K
DL2__CPU
4 4

2
1

PC127
NTC
PR172

PQ33
3.48K_0402_1% PH4

3
2
1

3
2
1

2
1 2 1 2

10KB_0603_1%_TH11-3H103FT
@

1 2

A PR174 0_0402_5% PC128 0.22U_0603_16V7K A

1 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Wednesday, November 09, 2005 Sheet 47 of 47
5 4 3 2 1