EM316 DIGITAL ELECTRONICS LABORATORY 6

NMOS Gates
Each of more complex logic gates has a single load device that is between the logic gate output and VDD in the same fashion as the NMOS inverters. Furthermore, the single output transistor NO is replaced with multiple N-channels either in parallel (NOR) or series (NAND) or both (AOIs). The gate terminal of each non-load N-channel MOSFET serves as a separate logical gate input.

Figure 25 NMOS NOR Gates

Figure 26 NMOS NAND Gate

Figure 27 AND - OR - invert gate

Figure 28 Exclusive OR/NOR gate

Simulation1
Setup SPICE model of circuit shown in Figure 29. Plot Voltage transient response of output.

Simulation2
Setup SPICE model of circuit shown in Figure 30 NMOS NOR. Plot Voltage transient response of output.

Simulation3
Setup SPICE model of circuit shown in Figure 31 NMOS NAND. Plot Voltage transient response of output.

Simulation4
Setup SPICE model of circuit shown in Figure 32 NMOS Schmitt Trigger. Plot Voltage transient response of output.

WO
V1 5 M9 MbreakND 5 V2

0 5.000V 0
0V

For MbreakND W= 10u L= 50u => RL= ~50k

M10 MbreaknD

0
5.000V

0
0V

M2 V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 500n PER = 1u V3
V

876.9mV 5.000V MbreakN

0
M3 V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 1000n PER = 2u V4
V

M8 MbreakN Mbreakn

0V

0V 0V 0V

0V 0V 0V

0
Figure 29 NMOS XNOR / XOR

V4 5 M4 MbreakND

0 5.000V 0
0V

V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 1u PER = 2u

V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 750n PER = 1500n

V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 500n PER = 1u

M1 5.000V MbreakN M2

V3
V

MbreakN M3 MbreakN

V2
V

0V

V1
V

0V

0V

0V

0V

0
0V

Figure 30 NMOS NOR

V4 V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 1u PER = 2u 5 M4 MbreakND V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 750n PER = 1500n

0
5.0

V3

Pw=2u PER = 4u
V

V1 = 0 V2 = 5 TD = 0 TR = 2n TF = 2n PW = 500n PER = 1u

M1 MbreakN

5.000V M2 MbreakN

V2

0V

2.570V M3 V1
V

2.570V

0V MbreakN

2.430V

0
0V

0V

0V

0
Figure 31 NMOS NAND

V1 5 M8 5.000V MbreaknD

V1 = 0 V2 = 4 TD = 0 TR = 100n TF = 100n PW = 500n PER = 1u V3

V

M2 Mbreakn 5.000V

M1 VOFF = 0 VAMPL = 2 FREQ = 3000000 MbreakN

M7 Mbreakn11

V2 5

V4

5.000V 0V

5.000V

0V R1 1

0V

0
0V

VOFF = 0 VAMPL = 2 FREQ = 9000000

V7 0V

0V

Figure 32 NMOS Schmitt Trigger

V3 5 5.000V
I W

0
MbreakP M1

V1 = 0 V2 = 5 TD = 10n TR = 10n TF = 10n PW = 1u PER = 2u

V1

0
0V

5.000V MbreakP 0V M2 0V

V1 = 0 V2 = 5 TD = 10n TR = 10n TF = 10n PW = 2u PER = 4u

V2 M3 MbreakN 0V 5.000V M4 MbreakN

V

0
0V

0V

Two input CMOS NOR gate

Simulation4
Setup SPICE model of circuit shown in Figure 32 NMOS Schmitt Trigger. Plot Voltage transient response, source current, source power of output. Assume that your computer has been made of 1M CMOS NOR gate. And your computer running at full speed which NMOS gate above supported. Then calculate the required power for your computer. Assume your computer has been made of bipolar transistor. Is a damm is enough for this CPU???