Integrated Circuits

A Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

Arithmetic Circuits
January, 2003
1

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

A Generic Digital Processor

MEM ORY INPUT-OUTPUT

CONTROL

DATAPATH

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

Building Blocks for Digital Architectures

Arithmetic unit - Bit-sliced datapath (adder, multiplier, shifter, comparator, etc.) Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, random logic.) - Counters Interconnect - Switches - Arbiters - Bus
EE141 Digital Integrated Circuits
2d n

Arithmetic Circuits

An Intel Microprocessor
9-1 Mux 5-1 Mux a CARRYGEN g64

SUMSEL

ck1

REG

node1

sum

sumb

to Cache

9-1 Mux

2-1 Mux

SUMGEN + LU LU : Logical Unit

s0 s1

1000um

Itanium has 6 integer execution units like this

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

Bit-Sliced Design
Control

Bit 3 Multiplexer Data-In Register Adder Bit 2 Bit 1 Bit 0 Shifter Data-Out
5

Tile identical processing elements

EE141 Digital Integrated Circuits
2d n

Arithmetic Circuits

Bit-Sliced Datapath
From register files / Cache / Bypass

Multiplexers Shifter Adder stage 1 Wiring Adder stage 2 Wiring

Loopback Bus Loopback Bus Loopback Bus

EE141 Digital Integrated Circuits

Bit slice 63

Bit slice 2

Bit slice 0 Bit slice 1

Adder stage 3 Sum Select

To register files / Cache
2d n

Arithmetic Circuits

Itanium Integer Datapath

EE141 Digital Integrated Circuits

Fetzer, Orton, ISSCC02 2d n

Arithmetic Circuits

Adders

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

Full-Adder
A Cin B Cout Full adder Sum

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

The Binary Adder

A Cin B Cout Full adder Sum

S = A B Ci = A BC i + ABC i + ABCi + ABCi C o = AB + BCi + ACi

EE141 Digital Integrated Circuits
2d n

10

Arithmetic Circuits

Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B Generate (G) = AB Propagate (P) = A B Delete = A B

Can also derive expressions for S and C o based on D and P Note that we will be sometimes using an alternate definition for Propagate (P) = A + B
EE141 Digital Integrated Circuits
2d n

11

Arithmetic Circuits

The Ripple-Carry Adder

A0 Ci,0 B0 Co,0 (= Ci,1) A1 B1 Co,1 A2 B2 Co,2 A3 B3

FA

FA

FA

FA

S0

S1

S2

S3

Worst case delay linear with the number of bits

td = O(N) tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit
EE141 Digital Integrated Circuits
2d n

12

Arithmetic Circuits

Complimentary Static CMOS Full Adder

VDD VDD A B Ci A Ci A B A Ci B VDD A Co B Ci A B X B Ci VDD B A Ci A B

28 Transistors
EE141 Digital Integrated Circuits
2d n

13

Arithmetic Circuits

Inversion Property
A Ci B A B

FA

Co

Ci

FA

Co

S S ( A, B, C i ) = S ( A, B , C i ) C ( A, B, C ) = C ( A, B , C ) o i o i

EE141 Digital Integrated Circuits

2d n

14

Arithmetic Circuits

Minimize Critical Path by Reducing Inverting Stages

Even cell A0 Ci,0 B0 Co,0 A1 B1 Co,1 A2 B2 C FA FA Odd cell A3 B3 Co,3

FA

FA

S0

S1

S2

S3

Exploit Inversion Property

EE141 Digital Integrated Circuits

2d n

15

Arithmetic Circuits

A Better Structure: The Mirror Adder

VDD VDD A "0"-Propagate Ci "1"-Propagate A B A Generate B A B Ci A B B B Kill A Co A B VDD Ci A B Ci S Ci

24 transistors
EE141 Digital Integrated Circuits
2d n

16

Arithmetic Circuits

Mirror Adder
Stick Diagram

VDD

Ci Co

A Ci

Co

Ci

S GND
EE141 Digital Integrated Circuits
2d n

17

Arithmetic Circuits

The Mirror Adder

The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carrygeneration circuitry. When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important. The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell . The transistors connected to Ci are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.
EE141 Digital Integrated Circuits
2d n

18

Arithmetic Circuits

Transmission Gate Full Adder

P VDD A A B A P A P B Ci P Ci P A P Ci Setup A P VDD Co Carry Generation VDD S Sum Generation

VDD Ci Ci

EE141 Digital Integrated Circuits

2d n

19

Arithmetic Circuits

Manchester Carry Chain

Pi Gi Ci Di Pi

VDD
Ci

Pi

VDD

Co Gi

Co

EE141 Digital Integrated Circuits

2d n

20

Arithmetic Circuits

Manchester Carry Chain

VDD P0 P1 P2 P3 C3 Ci,0 G0 G1 G2 G3

C0

C1

C2

C3

EE141 Digital Integrated Circuits

2d n

21

Arithmetic Circuits

Manchester Carry Chain

Stick Diagram
Propagate/Generate Row VDD Pi Ci - 1 GND Inverter/Sum Row Gi Ci Pi + 1 Gi + 1 Ci + 1

EE141 Digital Integrated Circuits

2d n

22

Arithmetic Circuits

Carry-Bypass Adder
P0 Ci,0 G1
C o,0

P0

G1
C o ,1

P2

G2
Co,2

P3

G3 Co,3

Also called Carry-Skip

FA

FA

FA

FA

P0 G1 Ci,0
C o ,0

P0

G1
Co,1

P2

G2
C o,2

P3

G3

BP=P oP1 P2 P3
Multiplexer

FA

FA

FA

FA

Co,3

Idea: If (P0 and P1 and P2 and P3 = 1) then C o3 = C0, else kill or generate.
23

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

Carry-Bypass Adder (cont.)

Bit 03 Setup tsetup Bit 47 Setup tbypass Bit 811 Setup Bit 1215 Setup

Carry propagation

Carry propagation

Carry propagation

Carry propagation

Sum M bits

Sum

Sum

tsum

Sum

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum

EE141 Digital Integrated Circuits

2d n

24

Arithmetic Circuits

Carry Ripple versus Carry Bypass

tp
ripple adder

bypass adder

4..8

N
25

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

Carry-Select Adder
Setup
P,G

"0"

"0" Carry Propagation

"1"

"1" Carry Propagation

Co,k-1

Multiplexer
Carry Vector

Co,k+3

Sum Generation

EE141 Digital Integrated Circuits

2d n

26

Arithmetic Circuits

Carry Select Adder: Critical Path

Bit 03 Setup Bit 47 Setup Bit 811 Setup Bit 1215 Setup 0 0-Carry 0 0-Carry 0 0-Carry 0 0-Carry

1-Carry

1-Carry

1-Carry

1-Carry

Ci,0

Multiplexer

Co,3

Multiplexer

Co,7

Multiplexer

Co,11

Multiplexer

Co,15

Sum Generation S03

Sum Generation S47

Sum Generation S811

Sum Generation S

EE141 Digital Integrated Circuits

2d n

27

Arithmetic Circuits

Linear Carry Select

Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15 Setup (1) "0" (1) "1" (5) "1" Carry (5) Multiplexer Ci,0 Sum Generation S0-3 Sum Generation S 4-7 Sum Generation S8-11 "1" (6) "1" Carry (5) Multiplexer "1" (7) "1" Carry (5) Multiplexer "1" (8) "1" Carry (5) Multiplexer (9) Sum Generation S 12-15 (10) "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry Setup Setup Setup

EE141 Digital Integrated Circuits

2d n

28

Arithmetic Circuits

Square Root Carry Select

Bit 0-1 Setup (1) "0" (1) "1" (3) Ci,0 Sum Generation S0-1 "1" Carry (3) Multiplexer (4) "1" "1" Carry (4) Multiplexer (5) "1" "1" Carry (5) Multiplexer (6) "1" "1" Carry (6) Multiplexer (7) Mux (8) Sum Generation S2-4 Sum Generation S5-8 Sum Generation S9-13 Sum S14-19 (9) (7) "0" Carry "0" "0" Carry "0" "0" Carry "0" "0" Carry Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19 Setup Setup Setup

EE141 Digital Integrated Circuits

2d n

29

Arithmetic Circuits

Adder Delays Comparison

50 40 tp (in unit delays) 30 20 10 0 Linear select Ripple adder

Square root select 0 20 N 40 60

EE141 Digital Integrated Circuits

2d n

30

Arithmetic Circuits

LookAhead - Basic Idea

A A1, B1

AN-1, BN-1

Ci,0

P0 Ci,1

P1

Ci, N-1

PN-1

S0

S1

SN-1

C o, k = f (A k, B k, Co , k 1 ) = Gk + P k Co , k 1

EE141 Digital Integrated Circuits

2d n

31

Arithmetic Circuits

Look-Ahead: Topology
Expanding Lookahead equations:
C o, k = Gk + P k (Gk 1 + Pk 1 Co , k 2 )
G2 VDD

All the way:

C o, k = Gk + Pk ( Gk 1 + P k 1( + P1 ( G0 + P0 Ci , 0) ) )

G1 G0 Ci,0 Co,3

P0 P1 P2 P3

EE141 Digital Integrated Circuits

2d n

32

Arithmetic Circuits

Logarithmic Look-Ahead Adder

A0 A1 A2 A0 A1 A2 A3 A4 A5 A6 A7 A3 A4 A5 A6 A7 F

tp N

tp log2(N)

EE141 Digital Integrated Circuits

2d n

33

Arithmetic Circuits

Carry Lookahead Trees

Co , 0 = G0 + P 0 Ci , 0 C o, 1 = G1 + P1 G0 + P1 P0 Ci, 0 C o, 2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P 0 C i, 0 = ( G2 + P2 G1) + ( P2 P1 ) ( G0 + P0 Ci , 0 ) = G 2:1 + P 2:1 C o, 0

Can continue building the tree hierarchically.

EE141 Digital Integrated Circuits

2d n

34

Arithmetic Circuits

(A0, B0) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 (A10, B10) (A11, B11) (A12, B12) (A13, B13) (A14, B14) (A15, B15) S10 S11 S12 S13 S14 S15 (A1, B1) (A2, B2) (A3, B3) (A4, B4) (A5, B5) (A6, B6) (A7, B7) (A8, B8) (A9, B9)

EE141 Digital Integrated Circuits

Tree Adders

16-bit radix-2 Kogge-Stone tree

2d n

35

Arithmetic Circuits

(a0, b0) (a1, b1) (a2, b2) (a3, b3) (a4, b4) (a5, b5) (a6, b6) (a7, b7) (a8, b8) (a9, b9) (a10, b10) (a11, b11) (a12, b12) (a13, b13) (a14, b14) (a15, b15) S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15

EE141 Digital Integrated Circuits

S0

Tree Adders

16-bit radix-4 Kogge-Stone Tree

2d n

36

Arithmetic Circuits

(a0, b0) S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 (a11, b11) (a12, b12) (a13, b13) (a14, b14) (a15, b15) S11 S12 S13 S14 S15 (a1, b1) (a2, b2) (a3, b3) (a4, b4) (a5, b5) (a6, b6) (a7, b7) (a8, b8) (a9, b9) (a10, b10)

EE141 Digital Integrated Circuits

Sparse Trees

16-bit radix-2 sparse tree with sparseness of 2

2d n

37

Arithmetic Circuits

(A0, B0) (A1, B1) (A2, B2) (A3, B3) (A4, B4) (A5, B5) (A6, B6) (A7, B7) (A8, B8) (A9, B9) (A10, B10) (A11, B11) (A12, B12) (A13, B13) (A14, B14) (A15, B15)

S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15

EE141 Digital Integrated Circuits

Brent-Kung Tree

Tree Adders

2d n

38

Arithmetic Circuits

Example: Domino Adder

VDD VDD Clk Gi = aibi

Clk

Pi= ai + bi

ai

ai

bi

bi

Clk

Clk

Propagate

Generate

EE141 Digital Integrated Circuits

2d n

39

Arithmetic Circuits

Example: Domino Adder

VDD Clkk VDD

Clkk

Pi:i-2k+1

Gi:i-2k+1

Pi:i-k+1

Pi:i-k+1 Gi:i-k+1

Pi-k:i-2k+1

Gi-k:i-2k+1

Propagate

Generate

EE141 Digital Integrated Circuits

2d n

40

Arithmetic Circuits

Example: Domino Sum

VDD Clk Clkd Sum Gi:0 VDD Keeper

Clk

Si0

Clkd Clk

Gi:0

Si1

Clk

EE141 Digital Integrated Circuits

2d n

41

Arithmetic Circuits

Multiplie rs

EE141 Digital Integrated Circuits

2d n

42

Arithmetic Circuits

The Binary Multiplication

Z
=

XY

M + N 1
=

M 1 = Xi2 i=0 j = 0

k=0 N 1 i

Zk 2 Yj 2
i + j

M 1 N 1
=

i =0 j= 0

Xi Yj 2

with
M 1

X Y
EE141 Digital Integrated Circuits
2d n

i=0 N 1
=

Xi 2

j= 0

Yj 2

j
43

Arithmetic Circuits

The Binary Multiplication

1 0 1 0 1 0 x 1 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 + 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 Result
44

Multiplicand Multiplier

Partial products

EE141 Digital Integrated Circuits

2d n

Arithmetic Circuits

The Array Multiplier

X3 X3 HA X3 FA X3 FA Z7 Z6 X2 FA Z5 X2 FA X1 FA Z4 X2 FA X1 FA X0 HA Z3 Y3 X2 X1 FA X0 HA Y2 X1 X0 HA Z1 X0 Y1 Y0

EE141 Digital Integrated Circuits

2d n

45

Arithmetic Circuits

The MxN Array Multiplier Critical Path

HA FA FA HA

FA

FA

FA

HA

Critical Path 1 Critical Path 2

FA

FA

FA

HA

Critical Path 1 & 2

EE141 Digital Integrated Circuits

2d n

46

Arithmetic Circuits

Carry-Save Multiplier
HA HA HA HA HA FA FA FA

HA

FA

FA

FA

HA

FA

FA

HA

Vector Merging Adder

EE141 Digital Integrated Circuits

2d n

47

Arithmetic Circuits

Multiplier Floorplan
X3 X2 X1 X0 Y0 Y1 HA Multiplier Cell C S C S C S C S Z0 FA Multiplier Cell Y2 C S C S C S C S Z1 Vector Merging Cell

Y3

C S

C S

C S

C S Z2

X and Y signals are broadcasted through the complete array. ( )

C S

C S

C S

C S

Z7

Z6

Z5

Z4

Z3

EE141 Digital Integrated Circuits

2d n

48

Arithmetic Circuits

Wallace-Tree Multiplier
Partial products 6 5 4 3 2 1 0 First stage 6 5 4 3 2 1 0 Bit position

(a) Second stage 6 5 4 3 2 1 0

(b) Final adder 6 5 4 3 2 1 0

FA (c)

HA (d)

EE141 Digital Integrated Circuits

2d n

49

Arithmetic Circuits

Wallace-Tree Multiplier
Partial products x3y3 x3y2 x2y3 x2y2 x3y1 x1y2 x3y0 x1y1 x2y0 x0y1 x1y3 x0y3 x0y2 x1y0 x0y

First stage

HA

HA

Second stage

FA

FA

FA

FA

Final adder

z7 z6

z5

z4

z3

z2

z1

z0

EE141 Digital Integrated Circuits

2d n

50

Arithmetic Circuits

Wallace-Tree Multiplier
y0 y1 y2 Ci-1 y3 Ci FA y4 FA Ci FA y5 Ci FA C C S
2d n

y0 y1 y2

y3 y4 y5

FA

FA Ci-1 Ci Ci

FA Ci-1 Ci-1

Ci-1

Ci

Ci-1

FA

EE141 Digital Integrated Circuits

51

Arithmetic Circuits

Multipliers Summary
Optimization Goals Different Vs Binary Adder Once Again: Identify Critical Path Other possible techniques - Logarithmic versus Linear (Wallace Tree Mult) - Data encoding (Booth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

EE141 Digital Integrated Circuits

2d n

52

Arithmetic Circuits

Shifters

EE141 Digital Integrated Circuits

2d n

53

Arithmetic Circuits

The Binary Shifter

Right nop Left

Ai

Bi

Ai-1

Bi-1
Bit-Slice i

...
EE141 Digital Integrated Circuits
2d n

54

Arithmetic Circuits

The Barrel Shifter

A3 B3 Sh1 A2 B2 Sh2 A1 B1 Sh3 A0 B0

: Data Wire : Control Wire

Sh0

Sh1

Sh2

Sh3

Area Dominated by Wiring

EE141 Digital Integrated Circuits
2d n

55

Arithmetic Circuits

4x4 barrel shifter

A3 A2

A1

A0

S0 h

S h1

Sh 2

S3 h

B ffe u r

Widthbarrel
EE141 Digital Integrated Circuits
2d n

~ 2 pm M
56

Arithmetic Circuits

Logarithmic Shifter
Sh1 Sh1 Sh2 Sh2 Sh4 Sh4

A3

B3

A2

B2

A1

B1

A0

B0

EE141 Digital Integrated Circuits

2d n

57

Arithmetic Circuits

0-7 bit Logarithmic Shifter

A 3 Out3 A

Out2

Out1

Out0

EE141 Digital Integrated Circuits

2d n

58

Arithmetic Circuits