SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF COMPUTING DEPARTMENT OF CSE COURSE PLAN Course Code Course

Title Semester Course Time Location : : : : :

CS0207
Computer Organization and Architecture III July Nov 2009 S.R.M.E.C Tech Park
SECTION C Hour Timing 9.2010.10 a.m 1.302.20 p.m 8.309.20 a.m 10.2011.10 am Hour 6

Day Hour Monday 2

A Timing 9.2010.10 a.m 11.1012.00 noon 1.302.20 p.m 11.1012.00 noon Hour 2

B Timing 9.2010.10 a.m 9.2010.10 a.m 1.302.20 p.m 11.1012.00 noon

D Timing 2.203.10 1.302.10 8.309.20 8.309.20 Hour -

E Timing -

Tuesday

9.20-10.10 9.2010.10,2.203.10 1.30-2.20

Wednesday

2,6

Thursday

Friday

Faculty Details Sec. A B C D E Name C.Malathy K.Annapoorani Panaiyappan C.Lakshmi PRAVEEN.N Akilandeswari. Office Tech Park Tech Park Tech Park Tech Park Tech Park Office hour Tuesday-2nd hour & 4th hourWednesday-5th hour,Friday-4th hour Monday-2nd hour,Tuesday-2nd hour,Wednesday-5th hour,Friday-4th hour Tuesday-2nd hour Wednesday5th hour,Thursday-1 st hour,Friday-4th hour Monday - Friday Monday - Friday Mail id malathyc@cse.srmuniv.ac.in annapoorani@cse.srmuniv.ac.in lakshmi@cse.srmuniv.ac.in praveen@cse.srmuniv.ac.in akilandeswari@cse.srmuniv.ac.in

Required Text Books:

1. Carl Hamacher,Computer Organization,Fifth Edition,McGrawHill International Edition, 2002 2. P.Pal Chaudhuri, "Computer Organization and Design" , 2nd Edition, PHI 2003 3. William Stallings , Computer Organization and Architecture Designing for Performance, PHI, 2004. 4. John P.Hayes, "Computer Architecture and Organization", III Edition, McGraw Hill International Editions,1998.
Web resources

www.amazon.com www.freebookcentre.com
Prerequisite Objectives : CS0102 Digital computer fundamentals

1. Gives a knowledge of various architectures 2. CPU, Control unit, I/O Processing 3. Memory and its types 4. Design of the above components
Assessment Details

Cycle Test I Surprise Test I Cycle Test II Surprise Test II Model Exam Test Schedule S.No. 1 2 3 Outcomes DATE

: : : : :

10 Marks 7 Marks 10 Marks 8 Marks 15 Marks

TEST Cycle Test - I Cycle Test - II Model Exam

TOPICS Unit I & II Unit III & IV All 5 units

DURATION 2 periods 2 periods 3 Hrs

Students who have successfully completed this course will have full understanding of the following concepts Course outcome To learn The basic functional units, operational concepts and Program outcome An ability to understand the basic functioning of computer. To understand the concepts of addressing modes a

The basic memory operations, addressing modes. Basic ALU functions (operations) Control unit design and memory and its types Input and output processing bus interface I/O interface Detailed Session Plan

To solve various ALU operations. To implement booth algorithm To understand various types of memory concepts I/O processing.

UNIT-I INTRODUCTION Evolution of Computer Systems-Computer Types-Functional units-Basic operational concepts-Bus structures-Memory location and addresses-memory operations- Addressing modes-Design of a computer system-Instruction and instruction sequencing, RISC versus CISC Sessi Time Teaching on Topics to be covered Ref Testing Method (min) Method No. Evolution of Computer Systems Group discussion 1 50 1,2 PPT Quiz Computer Types Objective type test 2 50 1,2 PPT Quiz 3 Functional units 50 1 PPT Quiz Basic operational concepts, Bus structures Quiz 4 50 1 PPT 5 6 7 8 9 RISC versus CISC Memory location and addresses-memory operations Addressing modes Design of a computer system Instruction and instruction sequencing 50 50 50 50 50 1,3 1,3 2 1,3 1,3 PPT PPT PPT PPT PPT Quiz Quiz Objective type test Quiz, Assignment Group discussion Group discussion

UNIT-II CENTRAL PROCESSING UNIT Introduction-Arithmetic Logic Unit - Fixed point arithmetic, floating point arithmetic-Execution of a complete instruction-Basic concepts of pipelining Introduction-Arithmetic Logic Unit Quiz 10 50 1,2 PPT Fixed point arithmetic Quiz 11 50 1,2 PPT Brain storming Fixed point arithmetic Quiz 12 50 1,2 PPT Surprise Test Floating point arithmetic Group discussion 13 50 1,2 PPT Quiz Floating point arithmetic Group discussion, Quiz 14 50 1,2 PPT Floating point arithmetic Quiz, Assignment 15 50 1,2 PPT Execution of a complete Quiz 16 50 1,2 PPT instruction 17 Basic concepts of pipelining 50 1,2 PPT Quiz

18 Basic concepts of pipelining 50 1,2 PPT Quiz UNIT-III CONTROL UNIT DESIGN Introduction-Control Transfer-Fetch cycle - Instruction Interpretation & Execution - Hardwired control Microprogrammed control

Introduction-Control Transfer 19 20 21 22 23 24 25 26 27 Fetch cycle Fetch cycle Instruction Interpretation & Execution Instruction Interpretation & Execution Hardwired control Hardwired control Microprogrammed control Microprogrammed control 50 50 50 50 50 50 50 50 50 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2,3 BB,PPT BB,PPT BB,PPT BB,PPT BB,PPT BB,PPT BB,PPT BB,PPT BB,PPT

Quiz Group discussion Objective type test Quiz Group discussion Quiz Quiz Surprise Test Quiz Group discussion Quiz Quiz Group discussion Quiz Quiz Brain storming

UNIT-IV MEMORIES AND SUBSYSTEMS Semiconductor memory - Static and Dynamic -Associative memory- Cache memory- Virtual memorySecondary memories-Optical magnetic tape & magnetic disks & controllers Semiconductor memory- Static and Group discussion 28 50 1,2,3 BB Dynamic memory Assignment Static and Dynamic memory Group discussion 29 50 1,2,3 BB Quiz Associative memory Group discussion 30 50 1,2,3 BB Assignment Associative memory Group discussion 31 50 1,2,3 BB Assignment Cache memory Objective type test 32 50 1,2,3 BB Quiz Group discussion Virtual memory Quiz 33 50 1,2,3 BB Group discussion 34 35 36 Secondary memories-Optical magnetic tape Magnetic disks & controllers Magnetic disks & controllers 50 50 50 1,2,3 1,2,3 1,2,3 BB BB BB Objective type test Objective type test Quiz Group discussion

UNIT-V I/O PROCESSING Introduction-Data transfer techniques- Bus Interface- I/O Channel-I/O Processor, I/O devices -Direct memory access. 37 38 39 40 41 Introduction-Data transfer techniques Bus Interface I/O Channel I/O Processor I/O Processor 50 50 50 50 50 1,2 1,2 1,2 1,2 2,3 BB BB BB BB BB Group discussion Objective type test Brain storming Brain storming Surprise test

42 43 44 45

I/O devices I/O devices Direct memory access. Direct memory access. BB Black Board PP Power Point

50 50 50 50

2,3 2,3 1,2 1,2

BB BB BB BB

Quiz Assignment Assignment Brain storming Brain storming